JPH0319373A - Formation of ferroelectric thin film - Google Patents
Formation of ferroelectric thin filmInfo
- Publication number
- JPH0319373A JPH0319373A JP1153997A JP15399789A JPH0319373A JP H0319373 A JPH0319373 A JP H0319373A JP 1153997 A JP1153997 A JP 1153997A JP 15399789 A JP15399789 A JP 15399789A JP H0319373 A JPH0319373 A JP H0319373A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- ferroelectric thin
- ferroelectric
- forming
- instance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 32
- 230000015572 biosynthetic process Effects 0.000 title 1
- 238000000034 method Methods 0.000 claims abstract description 23
- 238000004544 sputter deposition Methods 0.000 claims abstract description 8
- 239000010408 film Substances 0.000 claims description 15
- 238000010438 heat treatment Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 2
- 229910052760 oxygen Inorganic materials 0.000 claims 2
- 239000001301 oxygen Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 abstract description 13
- 230000005621 ferroelectricity Effects 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract description 4
- 239000002253 acid Substances 0.000 abstract description 2
- 229910003781 PbTiO3 Inorganic materials 0.000 abstract 1
- 229910020698 PbZrO3 Inorganic materials 0.000 abstract 1
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 230000015654 memory Effects 0.000 description 11
- 238000000137 annealing Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Physical Vapour Deposition (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
「産業上の利用分野]
本発明は、強誘電体を用いた,強誘電体メモj,特に電
気的に書き換え可能な不揮発性メモリの製造方法、特に
強誘電体薄膜の形成方法に関する6のである。[Detailed Description of the Invention] "Industrial Application Field" The present invention relates to a method for manufacturing a ferroelectric memo using a ferroelectric, particularly an electrically rewritable nonvolatile memory, and particularly a method for manufacturing a ferroelectric thin film. 6 regarding the method of forming.
〔発明の眼要1
本発明は、強誘電体薄膜の形成方1去において強請電I
,t膜を形成する工程と、強誘電体薄摸をIijiフL
のパターンにエッチングする工程と,所定のパターンに
形成した後に熱処理をする工程とすることにより、強誘
電体薄膜の特性に優れ、かつクラソクの発生がない強誘
電体薄膜を得るようにしたちのである.
[従来の技術]
従来の半導体不揮発性メモリとしては,絶縁ゲート中の
トラ・ンブまたは冫平遊ゲート(こシリコン基板からの
電荷を注入することによりシリコン基板の表面ポテンシ
ャルが変調される現象を用いたM I S 型トランジ
スタが一般に使用されておりIEPROM(紫外線消去
型不揮発性メモリ)やEIEPROM(電気的書き換え
可能型不揮発性メモ1)などとして実用化されている。[Aspects of the Invention 1] The present invention provides a method for forming a ferroelectric thin film.
, the process of forming the t-film and the ferroelectric thin model.
By performing an etching process to form a pattern and a heat treatment process after forming a predetermined pattern, we are able to obtain a ferroelectric thin film that has excellent properties and does not cause cracking. .. [Prior art] Conventional semiconductor non-volatile memory uses transistors in insulated gates or flat gates (this uses a phenomenon in which the surface potential of the silicon substrate is modulated by injecting charge from the silicon substrate). M I S type transistors are commonly used and have been put into practical use as IEPROMs (ultraviolet erasable nonvolatile memories), EIEPROMs (electrically rewritable nonvolatile memories), and the like.
[発明が解決しようとする課題]
しかしこれらの不揮発性メモリは、清報の書き換え電圧
が、通常約20V@後と高いことや,害き換え時間が非
常に長い(例えばEEFROMの場合数十msec)な
どの欠点を有す.また、情÷];の書き換え回数が、約
10@回程度であり,非′11!に少なく、繰り返し使
用する場合には問題が多し).
電気的に分極が反転可能である強誘電体を用いた、不揮
発性メモリについては,書き込み時間と読み出し時間が
原理的にほぼ同じであり、また電源を切って6分極は保
持されるため、理悲的な不揮発性メモリとなる可能性を
有する。このような強誘電体を用いた不揮発性メモリに
ついては,例えば米国特許4149302の様に、シリ
コン基{ル上に強誘電体からなるキャパシタを集積した
J,jIj造や、米国特許3832700のようにM
I S ’rA[・ランジスクのゲート部分に強誘電体
膜を配置した不揮発性メモリなどの提案がなされている
6また、最近では、第3図のようなMOS型半導(本装
置に積層した構造の不揮発性メモリがIEDM87pp
、850−851に提案されてる。第3図において,3
01はP型Si基板であり、302は素子分離用のLO
GOS酸化膜、303はソスとなるN型拡敗層であり,
304はドレイノとなるN型拡敗層である。305はゲ
ートN 1%であり、306は層間絶縁膜である。30
8が強誘電体膜であり,電極308と309により挟ま
れ、キャパシタを構成している.310は第2層間絶縁
膜であり、311が配線電極となるA1である.強誘電
体薄膜として例えばPZTを使用した場合、強誘電性を
得るためには結晶構造としで、ペロブス力イト構造とす
る必要がある。ぺロブスカイト構造を得るためには、例
えば強誘電体河膜の形成方法としてスパッタリング法を
使った場合,基tFj 濡度を500℃以上に上げるか
、または低温でスパッタした後、500″C以上でアニ
ルする方法がよくとられる.このように例えばスパノク
リング法により強誘電体薄膜を形成した後:ニアニール
した場合には強誘電体薄膜と基板である例えばSi基板
との熱膨張係数の違いにより、アニールした後にクラッ
クが発生するという課題を有する.そこで本発明はこの
ような課題を解沃するもので,その目的とする所は,ク
ラックの発士がなく強誘電体性に優れた強誘電体薄膜の
形成方法を提供する所にある.
[課題を解決するための千段1
本発明の強誘電体薄膜の形成方法は,強誘電体膜を形成
する工程と、強誘電体薄膜の形成後、所定のパターンに
エンチングする工程と、その後声九処理をする工程とし
たことを特徴とする。[Problems to be solved by the invention] However, in these non-volatile memories, the voltage for rewriting information is usually as high as about 20 V, and the rewriting time is very long (for example, in the case of EEFROM, it takes several tens of milliseconds). ) and other disadvantages. Also, the number of rewrites of information ÷ ]; is about 10 @ times, which is not '11! However, there are many problems when using it repeatedly). For non-volatile memories that use ferroelectric materials whose polarization can be electrically reversed, the write time and read time are in principle almost the same, and the six polarizations are maintained even when the power is turned off, so it is logical that It has the potential to become a tragic non-volatile memory. Regarding nonvolatile memories using such ferroelectric materials, there are, for example, U.S. Pat. M
Proposals have been made for non-volatile memories in which a ferroelectric film is placed on the gate of I S 'rA[・randisk. The non-volatile memory structure is IEDM87pp.
, 850-851. In Figure 3, 3
01 is a P-type Si substrate, and 302 is an LO for element isolation.
The GOS oxide film 303 is an N-type diffusion layer that becomes a sos.
304 is an N-type expanding layer that becomes Draino. 305 is a gate N1%, and 306 is an interlayer insulating film. 30
8 is a ferroelectric film, which is sandwiched between electrodes 308 and 309 to form a capacitor. 310 is a second interlayer insulating film, and 311 is A1 which becomes a wiring electrode. When PZT is used as a ferroelectric thin film, for example, in order to obtain ferroelectricity, it is necessary to have a crystal structure and a perovskite structure. In order to obtain a perovskite structure, for example, when sputtering is used as a method for forming a ferroelectric film, the wetness of the base tFj must be increased to 500°C or higher, or sputtering at a low temperature and then sputtering at 500"C or higher is required. In this way, after forming a ferroelectric thin film by the spanokling method, for example, if near annealing is performed, due to the difference in thermal expansion coefficient between the ferroelectric thin film and the substrate, for example, a Si substrate, annealing may occur. Therefore, the present invention solves this problem, and its purpose is to create a ferroelectric thin film that does not cause cracks and has excellent ferroelectric properties. The present invention provides a method for forming a ferroelectric thin film. It is characterized by a step of enching to a predetermined pattern, and a step of subsequently performing voice nine processing.
[実 施 例1
第1図は,本発明の半導体装{1tの一実施例にljj
,.ける主要工程図である。以下、第1図に従い、本弁
明の強誘電体薄膜の形成方法を説明する。[Example 1] Figure 1 shows an example of the semiconductor device {1t} of the present invention.
、. This is the main process diagram. Hereinafter, a method for forming a ferroelectric thin film according to the present invention will be explained with reference to FIG.
(第1図(a) ) 1 0 1は基板となる{列え
ばSi基板である。+02は基板と強誘電体薄膜を分離
する絶縁膜であり、例えば酸化膜をI LI ITI
If三1il2する。103は強誘電体薄膜の下部に形
成される下部電極であり、例えばPtをIOOOA形成
する。(FIG. 1(a)) 1 0 1 is a substrate (if it is arranged in a row, it is a Si substrate). +02 is an insulating film that separates the substrate and the ferroelectric thin film; for example, an oxide film is
If31il2. A lower electrode 103 is formed under the ferroelectric thin film, and is made of, for example, Pt IOOOA.
(第1図(b)) 次に強誘電体,コリni 1o 4
を{t)1λばスバック法により約5 0 0 0 A
形成する。強講電体としては例えばPZTを用い、ター
ゲソ1・とじては例えばP b Z r O 3 /
P b T i O 3 =52%/48%にPbOを
5mo l%添加したクゲットを用いる。スバッタ条件
としてはAr/02雰囲気中で例えば、200Wて、基
板温度としては例えば、常(品から300℃の間でスパ
ッタを行なう.
(第1図(C)) 次にHCLとHFの混酸で所定のパ
ターン105にエッチングする.そしてこの状態で、例
えば02雰囲気中で、550℃、1時間の熱処理を行な
う.この熱処理によりスバッタされたPZTはペロブス
力イト構造となり強誘電性を示すようになる。そして、
所定のパターンに形成した後にアニールを行なうため,
クラックは発生しない。(Figure 1(b)) Next, ferroelectric material, Cori ni 1o 4
{t) About 5 0 0 0 A by 1λ Subback method
Form. For example, PZT is used as the strong electrical conductor, and for example, P b Z r O 3 /
A cugette prepared by adding 5 mol % of PbO to P b T i O 3 =52%/48% is used. The sputtering conditions are, for example, 200 W in an Ar/02 atmosphere, and the substrate temperature is, for example, between 300° C. (Fig. 1 (C)). Next, a mixed acid of HCL and HF is used. It is etched into a predetermined pattern 105. Then, in this state, heat treatment is performed at 550° C. for 1 hour in, for example, 02 atmosphere. Through this heat treatment, the spattered PZT becomes a perovskite structure and exhibits ferroelectricity. .and,
Because annealing is performed after forming a predetermined pattern,
No cracks occur.
クラックの発生とパターンの大きさについて{炙討した
ところ、第2図のように、下部電極201〜203上に
強誘電体薄膜を形成する場合、第2図(a)の様に、強
誘電体薄膜204〜206を独立に形成してやればクラ
ックは発生しないことが分かった.さらに、第2図(b
)の様に,強誘電体薄膜を下部電極に対し一片を繋げて
やって6クラックは発生しないこと6分かった.そして
、一片の長さ208を10um以下にしてやれば他片が
繋がっていて6良いこともわかった.以上の説明におい
ては強誘電体薄膜部分についてのみ述べたため、基板と
してはSiMmばかりでなく他の基板で6良い。さらに
強誘電体薄膜と同時に能動素子として例えばMos+−
ランジスタを集積してち良いことはいうまでも無い。When we investigated the occurrence of cracks and the size of the pattern, we found that when forming a ferroelectric thin film on the lower electrodes 201 to 203 as shown in Fig. 2, It was found that if the body thin films 204 to 206 were formed independently, no cracks would occur. Furthermore, Figure 2 (b
), it was found that no cracks were generated by connecting one piece of the ferroelectric thin film to the lower electrode. We also found that if we made the length of one piece 208 less than 10 um, the other pieces would be connected and 6 would be better. In the above description, only the ferroelectric thin film portion has been described, so the substrate may be not only SiMm but also other substrates. Furthermore, at the same time as the ferroelectric thin film, as an active element, for example, Mos+-
It goes without saying that it is good to integrate transistors.
r発明の効果〕
以上述べてきた様に、本発明によれば、強誘電体薄膜の
形成方l去において,強誘電体膜を形成する工程と、所
定のパターンにエッチングする工程と、熱処理をする工
程としたため、強誘電性に優れ,かつ、クラックの発生
のない強誘電体薄膜の形成が可能となるという効果を有
する。[Effects of the Invention] As described above, according to the present invention, in the method of forming a ferroelectric thin film, a step of forming a ferroelectric film, a step of etching into a predetermined pattern, and a heat treatment are performed. This process has the effect of making it possible to form a ferroelectric thin film that has excellent ferroelectricity and is free from cracks.
第1図(a)〜(C)は本発明の強誘電体薄膜の形成方
法の主要工程図であり、第2図(a)(b)は本発明の
強誘電体薄膜の所定パターンを示す図である。第3図は
従来の強誘電体メモリーの断面図である。
101.301・・・Si基板
102 、 302 ・
104 ・ ・ ・ ・ ・
1 0 5 ・ ・ ・ ・ ・
103、 201.
2 0 4
・・素子分iiiI II@
・・強誘電体薄膜
・・所定パターン
202.203
・・・下部電極
205、206、207
・・・強誘電体薄膜の所定バタ
ン
・所定パターンの長さ
・・N型拡敗層
・・ゲート電極
・・・強誘電体膜
・・・AI電極
・一層間絶縁膜
・・・下部電極
・・上部電極
以上
h 1 園 (α)
2 0 8
303、 304 ・
305 ・ ・ ・ ・
308 ・ ・ ・
311 ・ ・ ・ ・
306. 310
307 ・ ・ ・
309 ・ ・ ・ ・
so5FIGS. 1(a) to (C) are main process diagrams of the method for forming a ferroelectric thin film of the present invention, and FIGS. 2(a) and (b) show predetermined patterns of the ferroelectric thin film of the present invention. It is a diagram. FIG. 3 is a cross-sectional view of a conventional ferroelectric memory. 101.301...Si substrate 102 , 302 ・ 104 ・ ・ ・ ・ 1 0 5 ・ ・ ・ ・ 103, 201. 2 0 4...Element portion iii II@...Ferroelectric thin film...Predetermined pattern 202.203...Lower electrodes 205, 206, 207...Predetermined pattern/length of ferroelectric thin film...・N-type spreading layer・Gate electrode・Ferroelectric film・AI electrode・Single-layer insulating film・Bottom electrode・Higher than upper electrode h 1 (α) 2 0 8 303, 304 ・305 ・ ・ ・ ・ 308 ・ ・ ・ 311 ・ ・ ・ ・ 306. 310 307 ・ ・ ・ 309 ・ ・ ・ ・ so5
Claims (5)
、 熱処理をする工程とを含むことを特徴とする強誘電体薄
膜の形成方法。(1) A method for forming a ferroelectric thin film, comprising the steps of forming a ferroelectric film, etching the ferroelectric thin film into a predetermined pattern, and performing heat treatment.
であることを特徴とする請求項1記載の強誘電体薄膜の
形成方法。(2) The method for forming a ferroelectric thin film according to claim 1, wherein the step of forming the ferroelectric film is sputtering.
雰囲気で、かつ500℃以上であることを特徴とする請
求項1記載の強誘電体薄膜の形成方法。(3) The method for forming a ferroelectric thin film according to claim 1, wherein the heat treatment step is performed in an atmosphere containing at least oxygen and at a temperature of 500° C. or higher.
10um以下であることを特徴とする請求項1記載の強
誘電体薄膜の形成方法。(4) The method for forming a ferroelectric thin film according to claim 1, wherein the size of at least one piece of the predetermined pattern is 10 um or less.
であり、かつ、前記熱処理をする工程が、少なくとも酸
素を含む雰囲気で、かつ500℃以上であり、かつ、前
記所定のパターンの少なくとも一片の大きさが10um
以下であることを特徴とする請求項1記載の強誘電体薄
膜の形成方法。(5) The step of forming the ferroelectric film is sputtering, and the heat treatment step is performed in an atmosphere containing at least oxygen and at a temperature of 500° C. or higher, and Size is 10um
The method of forming a ferroelectric thin film according to claim 1, characterized in that:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1153997A JPH0319373A (en) | 1989-06-16 | 1989-06-16 | Formation of ferroelectric thin film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1153997A JPH0319373A (en) | 1989-06-16 | 1989-06-16 | Formation of ferroelectric thin film |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0319373A true JPH0319373A (en) | 1991-01-28 |
Family
ID=15574659
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1153997A Pending JPH0319373A (en) | 1989-06-16 | 1989-06-16 | Formation of ferroelectric thin film |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0319373A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0424958A (en) * | 1990-05-15 | 1992-01-28 | Mitsubishi Materials Corp | Structure of capacitive element |
WO1992002045A1 (en) * | 1990-07-20 | 1992-02-06 | Seiko Epson Corporation | Method for manufacturing semiconductor device |
JP2008205235A (en) * | 2007-02-21 | 2008-09-04 | Fujitsu Ltd | Semiconductor device and manufacturing method therefor |
-
1989
- 1989-06-16 JP JP1153997A patent/JPH0319373A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0424958A (en) * | 1990-05-15 | 1992-01-28 | Mitsubishi Materials Corp | Structure of capacitive element |
WO1992002045A1 (en) * | 1990-07-20 | 1992-02-06 | Seiko Epson Corporation | Method for manufacturing semiconductor device |
JP2008205235A (en) * | 2007-02-21 | 2008-09-04 | Fujitsu Ltd | Semiconductor device and manufacturing method therefor |
US8338249B2 (en) | 2007-02-21 | 2012-12-25 | Fujitsu Semiconductor Limited | Semiconductor device and method for manufacturing the same having improved polarization reversal characteristic |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100388497C (en) | Metal thin film and method of manufacturing the same, dielectric capacitor and method of manufacturing the same, and semiconductor memory device | |
JPH09162362A (en) | Nonvolatile semiconductor storage device | |
JPH0437170A (en) | Manufacture of semiconductor device | |
JPH10341002A (en) | Ferroelectric transistor, semiconductor storage, and handling method and manufacture of ferroelectric transistor | |
KR100353804B1 (en) | A method for forming ferroelectric capacitor in semiconductor device | |
KR100382719B1 (en) | Semiconductor device comprising ferroelectric capacitor and method of manufacturing the same | |
JP2002026287A (en) | METHOD OF MANUFACTURING Fe RAM ELEMENT | |
JPH02232973A (en) | Semiconductor device | |
JPH10321809A (en) | Semiconductor storage element manufacturing method | |
JPH0319373A (en) | Formation of ferroelectric thin film | |
JP2001237402A (en) | Structured metal oxide containing layer, and method of manufacturing semiconductor structure element | |
JPH02208978A (en) | Semiconductor device | |
JPH03142973A (en) | Semiconductor storage device | |
JPH02249278A (en) | Manufacture of ferroelectric film | |
JPH0823073A (en) | Ferroelectric thin capacitor and manufacture thereof | |
JPH09321237A (en) | Non-volatile semiconductor storage device having ferroelectric film, capacitor having ferroelectric film and its manufacture | |
JP3120477B2 (en) | Semiconductor device | |
JPH10256495A (en) | Nonvolatile semiconductor storage device | |
JP3663575B2 (en) | Method for modifying ferroelectric film and method for manufacturing capacitive element | |
KR0165352B1 (en) | Process of fabricating ferroelectric capacitor | |
JP2000223667A (en) | Ferroelectric memory, fabrication thereof and noncontact ic card | |
JPH0997877A (en) | Semiconductor storage device and its manufacture | |
JP2002329843A (en) | Ferroelectric transistor type nonvolatile storage element and its manufacturing method | |
JP3872917B2 (en) | Manufacturing method of semiconductor device | |
JPH05211307A (en) | Nonvolatile memory cell |