JPH02232973A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02232973A JPH02232973A JP1054222A JP5422289A JPH02232973A JP H02232973 A JPH02232973 A JP H02232973A JP 1054222 A JP1054222 A JP 1054222A JP 5422289 A JP5422289 A JP 5422289A JP H02232973 A JPH02232973 A JP H02232973A
- Authority
- JP
- Japan
- Prior art keywords
- ferroelectric film
- semiconductor device
- electrode
- silicide
- diffusion layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000009792 diffusion process Methods 0.000 claims abstract description 20
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 18
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 238000002844 melting Methods 0.000 claims abstract description 9
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 8
- 230000008018 melting Effects 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 229910003781 PbTiO3 Inorganic materials 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 18
- 230000015654 memory Effects 0.000 description 13
- 239000011229 interlayer Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000002801 charged material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、強誘電体を用いた、電気的に書き換え可能な
不揮発性メモリの構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of an electrically rewritable nonvolatile memory using a ferroelectric material.
［発明の概要］
本発明は、強誘電体膜を用いた、不揮発性メモリの構造
において、半導体基板上に形成されたソース，ドレイン
となる高濃度拡散層の表面に高融点金属を主成分とした
シリサイドを形成し、このシリサイド上に強誘電体膜を
直接形成するようにしたため、工程増が少なく、かつ、
結晶性の優れた強誘電体膜を得るようにしたものである
。[Summary of the Invention] The present invention provides a structure of a non-volatile memory using a ferroelectric film, in which a refractory metal is the main component on the surface of a highly concentrated diffusion layer that is formed on a semiconductor substrate and serves as a source and a drain. Since the ferroelectric film is formed directly on this silicide, the number of steps required is small, and
This is to obtain a ferroelectric film with excellent crystallinity.
［従来の技術コ
従来の半導体不揮発性メモリとしては、絶縁ゲート中の
トラップまたは浮遊ゲートにシリコン基板からの電荷を
注入することによりシリコン基板の表面ポテンシャルが
変調される現象を用いた、ＭｌＳ型トランジスタが一般
Ｋ使用されており、ＫＰＲＯＭ（紫外線消去型不揮発性
メモリ）やＥＥＰＲＯＭ（電気的書き換え可能型不揮発
性メモリ）などとして実用化されている。[Conventional technology] Conventional semiconductor non-volatile memory uses MlS type transistors, which utilize a phenomenon in which the surface potential of a silicon substrate is modulated by injecting charge from a silicon substrate into a trap or floating gate in an insulated gate. is commonly used and has been put into practical use as KPROM (ultraviolet erasable nonvolatile memory) and EEPROM (electrically rewritable nonvolatile memory).
［発明が解決しようとする課題］
しかしこれらの不揮発性メモリは、情報の書き換え電圧
が、通常約２０７前後と高いことや、書き換え時間が非
常に長い（例えばＫＥＦＲＯＭの場合数十ｍ ｓｅｃ）
などの欠点を有す。また、情報の書き換え回数が、約１
０５回程度であり、非常に少な《、繰り返し使用する場
合Ｋは問題が多い。[Problems to be Solved by the Invention] However, these nonvolatile memories have a high information rewriting voltage, usually around 207, and a very long rewriting time (for example, several tens of msec in the case of KEFROM).
It has the following disadvantages. Also, the number of times information is rewritten is approximately 1
It is about 05 times, which is very small. If it is used repeatedly, K has many problems.
電気的に分極が反転可能である強訪電体を用いた、不揮
発性メモリについては、書き込み時間と読み出し時間が
原理的にほぼ同じであり、また電源を切っても分極は保
持されるため、理想的な不揮発性メモリとなる可能性を
有する。このような強誘電体を用いた不揮発性メモリに
ついては、例えば米国特許４１４９３０．２の様に、シ
リＦン基板上Ｋ強誘電体からなるキャパシタを集積した
構′造や、米国特許５８５２７００のようにＭＩＳ型ト
ランジスタのゲート部分に強誘電体膜を配置した不揮発
性メモリなどの提案がなされている。また、最近では、
第３図のようなＭＯＳ型半導体装置に積層した構造の不
揮発性メモリが工ＫＤＭｔ８７ｐｐ・８５０−８５１に
提案されている。第３図において、５０１はＰ型Ｓ１基
板であり、３０２は素子分離用のＬＯＯＯＳ酸化膜、３
０３はソースとなるＮ型拡散層であり、３０４はドレイ
ンとなるＮ型拡散層である。６０５はゲート電極であり
、３０６は眉間絶縁膜である。６０８が強誘電体膜であ
り、電極３０８と３０９により挾まれ、キャパシタを構
成している。３１０は第２層間絶縁膜であり、３１１が
配線電極となるＡｔである。このようにＭＯＳ型半導体
装置の上部Ｋ積層した構造では素子面積はそれほど増え
ないが、製造工程が大幅に増え（通常の半導体装置に対
して、下部電極形成、強誘電体膜形成、上部電極形成、
第２層間膜形成が増える）、仮に特性的に満足がいく強
誘電体膜が得られても、製造工程が、長くなるため、コ
ストが高くなるという課題を有する。そこで本発明はこ
のような課題を解決するもので、その目的とする所は、
強誘電体膜を用いても工程の増加の少な《低コストな、
かつ強誘電体膜の結晶性に優れた半導体装置、特Ｋ不揮
発性メモリを提供する所にある。For non-volatile memory that uses a strongly charged material whose polarization can be electrically reversed, the write time and read time are basically the same, and the polarization is maintained even when the power is turned off. It has the potential to become an ideal nonvolatile memory. Regarding non-volatile memories using such ferroelectric materials, for example, there is a structure in which capacitors made of K ferroelectric material are integrated on a silicon F substrate as in U.S. Pat. Recently, proposals have been made for nonvolatile memories in which a ferroelectric film is disposed at the gate of an MIS transistor. Also, recently,
A nonvolatile memory having a structure stacked on a MOS type semiconductor device as shown in FIG. 3 has been proposed in KDMt87pp.850-851. In FIG. 3, 501 is a P-type S1 substrate, 302 is a LOOOS oxide film for element isolation, and 3
03 is an N-type diffusion layer that becomes a source, and 304 is an N-type diffusion layer that becomes a drain. 605 is a gate electrode, and 306 is an insulating film between the eyebrows. A ferroelectric film 608 is sandwiched between electrodes 308 and 309 to form a capacitor. 310 is a second interlayer insulating film, and 311 is At which becomes a wiring electrode. In this way, the device area does not increase significantly in the upper K layered structure of a MOS type semiconductor device, but the manufacturing steps are significantly increased (compared to a normal semiconductor device, it requires lower electrode formation, ferroelectric film formation, upper electrode formation). ,
Even if a ferroelectric film with satisfactory characteristics can be obtained, the manufacturing process becomes longer and the cost becomes higher. Therefore, the present invention is intended to solve such problems, and its purpose is to:
Even if a ferroelectric film is used, there is little increase in process steps (low cost,
The present invention also provides a semiconductor device and a special nonvolatile memory with excellent crystallinity of a ferroelectric film.
［課題を解決するための手段］
本発明の半導体装置は、半導体基板上に形成されたソー
ス，ドレインとなる高濃度拡散層の表面に高融点金属を
主成分としたシリサイドを形成しシリサイド上に直接強
訪電体膜が形成されていることを特徴とする。[Means for Solving the Problems] The semiconductor device of the present invention forms silicide containing a high melting point metal as a main component on the surface of a highly concentrated diffusion layer that is formed on a semiconductor substrate and serves as a source and drain. It is characterized by a direct ferroelectric film formed thereon.
［実施例］
第１図は、本発明の半導体装置の一実施例に於ける主要
断面図である。以下、第１図Ｋ従い、本発明の半導体装
置を説明する。ここでは説明の都合上８１基板を用い、
Ｎチャンネルトランジスタを用いた例Ｋつき説明する。[Embodiment] FIG. 1 is a main sectional view of an embodiment of the semiconductor device of the present invention. The semiconductor device of the present invention will be described below with reference to FIG. 1K. For convenience of explanation, 81 board is used here.
An example K using an N-channel transistor will be explained.
１０１はＰ型Ｓ１基板であり、例えば２００ｈｍ．ａｎ
の比抵抗のウェハな用いる。１０２は素子分離用の絶縁
膜であり、例えば、従来技術であるＬＯＯＯＳ法により
酸化膜を６００ＯＡ形成する１０３はソースとなるＮ型
拡散層で，あり、例えばリンを８ ０ＫｅＶ５Ｋ１ ５
ｃｆｎ−２イオン注入することにより形成する。１０４
はドレインとなるＮ型拡敗層であり、１０３と同時に形
成する。１０５はゲート電極であり，例えばリンでドー
プされたボリＳ１を用いる。１１１，１１２，１１３は
それぞれドレイン拡散層上、ゲート電極上、ソース拡散
層上に形成したシリサイドであり、その形成方法として
は、１０５のゲートＮ極、１０３，１０４の高濃度拡散
層を形成後、ゲート電極表面と、拡散層表面を７ツ酸に
よるウェットエッチングで露出後、例えば、Ｔｉ金属を
１ ００ＯＡ全面にスパッタし、８００℃で３０分アニ
ールスルこと罠より８１と反応させシリサイドを形成し
、その後ウェットエッチングにより反応していないＴ１
金属を除去することにより形成する。１０６は層間絶縁
膜であり、例えば気相成長法によりリンガラスを６００
ＯＡ形成する。１０９は１０６の層間絶縁膜に形成した
フンタクトホールであり他の部分においてはく図示せず
）配線電極と、拡散層やボリＳ１とを接続するコンタク
トホールとなる。１０７が強誘電体膜であり、１１３の
シリサイドを介してＮ型高濃度拡散層上に直接形成され
る。強誘電体膜としては、例えばＰｂＴｉＯ，，ＰＺＴ
（ＰｂＺｒＯ，，ＰｂＴｉＯ，，ＰＬＺＴ（Ｌａ，Ｐｔ
＋ＺｒＯ，，ＰｂＴｉＯ，）などを用いる。１日が上部
電極となる例えばＡｔであり、他の部分においては（図
示せず）配線電極となる。101 is a P-type S1 substrate, for example, 200hm. an
The resistivity of the wafer is used. 102 is an insulating film for element isolation, for example, an oxide film of 600 OA is formed by the conventional LOOOS method. 103 is an N-type diffusion layer that becomes a source, and for example, 80 KeV5K15 of phosphorus is formed.
It is formed by implanting cfn-2 ions. 104
is an N-type diffusion layer which becomes a drain, and is formed at the same time as 103. Reference numeral 105 denotes a gate electrode, for example, a phosphor-doped polygon S1 is used. 111, 112, and 113 are silicides formed on the drain diffusion layer, the gate electrode, and the source diffusion layer, respectively, and the method for forming them is as follows: After forming the gate N electrode 105 and the high concentration diffusion layers 103 and 104. After exposing the surface of the gate electrode and the surface of the diffusion layer by wet etching with 7-acid, for example, Ti metal is sputtered on the entire surface with a thickness of 100 OA, annealed at 800° C. for 30 minutes, and reacted with 81 to form silicide. After that, T1 has not reacted due to wet etching.
Formed by removing metal. 106 is an interlayer insulating film, for example, 600% phosphorus glass is formed by vapor phase growth.
Forms OA. Reference numeral 109 denotes a contact hole formed in the interlayer insulating film 106, which serves as a contact hole for connecting the wiring electrode (not shown) to the diffusion layer and the bulge S1 in other parts. A ferroelectric film 107 is formed directly on the N-type high concentration diffusion layer via the silicide 113. As the ferroelectric film, for example, PbTiO, PZT
(PbZrO,,PbTiO,,PLZT(La,Pt
+ZrO, , PbTiO, ), etc. are used. For example, the first electrode is At, which serves as the upper electrode, and the other portions serve as wiring electrodes (not shown).
第１図において、強誘電体膜を用いたキャパシタについ
ては、下部電極が１１３の高融点金属を主成分としたシ
リサイドとしたため、例えばｐｔを用いた場合、結晶性
の優れた強誘電体膜を得ることが出来た。また高融点金
属であるため、強誘電体膜を形成した後の結晶性の向上
のためのアニ−ルとしても、例えば、９００℃前後まで
可能であり、より結晶性の優れた強誘電体膜の形成が可
能である。In Figure 1, for a capacitor using a ferroelectric film, the lower electrode is made of silicide whose main component is 113, a high melting point metal. I was able to get it. In addition, since it is a high melting point metal, annealing to improve crystallinity after forming a ferroelectric film can be performed up to, for example, around 900°C, resulting in a ferroelectric film with even better crystallinity. It is possible to form
工程の増加は、通常のＭＯＳ型半導体装置の工程に比較
し、１０７の強誘電体膜を形成する工程のみであり、低
コストで強誘電体膜を用いた半導体装置が可能となる。The only increase in the number of steps is the step of forming 107 ferroelectric films compared to the steps for a normal MOS type semiconductor device, making it possible to produce a semiconductor device using ferroelectric films at low cost.
電気的特性Ｋついては、本発明のように下部電極として
高融点金属のシリサイドとしたため、結晶性の向上によ
り、例えば、Ｐｔシリサイドを電極とした場合、情報の
書き換え回数が、金属電極を設げない場合に対し、１０
８回から１０１°回に改善出来た。同様な効果は、ｐｔ
ばかりでなく、Ｍｏ，Ｔｉ，Ｐｔ，Ｗなどの高融点金属
を用いたシリサイドにおいても、程度の違いはあれ、同
様にあクた。Regarding the electrical characteristics K, since the lower electrode is made of silicide of a high melting point metal as in the present invention, the crystallinity is improved, and therefore, for example, when Pt silicide is used as an electrode, the number of times information is rewritten is lower than that without providing a metal electrode. For the case, 10
I was able to improve from 8 times to 101 degrees. A similar effect is pt
Not only that, but silicides using high-melting point metals such as Mo, Ti, Pt, and W were similarly exposed, albeit to different degrees.
次に第２図を用い、本発明の半導体装置の製造方法を説
明する。第２図は本発明の主要工程図である。Next, a method for manufacturing a semiconductor device according to the present invention will be explained using FIG. FIG. 2 is a main process diagram of the present invention.
第２図（α） １０１の８１基板に１０２の素子分離膜
、１０３，１０４のＮ型拡散層、１０５のゲート電極を
形成する。その後、前述したように１１１，１１２，１
１５のシリサイドを拡散層表面，ゲート電極表面に形成
する。その後１０６の層間絶縁戻を形成し、１０９のコ
ンタクトホールな形成する。ここまでは従来技術を用い
ることにより、十分Ｋ構成出来る。FIG. 2(α) An element isolation film 102, N-type diffusion layers 103 and 104, and a gate electrode 105 are formed on a substrate 101 (81). After that, as mentioned above, 111, 112, 1
Silicide No. 15 is formed on the surface of the diffusion layer and the gate electrode. Thereafter, an interlayer insulation layer 106 is formed, and a contact hole 109 is formed. Up to this point, by using the conventional technology, a sufficient K configuration can be achieved.
第２図Ｃｂ） その後、強誘電体膜として例えばＰｂ
ＴｉＯ，をスバッタ法により、約５００ＯＡ形成する。(Fig. 2Cb) After that, as a ferroelectric film, for example, Pb
About 500 OA of TiO is formed by a sputtering method.
スパッタ条件としては、例えば、ガスとしてはＡｒ／＃
素＝９０％／１０％、ターゲットとしては、Ｐｂを５〜
１０％余分に添加したＰｂＴｉＯｓを用い、ＲＦパワー
としては２００Ｗとだ。また、基板温度としては３５０
℃としたその後、６００℃で１時間、Ｎ，雰囲気中でア
二一ルを行ない強誘電体膜の結晶性の改善を行なった。As for the sputtering conditions, for example, the gas is Ar/#
Prime = 90%/10%, as a target, Pb is 5~
It uses 10% extra PbTiOs and has an RF power of 200W. Also, the substrate temperature is 350
After that, annealing was performed at 600° C. for 1 hour in a nitrogen atmosphere to improve the crystallinity of the ferroelectric film.
そして、従来技術である露光法を用いて１０７０強誘電
体膜を所定のパターンに形成した。Then, a 1070 ferroelectric film was formed into a predetermined pattern using a conventional exposure method.
強誘電体膜のエッチングとしては、例えば、塩酸と７ツ
酸の混合液を用いた。強誘電体膜のエッチングはＡｒガ
スを用いたイオンミリングでも良いし、適当な反応性ガ
スを用いたドライエッチングでも良い。For etching the ferroelectric film, for example, a mixed solution of hydrochloric acid and hexachloric acid was used. The ferroelectric film may be etched by ion milling using Ar gas or by dry etching using an appropriate reactive gas.
第２図ＣＣ） 次に、上部電極として、Ａｔを例えば
１μｍスパッタ法により形成する。そして、従来技術で
ある露光技術により１０８の電極パターンを形成する。(FIG. 2 CC) Next, At is formed as an upper electrode by, for example, a 1 μm sputtering method. Then, 108 electrode patterns are formed using conventional exposure technology.
以上のようにして、本発明の半導体装置を得る以上の説
明においては、ＰｂＴｉ０３について説明したが、他の
強誘電体膜、例えばＰＺＴや、ＰＬＺＴを用いても本発
明が適用出来ることは言うまでもない。As described above, the semiconductor device of the present invention is obtained. In the above explanation, PbTiO3 has been explained, but it goes without saying that the present invention can be applied to other ferroelectric films, such as PZT and PLZT. .
また、本発明の趣旨は強誘電体膜を直接高濃度拡散層の
上に形成することであるため、下地の構造に関しては、
第１図で説明したような構造ばかりでな《、ＯＭＯＳ構
造、バイボーラトランジスタを用いた構造．、バイボー
ラ／ Ｏ Ｍ Ｏ Ｓの構造についても本発明が適用出
来ることは言うまでもない。Furthermore, since the purpose of the present invention is to form a ferroelectric film directly on a high concentration diffusion layer, regarding the underlying structure,
Not only the structure explained in Fig. 1, but also the structure using OMOS structure and bibolar transistor. It goes without saying that the present invention can also be applied to the structure of bibolar/OMOS.
［発明の効果コ
以上述べてきた様に、本発明の半導体装置によれば、半
導体基板上に形成されたソース，ドレインとなる高濃度
拡散層の表面に高融点金属を主成分としたシリサイドを
形成し、シリサイド上に直接強誘電体膜を形成するよう
にしたため、工程の増加が少な《、低コストの半導体装
置、特に不揮発性メモリが製造出来、かつ、結晶性の優
れた強誘電体膜の形成が可能となると言う効果を有する[Effects of the Invention] As described above, according to the semiconductor device of the present invention, silicide containing a high melting point metal as a main component is formed on the surface of the high concentration diffusion layer which is formed on the semiconductor substrate and becomes the source and drain. Since the ferroelectric film is formed directly on the silicide, the number of steps is small, and low-cost semiconductor devices, especially non-volatile memories, can be manufactured, and the ferroelectric film has excellent crystallinity. It has the effect of enabling the formation of
第１図は本発明の半導体装置の主要断面図であり、第２
図（α）〜（Ｃ）は本発明の半導体装置の主要工程図で
ある。第３図は従来の半導体装置の主要断面図である。
１０１，３０１・・・・・・８１基板
１０２，３０２・・・・・・素子分離膜１０３，３０３
，１０４，３０４・・・・・・Ｎ型拡散層
１０５，３０５・・・・・・ゲート電極１０６，３０６
・・・−・・層間絶縁膜１０７，３０８・・・・・・強
誘電体膜築 １ 回
８，３１１・・・・・・Ａｔ電極
９・・・・・・コンタクトホール
０・・・・・・Ａｔ電極の大きさ
１，１１２，１１５・・・・・・シリサイ７・・・・・
・下部電極
９・・・・・・上部電極
０・・・・・・第２層間絶縁膜
以FIG. 1 is a main sectional view of the semiconductor device of the present invention, and FIG.
Figures (α) to (C) are main process diagrams of the semiconductor device of the present invention. FIG. 3 is a main cross-sectional view of a conventional semiconductor device. 101, 301...81 Substrate 102, 302... Element isolation film 103, 303
, 104, 304... N-type diffusion layer 105, 305... Gate electrode 106, 306
......Interlayer insulating film 107, 308...Ferroelectric film construction 1 time 8,311...At electrode 9...Contact hole 0...・・At electrode size 1,112,115・・Silicon size 7・・・・
・Lower electrode 9...Top electrode 0...Second interlayer insulating film and beyond
Claims (2)
基板上に集積された半導体装置において、前記半導体基
板上に形成された高濃度拡散層の表面に高融点金属を主
成分としたシリサイドが形成され、前記シリサイド上に
強誘電体膜が形成されていることを特徴とする半導体装
置。(1) In a semiconductor device in which a ferroelectric film is integrated on the same semiconductor substrate on which active elements are formed, a high-melting point metal is used as a main component on the surface of a high concentration diffusion layer formed on the semiconductor substrate. 1. A semiconductor device comprising: silicide; and a ferroelectric film formed on the silicide.
、Ｎｉ金属からなるシリサイドのうちの、いずれかであ
ることを特徴とする請求項１記載の半導体装置。(2) The silicide is Pt, Mo, Ti, W, Ta
, or silicide made of Ni metal.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1054222A JPH02232973A (en) | 1989-03-07 | 1989-03-07 | Semiconductor device |
| KR1019900001323A KR950000156B1 (en) | 1989-02-08 | 1990-02-05 | Semiconductor device |
| DE69021419T DE69021419T2 (en) | 1989-02-08 | 1990-02-08 | Semiconductor memory device with a ferroelectric material. |
| EP90102489A EP0389762B1 (en) | 1989-02-08 | 1990-02-08 | Memory semiconductor device employing a ferroelectric substance |
| US07/723,681 US5099305A (en) | 1989-02-08 | 1991-05-30 | Platinum capacitor mos memory having lattice matched pzt |
| HK107697A HK107697A (en) | 1989-02-08 | 1997-06-26 | Memory semiconductor device employing a ferroelectric substance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1054222A JPH02232973A (en) | 1989-03-07 | 1989-03-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02232973A true JPH02232973A (en) | 1990-09-14 |
Family
ID=12964509
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1054222A Pending JPH02232973A (en) | 1989-02-08 | 1989-03-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02232973A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1992002046A1 (en) * | 1990-07-24 | 1992-02-06 | Seiko Epson Corporation | Method of manufacturing semiconductor device |
| WO1992006498A1 (en) * | 1990-09-28 | 1992-04-16 | Seiko Epson Corporation | Semiconductor device |
| WO1992006499A1 (en) * | 1990-09-28 | 1992-04-16 | Seiko Epson Corporation | Semiconductor device |
| US5293510A (en) * | 1990-04-24 | 1994-03-08 | Ramtron International Corporation | Semiconductor device with ferroelectric and method of manufacturing the same |
| US5902131A (en) * | 1997-05-09 | 1999-05-11 | Ramtron International Corporation | Dual-level metalization method for integrated circuit ferroelectric devices |
| US6281536B1 (en) | 1998-04-08 | 2001-08-28 | Nec Corporation | Ferroelectric memory device with improved ferroelectric capacity characteristic |
| US6384440B1 (en) | 1999-11-10 | 2002-05-07 | Nec Corporation | Ferroelectric memory including ferroelectric capacitor, one of whose electrodes is connected to metal silicide film |
| US6940741B2 (en) | 1990-08-03 | 2005-09-06 | Hitachi, Ltd. | Semiconductor memory device and methods of operation thereof |
| US9846664B2 (en) | 2010-07-09 | 2017-12-19 | Cypress Semiconductor Corporation | RFID interface and interrupt |
-
1989
- 1989-03-07 JP JP1054222A patent/JPH02232973A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5293510A (en) * | 1990-04-24 | 1994-03-08 | Ramtron International Corporation | Semiconductor device with ferroelectric and method of manufacturing the same |
| WO1992002046A1 (en) * | 1990-07-24 | 1992-02-06 | Seiko Epson Corporation | Method of manufacturing semiconductor device |
| US6940741B2 (en) | 1990-08-03 | 2005-09-06 | Hitachi, Ltd. | Semiconductor memory device and methods of operation thereof |
| WO1992006498A1 (en) * | 1990-09-28 | 1992-04-16 | Seiko Epson Corporation | Semiconductor device |
| WO1992006499A1 (en) * | 1990-09-28 | 1992-04-16 | Seiko Epson Corporation | Semiconductor device |
| US5902131A (en) * | 1997-05-09 | 1999-05-11 | Ramtron International Corporation | Dual-level metalization method for integrated circuit ferroelectric devices |
| US6281536B1 (en) | 1998-04-08 | 2001-08-28 | Nec Corporation | Ferroelectric memory device with improved ferroelectric capacity characteristic |
| US6384440B1 (en) | 1999-11-10 | 2002-05-07 | Nec Corporation | Ferroelectric memory including ferroelectric capacitor, one of whose electrodes is connected to metal silicide film |
| US9846664B2 (en) | 2010-07-09 | 2017-12-19 | Cypress Semiconductor Corporation | RFID interface and interrupt |
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