JPH02288368A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide excellent integration, productivity by forming at least one of electrodes for holding a ferrodielectric film in the same mask pattern as that of the ferrodielectric film. CONSTITUTION:A field oxide film 12 is grown, for example, on a P-type silicon substrate 11, a gate insulating electrode 13 and a gate electrode 14 are formed, phosphorus is ion implanted to form N-type impurity layers 15, 16, an interlayer insulating film 17 is formed, and a contact hole is opened. Then, poly-Si is vapor grown, impurity is doped, a ferrodielectric film 19 is sputtered, then heat treated, poly-Si is again vapor grown, and impurity is doped. Thereafter, with photoresist 30 as a mask the film 19 the poly-Si to become lower electrodes 20, 18 are dry etched in a predetermined shape continuously in the same chamber. Thus, since the ferrodielectric film, the lower or upper electrode are formed in a self-alignment manner, the control of size can be facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device using a ferroelectric film, and particularly to a method for manufacturing an electrically rewritable nonvolatile memory.

[Conventional technology]

MIS type transistors are commonly used as conventional semiconductor non-volatile memories, and have been put into practical use as EFROM (ultraviolet erasable non-volatile memory), EEPROM (electrically rewritable non-volatile memory), etc.; Problems include the high voltage of about 20 V and the long rewriting time. Therefore, recently, non-volatile memories have been proposed that use ferroelectric films whose polarization can be electrically reversed, and whose writing and reading times are essentially the same, and whose polarization is maintained even when the power is turned off. There is. Regarding non-volatile memories using such ferroelectric films, for example, there are structures in which capacitors made of ferroelectric films are integrated on a silicon substrate as in US Pat. No. 4,149,302, and MIS type transistors as in US Pat. No. 3,832,700. A nonvolatile memory has been proposed in which a ferroelectric film is disposed on the gate portion of a MOS type semiconductor device, or a structure in which a ferroelectric film is stacked on a MOS type semiconductor device as in IEDM; 87pp, 850-851. Conventionally, these manufacturing methods include, for example, as shown in FIG. 2, a field oxide film 12 is formed on a silicon substrate 11 on which semiconductor elements such as MOS transistors are formed.
The lower electrode 18 is formed by growing a conductive film such as Po1y-3i through the first interlayer insulating film 17 and patterning it with a dry etcher using a fluorocarbon gas such as CF4. Here, 13 is a gate insulating film, 14 is a gate electrode using Poly-3t, etc.
5.16 is an N-type impurity layer such as source and drain (
Figure 2(a)). Next, PbTi is used as the ferroelectric film 19.
O3 and PZT (PbTi03/PbZ r03),
PLZT (La/PbT t.

3/PbZr03) etc., heat treatment is performed to improve crystallinity, and then HCI, H
The ferroelectric film 19 is etched into a predetermined shape using a mixed solution of F and NH4F. Next, the A1 alloy is sputtered and patterned to form the upper electrode 20 (Fig. 2(b)
)). Subsequently, a silicon oxide film is grown in a vapor phase as a second interlayer insulating film 21, and after contact holes are formed, metal interconnections 22 made of A1 alloy are formed (FIG. 2(C)).

[Problem to be solved by the invention]

However, in the conventional technique, the ferroelectric film 19 and the upper and lower electrodes 18 and 20 are patterned in separate steps, which causes problems in dimensional accuracy, reproducibility of alignment accuracy, and number of steps. Furthermore, each time patterning is repeated, the first interlayer insulating film 17 becomes thinner, and when forming a contact hole, the thickness of the interlayer insulating film on the upper electrode is different from that on the impurity layer of the silicon substrate. The electrodes are sometimes etched, which poses problems in terms of integration and productivity.

However, the present invention is intended to solve these problems, and is aimed at the practical application and stable supply of low-cost, easy-to-manufacture microscopic semiconductor devices, especially nonvolatile memories using ferroelectric films. be.

[Means to solve the problem]

In the semiconductor device manufacturing method of the present invention, in a semiconductor device in which a ferroelectric film is integrated on the same semiconductor substrate on which active elements are formed, at least one of the electrodes sandwiching the ferroelectric film is It is characterized by being formed using the same mask pattern as the ferroelectric film.

〔Example〕

An embodiment of the semiconductor device manufacturing method of the present invention will be described in detail with reference to FIG. For example, after growing a field oxide film 12 on a P-type silicon substrate 11 by selective oxidation, a gate insulating film 13 made of a 200-layer silicon oxide film and a gate electrode 14 made of, for example, phosphorus-doped Po1y-Si are formed. In order to form N-type impurity layers 15.16 such as source and drain in a self-aligned manner, 8×1
Ion implantation was performed at 0"Cm-2. This was then coated with vapor phase growth oxidation and coated glass for planarization as the first interlayer insulating film 17, and contact holes were opened (see Fig. 1). (a)) Next, Poly-3t of about 3500A is grown in vapor phase, doped with impurities such as phosphorus, sputtered with about 5000 PbTiO3 as the ferroelectric film 19, and then heat-treated at about 650°C. After improving the crystallinity, P again.

1y-8i is grown in a vapor phase and doped with impurities. Here, the heat treatment of the ferroelectric film is performed by
The growth of 5t may be performed in the same furnace. Next, using the photoresist 30 as a mask, C2C12Fa, S
F6 and A: Using a gas or the like, the ferroelectric film 19 and the Po1y-3i, which will become the upper and lower electrodes 20.18, were continuously dry-etched in the same chamber into a predetermined shape (see Fig. 1(b)). )) Subsequently, after removing the photoresist 30, a second interlayer insulating film 2 is formed by growing a silicon oxide film in a vapor phase.
A contact hole was formed in the first interlayer insulating film 17 and the like, and the sputtered A1 alloy film with a thickness of about 1.0 μm was photoetched to form a metal wiring 22 (FIG. 1(C)). Thereafter, a silicon nitride film was deposited by plasma growth to serve as a surface protective film, and pads for taking out external electrodes were opened.

In the semiconductor device constructed in this manner, the ferroelectric film and the lower or upper electrode are formed in a nearly self-aligned manner, so that the dimensions can be easily controlled and integrated more easily than in the past. In addition, the number of photo-etching steps was reduced, and the number of man-hours was reduced and the thickness of the interlayer insulating film was ensured.

Furthermore, the connection between the capacitor and the impurity layer can be made directly with the lower electrode, and the upper electrode is no longer removed by etching when holes are opened. Note that PbTiO is used as the ferroelectric film 19.
31: Similar effects were obtained by using alternative esters, PZT, and PLZT.

In addition to simultaneously etching the three layers of the ferroelectric film and the upper and lower electrodes, the ferroelectric film and the lower electrode, and the ferroelectric film and the upper electrode may be etched simultaneously. On the other hand, although Po1y-Si was used for the upper and lower electrodes, other materials such as a-3i, high melting point metals such as Ti1W, Mo5Ta, and Pt, silicides, nitrides, and single-layer or multilayer structures of these compounds may also be used. It is applicable. Furthermore, although the present invention has been described with reference to a case where a memory structure of a ferroelectric film is formed on a silicon substrate including an MO3IC, a CMO
3. ICtR structure of bipolar or a composite element thereof, or a compound semiconductor such as GaAs may be used for the substrate.

〔Effect of the invention〕

As described above, according to the present invention, by simultaneously etching the ferroelectric film and the upper or lower electrode, integration and
This can contribute to the practical application and stable supply of highly productive semiconductor devices, especially nonvolatile memories.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(c) are schematic cross-sectional views showing an embodiment of a method for manufacturing a semiconductor device according to the present invention. FIGS. 2(a) to 2(c) are schematic cross-sectional views of a conventional semiconductor device manufacturing method. 11...Silicon substrate 12...Field oxide film 13...Gate insulating film 14...Gate electrode 15.16/Impurity layer 18...20/No. 21...22...30... - First interlayer insulating film lower electrode Ferroelectric film upper electrode Second interlayer insulating film Metal wiring photoresist Applicant: Seiko Epson Corporation

Claims (2)

[Claims] (1) In a semiconductor device in which a ferroelectric film is integrated on the same semiconductor substrate on which active elements are formed, at least one of the electrodes sandwiching the ferroelectric film has the same mask as the ferroelectric film. A method for manufacturing a semiconductor device, characterized in that it is formed by a pattern. (2) The method of manufacturing a semiconductor device according to claim 1, wherein etching of at least one of the ferroelectric film and the electrodes sandwiching the ferroelectric film is performed in the same apparatus.