JPH0319372A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0319372A
JPH0319372A JP1153994A JP15399489A JPH0319372A JP H0319372 A JPH0319372 A JP H0319372A JP 1153994 A JP1153994 A JP 1153994A JP 15399489 A JP15399489 A JP 15399489A JP H0319372 A JPH0319372 A JP H0319372A
Authority
JP
Japan
Prior art keywords
film
capacitor
electrode
photoetching
paraelectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1153994A
Other languages
Japanese (ja)
Inventor
Shoichi Kimura
木村 正一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP1153994A priority Critical patent/JPH0319372A/en
Publication of JPH0319372A publication Critical patent/JPH0319372A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B53/00Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To obtain a capacitor and a non-volatile memory provided with a high dielectric film operable at a low voltage, high in polarization speed, and stable by a method wherein the electrode end of the capacitor of ferroelectric film is formed of paraelectric film. CONSTITUTION:A lower electrode 8 is kept at a fixed potential of a capacitor. A paraelectric film 11 of SiO2 or the like is formed. The disused part of the paraelectric film 11 is removed through photoetching so as to leave the end of the capacitor electrode unremoved. Then, a ferroelectric film 9 of PbTiO3, for instance, is formed. The ferroelectric film 9 is thermally treated in an atmosphere of N2. The ferroelectric film 9 is formed into a pattern of prescribed shape through a photoetching method so as to leave the inside of the paraelectric film 11 unremoved. Then, Pt is deposited, for instance, as an upper electrode 10, which is formed into a pattern of prescribed shape through photoetching. A second interlaminar insulating film 12 is formed, a connection hole is provided in the upper electrode 10 and a source 5 through photoetching, and an AC film 13 is, for instance, formed, which is subjected to photoetching so as to connect the upper electrode 10 and the source 5 together.

Description

【発明の詳細な説明】 r産業上の利用分野] 本発明は、強誘電体を用いた、不揮発性メモリに関し、
特にキャパシタに適用して有効な技術に関する. [従来の技術1 半導体不揮発性メモリとしては、絶縁ゲート中のトラッ
プまたは浮遊ゲートにシリコン基板からの電荷を注入す
ることにより,シリコン基板の表面ポテンシャルが変調
される現象を用いた、MIS型トランジスタが,一般に
使用されており、EPROM (紫外線消去型不揮発性
メモリ)やEEPROM ([気的書き換え可能型不揮
発性メモリ)などとして実用化されている.しかしこれ
らの不揮発性メモリは、情報の書き換え電圧が,通常約
20V前後と高いなどの欠点を有する.il気的に分極
が反転可能である強誘電体を用いた、不揮発性メモリに
ついては、書き込み電圧も、通常用いられてる5Vであ
り、また電源を切っても分極は保持されるため、理想的
な不揮発メモリーとなる可能性を有する. この様な強誘電体を用いた不揮発性メモリ構造ノ一ツニ
、W.I.KINNEY:・A NON−VOLATI
LE MEMORY(:ELL BASED ON F
ERRQELECTRIC STORAGE CAPA
CITORS’.IEDM,8 7 , PP8 5 
0−に開示された、第3図に代表される様な、キャパシ
タをトランジスタの上に絶縁膜を介して積層する.いわ
ゆるスタックト型構造がある. [発明が解決しようとする課題] 強誘電体を用いたキャパシタの理想的な印加電圧と、蓄
積電荷との関係を示したのが、第4図である.しかし第
3図のキャパシタの場合、印加電圧と、蓄積電荷との関
係は、第5図の様になる.これは、第6図の様に、キャ
パシタの電極端の電界が、前記電極下の外側に回わりこ
むため,その部分の分極が必要になるためである.した
がって、理恕的な場合と比較すると、分極を生じさせた
り、分極を反転させるには、高い電圧が必要となる.ま
たこれを不揮発性メモリーのキャパシタとして用いれば
、書き込み電圧を高く設定してやる必要があるし、書き
込み時間も長時間となる.また分極電荷ら一定でない.
また、高い電圧が必要のため、不揮発性メモリ設計のマ
ージンもなくなるし、低電圧動作させた場合、不安定と
なる.そこで本発明は、この様な問題を解決するもので
、その目的とするところは,低電圧動作が可能で,分極
速度ら速く.安定した高誘電体膜を用いたキャパシタ及
び不揮発性メモリーを提供するところにある. 〔課題を解決するための手段1 本発明の半導体装置は, (1)半導体基板上に絶縁膜が形成されており前記絶縁
股上に下部電極が形成されており、前記下部電極上に強
誘電体薄膜が形成されており、前記強誘電体薄膜上に上
部電極が形成されているキャパシタにおいて、該上部M
極および下部iitiにはさまれた部分の端には常誘電
体が形成されていることを特徴とする. [実 施 例] 第1図は本発明のl実施例における半導体装置の断面図
である.また第2図(a)〜第2図(C)はその製造工
程ごとの主要断面図である.なお実施例の全図において
、同一の機能を有するちのには、同一の符号を付け,そ
の繰り返しの説明は省略する. 以下、第2図(a)〜第2図(c)に従い,説明してい
く.ここでは説明の都合上、Nチャネルトランジスタを
用いた例につき説明する.まず,第2図(a)の如く,
例えばP型のSi基板上を用いる.比抵抗は2 0oh
m . cm程度が適当であろう.それに素子分離用絶
縁膜2を例えばLOCOS法により約6000人形成す
る.7はゲート膜であり、前記素子分離用絶縁膜2を形
成後,酸化雰囲気中で熱酸化させ形成する.例えば30
0人程度が適当であろう.4はゲート1!陽とな?,例
えば多結晶S1であり、例えば4000人の膜厚で形成
する.5と6は、uos トランジスタのソース、ドレ
インとなるN型拡敗層であり、例えば前記ゲート電極4
を形成したあとに、イオン注入法により,リンを4 X
 1 0 ”cm−”注入することにより形成する.3
は,前記Si基板】に形成したMOS型トランジスタと
分離するための第1層間絶縁膜であり、化学気相成長法
(cvd法)により{51)えば2000人のSiO■
を形成する.そしてキャパシタの下部電極8として、例
えばptを、スバック法により例えば5000ス形成す
る.そしてフォト・エッチングの工程により所定形のパ
ターンを形成する.なお本実施例では,下部電極8はキ
ャパシタの固定電位になっている。
[Detailed Description of the Invention] r Industrial Application Field] The present invention relates to a nonvolatile memory using a ferroelectric material,
In particular, it concerns techniques that are effective when applied to capacitors. [Conventional technology 1] As a semiconductor non-volatile memory, an MIS type transistor uses a phenomenon in which the surface potential of the silicon substrate is modulated by injecting charge from the silicon substrate into a trap or a floating gate in an insulated gate. It is commonly used and has been put into practical use as EPROM (ultraviolet erasable non-volatile memory) and EEPROM (electronically rewritable non-volatile memory). However, these nonvolatile memories have drawbacks such as the high voltage required for rewriting information, usually around 20V. For non-volatile memory that uses ferroelectric material whose polarization can be reversed automatically, the write voltage is the commonly used 5V, and the polarization is maintained even when the power is turned off, making it ideal. It has the potential to become a non-volatile memory. A nonvolatile memory structure using such a ferroelectric material, W. I. KINNEY:・A NON-VOLATI
LE MEMORY(:ELL BASED ON F
ERRQELECTRIC STORAGE CAPA
CITORS'. IEDM, 8 7, PP8 5
0-, a capacitor as typified by FIG. 3 is laminated on top of a transistor with an insulating film interposed therebetween. There is a so-called stacked structure. [Problems to be Solved by the Invention] Figure 4 shows the relationship between the ideal applied voltage and accumulated charge in a capacitor using a ferroelectric material. However, in the case of the capacitor shown in Figure 3, the relationship between the applied voltage and the accumulated charge is as shown in Figure 5. This is because, as shown in Figure 6, the electric field at the electrode end of the capacitor wraps around to the outside under the electrode, and that part needs to be polarized. Therefore, compared to the rational case, a higher voltage is required to generate polarization or reverse polarization. Furthermore, if this is used as a capacitor for non-volatile memory, the write voltage must be set high and the write time will be long. Also, the polarization charge is not constant.
Additionally, since high voltage is required, there is no margin for nonvolatile memory design, and it becomes unstable when operated at low voltages. The present invention is intended to solve these problems, and its purpose is to enable low voltage operation and to increase the polarization speed. Our goal is to provide capacitors and nonvolatile memories using stable high dielectric films. [Means for Solving the Problems 1] The semiconductor device of the present invention includes: (1) an insulating film is formed on a semiconductor substrate, a lower electrode is formed on the insulating layer, and a ferroelectric material is formed on the lower electrode. In a capacitor in which a thin film is formed and an upper electrode is formed on the ferroelectric thin film, the upper M
It is characterized in that a paraelectric material is formed at the end of the part sandwiched between the pole and the lower part. [Embodiment] FIG. 1 is a sectional view of a semiconductor device in an embodiment of the present invention. Moreover, FIGS. 2(a) to 2(C) are main cross-sectional views for each manufacturing process. In all the figures of the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations will be omitted. The explanation will be given below according to Fig. 2(a) to Fig. 2(c). For convenience of explanation, an example using an N-channel transistor will be explained here. First, as shown in Figure 2 (a),
For example, use a P-type Si substrate. Specific resistance is 20ohh
m. About cm would be appropriate. Approximately 6,000 people then form an insulating film 2 for element isolation using, for example, the LOCOS method. Reference numeral 7 denotes a gate film, which is formed by thermal oxidation in an oxidizing atmosphere after the element isolation insulating film 2 is formed. For example 30
Approximately 0 people would be appropriate. 4 is gate 1! Sun and what? , for example, is polycrystalline S1, and is formed with a film thickness of, for example, 4000. 5 and 6 are N-type diffusion layers that become the source and drain of the UOS transistor; for example, the gate electrode 4
After forming, 4X phosphorus is added by ion implantation
Formed by implanting 10 cm-. 3
is the first interlayer insulating film for separating from the MOS transistor formed on the above-mentioned Si substrate.
form. Then, as the lower electrode 8 of the capacitor, for example, 5,000 layers of PT is formed by the Subac method. Then, a predetermined pattern is formed using a photo-etching process. In this embodiment, the lower electrode 8 has a fixed potential of a capacitor.

次に第2図(b)の如く、常誘電体膜l1として例えば
SiOzを5000人の膜厚でcvd法により形成する
.そして,キャパシタ電極の端を残すよう1こ、フォト
・エッチングの工I呈1こより前記常;秀電体1lの不
要な部分を取り除く.次に強誘電体膜9を例えばPbT
iOsをスパッタ法により5000人形成する.そして
N2雰囲気中で550℃で、1時間熱処理を行なう. 次に第2図(c)の如く、前記常誘電体1i1)の内測
を残す様に、前記強誘電体1)i9を、フォト・エッチ
ングの工程により所定形のパターンに形成する.次に上
部電極10として、例えばptを5000人スパッタ法
により形成し,フォト・エッチングの工程により、所定
形のパターンに形成する. そして最後に第2層間絶縁膜l2を化学気相成長法によ
り形成し,前記上部電極lO上及び前記ソース5上に接
続穴を、フォト・エッチングの工程により形成し、例え
ばAC膜l3をIumほどスバッタ〆去により形成し、
前記上部電極IO及び前記ソース5を接続する様に、前
記AC膜13をフォト・エッチングすることにより、第
1図の様な本実施例を得る. なお本実施例では、強誘電体としてPbTtOsを用イ
タが、PZTfPbTiOszPbZrOi ) . 
PLZTなど他の強誘電体材料を用いても良い. この様に、キャパシタの端を強誘電体膜ではなく、常誘
電体膜を用いることにより、第6図の様に,キャパシタ
の電極端の電界がキャパシタ外に回りこむが、その部分
は常誘電体膜のため、強誘電体膜の分極量は、一定とな
る.したがって印加電圧と蓄積電荷との関係は、第4図
の様な理想的な関係に近ずく.よって強誘電体膜に分極
を生じさせたり反転されるのにより低電圧ですむことに
なる.また不揮発性メモリのキャパシタとして用いれば
、書き込み電圧をより低く設定することち可能であるし
,書き込み時間ち短かくなる.また低い電圧での動作が
可能となるため、不揮発性メモリーの設計マージンらあ
り、低電圧で動作させても安定動作することが可能とな
る. また前記常誘電体膜1)は、キャパシタの端のすべてに
あることが望ましいが、一部分で6その分の効果は期待
できる. また本発明は、強誘電体膜を用いたキャパシタ特製の改
善であるため、キャパシタ以外の構造に関しては、本実
施例で説明した構造ばかりでなくCMOS構造、バイボ
ーラ構造などでも良いことは言うまでちない. また本実施例では、前記下部電極8を接地し、前記上部
電極10に電圧を印加してキャバシクとする構造である
が、その逆の構造でも本発明と同じである. また本実施例では,常誘電体膜の内側に強誘電体膜を形
成する場合,通常のフォト・エッチング工程を用いたが
、形成が固難な場合、リフト才フl去エッチバック法を
用いて形成してち良い.[発明の効果1 以上述べてきた様に、本発明の半導体装置によれば,強
誘電体膜を用いたキャパシタの電極端を常誘電体膜にす
ることにより、キャパシタの端ではなく内測の強誘電体
膜が分極することになり、低電圧動作、安定動作が可能
な高誘電体膜キャパシタを作ることができ、低電圧動作
が可能で、書き込み時間の短かい不揮発性メモリーを作
ることができる.
Next, as shown in FIG. 2(b), a paraelectric film l1 of SiOz, for example, is formed to a thickness of 5,000 yen by the CVD method. Then, remove unnecessary portions of the electrical conductor 1l using a photo-etching process so as to leave the ends of the capacitor electrodes intact. Next, the ferroelectric film 9 is made of, for example, PbT.
Form 5,000 iOs using sputtering method. Then heat treatment was performed at 550°C for 1 hour in a N2 atmosphere. Next, as shown in FIG. 2(c), the ferroelectric material 1)i9 is formed into a predetermined pattern by a photo-etching process so as to leave the internal measurements of the paraelectric material 1i1). Next, as the upper electrode 10, PT, for example, is formed by a 5,000-person sputtering method, and is formed into a predetermined pattern by a photo-etching process. Finally, a second interlayer insulating film l2 is formed by chemical vapor deposition, and connection holes are formed on the upper electrode lO and on the source 5 by a photo-etching process. Formed by removing the grass,
By photo-etching the AC film 13 so as to connect the upper electrode IO and the source 5, this embodiment as shown in FIG. 1 is obtained. In this example, PbTtOs is used as the ferroelectric material, but PZTfPbTiOszPbZrOi).
Other ferroelectric materials such as PLZT may also be used. In this way, by using a paraelectric film instead of a ferroelectric film at the end of the capacitor, the electric field at the electrode end of the capacitor wraps around to the outside of the capacitor, as shown in Figure 6, but that part is not a paraelectric film. Since it is a body film, the amount of polarization of the ferroelectric film is constant. Therefore, the relationship between applied voltage and accumulated charge approaches the ideal relationship as shown in FIG. Therefore, low voltage is required because polarization is generated or reversed in the ferroelectric film. Furthermore, if it is used as a capacitor for non-volatile memory, it is possible to set the write voltage lower and the write time becomes shorter. In addition, since it is possible to operate at low voltages, there is a margin in the design of nonvolatile memory, and it is possible to operate stably even at low voltages. Further, although it is desirable that the paraelectric film 1) be provided on all the ends of the capacitor, it is possible to expect an effect equivalent to 6 on a portion. Furthermore, since the present invention is a special improvement of a capacitor using a ferroelectric film, it goes without saying that structures other than the capacitor may be not only the structure explained in this embodiment but also a CMOS structure, a bibolar structure, etc. do not have. Further, in this embodiment, the lower electrode 8 is grounded and a voltage is applied to the upper electrode 10 to form a cavity, but the present invention can also have the opposite structure. In addition, in this example, when forming a ferroelectric film inside a paraelectric film, a normal photo-etching process was used, but if formation was difficult, a lift-off etch-back method was used. It is better to form it. [Effects of the Invention 1] As described above, according to the semiconductor device of the present invention, by using a paraelectric film as the electrode end of a capacitor using a ferroelectric film, internal measurement can be performed instead of at the end of the capacitor. The ferroelectric film becomes polarized, making it possible to create high dielectric film capacitors that can operate at low voltages and operate stably, making it possible to create nonvolatile memories that can operate at low voltages and have short write times. can.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の半導体装置及び半導体記憶装置の一
実施例を示す主要断面図. 第2図(a)〜(c)は、本発明の半導体装置及び半導
体記憶装置の製造方法の一例を工程順に説明するための
主要断面図. 第3図は、従来の半導体装置及び半導体記憶装置を示す
主要断面図. 第4図は、強誘電体膜を用いたキャパシタの理想的な、
印加電圧と、分極した電荷の関係の図.第5図は、従来
構造の強誘電体膜を用いたキャパシタの印加電圧と分極
した電荷の関係の図。 第6図は、従来の強誘電体膜を用いたキャパシタの電界
のかかり方を示した図. 1 ・ ・ 2 ・ ・ 3 4 ・ 5 ・ 31基板 素子分離用絶縁膜 第1層間絶縁膜 ゲート電極 ソース 6 ・ 7 ・ 8 ・ 9 ・ 1 0 ・ 1)  ・ l 2 ・ l 3 ・ l 4 ・ ・ドレイン ・ゲート膜 ・下部電極 ・強誘電体膜 ・上部電極 ・常誘電体膿 第2層間絶縁膜 ・ALIII ・電界
FIG. 1 is a main sectional view showing an embodiment of a semiconductor device and a semiconductor memory device of the present invention. FIGS. 2(a) to 2(c) are main cross-sectional views for explaining an example of a method for manufacturing a semiconductor device and a semiconductor memory device according to the present invention in the order of steps. FIG. 3 is a main cross-sectional view showing a conventional semiconductor device and semiconductor memory device. Figure 4 shows an ideal capacitor using a ferroelectric film.
Diagram of the relationship between applied voltage and polarized charge. FIG. 5 is a diagram showing the relationship between applied voltage and polarized charge of a capacitor using a ferroelectric film with a conventional structure. Figure 6 is a diagram showing how an electric field is applied to a capacitor using a conventional ferroelectric film. 1 ・ ・ 2 ・ ・ 3 4 ・ 5 ・ 31 Substrate element isolation insulating film First interlayer insulating film Gate electrode source 6 ・ 7 ・ 8 ・ 9 ・ 1 0 ・ 1) ・ l 2 ・ l 3 ・ l 4 ・ ・Drain, gate film, lower electrode, ferroelectric film, upper electrode, paraelectric second interlayer insulating film, ALIII, electric field

Claims (4)

【特許請求の範囲】[Claims] (1)半導体基板上に絶縁膜が形成されており、前記絶
縁膜上に下部電極が形成されており、前記下部電極上に
強誘電体薄膜が形成されており、前記強誘電体薄上に上
部電極が形成されているキャパシタにおいて、該上部電
極および下部電極にはさまれた部分の端には常誘電体が
形成されていることを特徴とする半導体装置。
(1) An insulating film is formed on a semiconductor substrate, a lower electrode is formed on the insulating film, a ferroelectric thin film is formed on the lower electrode, and a ferroelectric thin film is formed on the ferroelectric thin film. 1. A semiconductor device characterized in that, in a capacitor in which an upper electrode is formed, a paraelectric material is formed at an end of a portion sandwiched between the upper electrode and the lower electrode.
(2)前記強誘電体薄膜の主成分が少なくともPbTi
O_3、PZT(PbTiO_3/PbZrO_3)、
PLZT(La/PbTiO_3/PbZrO_3)の
うちのいずれかであることを特徴とする請求項1記載の
半導体装置。
(2) The main component of the ferroelectric thin film is at least PbTi.
O_3, PZT (PbTiO_3/PbZrO_3),
2. The semiconductor device according to claim 1, wherein the semiconductor device is one of PLZT (La/PbTiO_3/PbZrO_3).
(3)前記第2上部電極は、高濃度に不純物を注入され
た多結晶シリコン膜もしくはそのポリサイド膜から成る
ことを特徴とする請求項1記載の半導体装置。
(3) The semiconductor device according to claim 1, wherein the second upper electrode is made of a polycrystalline silicon film into which impurities are implanted at a high concentration or a polycide film thereof.
(4)前記キャパシタを不揮発性メモリのキャパシタと
して用いたことを特徴とする請求項1記載の半導体装置
(4) The semiconductor device according to claim 1, wherein the capacitor is used as a capacitor of a nonvolatile memory.
JP1153994A 1989-06-16 1989-06-16 Semiconductor device Pending JPH0319372A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1153994A JPH0319372A (en) 1989-06-16 1989-06-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1153994A JPH0319372A (en) 1989-06-16 1989-06-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0319372A true JPH0319372A (en) 1991-01-28

Family

ID=15574594

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1153994A Pending JPH0319372A (en) 1989-06-16 1989-06-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0319372A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999025014A1 (en) * 1997-11-10 1999-05-20 Hitachi, Ltd. Dielectric element and manufacturing method therefor
US6379977B1 (en) 1998-10-01 2002-04-30 Hyundai Electronics Industries Co., Ltd. Method of manufacturing ferroelectric memory device
US6487119B2 (en) * 2000-11-17 2002-11-26 Oki Electric Industry Co., Ltd. Non-volatile read only memory and its manufacturing method
US6611457B2 (en) 2001-09-18 2003-08-26 Oki Electric Industry Co., Ltd. Read-only nonvolatile memory
US6913970B2 (en) * 2000-06-19 2005-07-05 Fujitsu Limited Semiconductor device and method of manufacturing the same
KR100705175B1 (en) * 2000-12-27 2007-04-06 주식회사 하이닉스반도체 Method of manufacturing MOS structure

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999025014A1 (en) * 1997-11-10 1999-05-20 Hitachi, Ltd. Dielectric element and manufacturing method therefor
US6379977B1 (en) 1998-10-01 2002-04-30 Hyundai Electronics Industries Co., Ltd. Method of manufacturing ferroelectric memory device
US6913970B2 (en) * 2000-06-19 2005-07-05 Fujitsu Limited Semiconductor device and method of manufacturing the same
US6487119B2 (en) * 2000-11-17 2002-11-26 Oki Electric Industry Co., Ltd. Non-volatile read only memory and its manufacturing method
US6780710B2 (en) 2000-11-17 2004-08-24 Oki Electric Industry Co., Ltd. Method of manufacturing non-volatile read only memory
US6955966B2 (en) 2000-11-17 2005-10-18 Oki Electric Industry Co., Ltd. Method of manufacturing non-volatile read only memory
KR100705175B1 (en) * 2000-12-27 2007-04-06 주식회사 하이닉스반도체 Method of manufacturing MOS structure
US6611457B2 (en) 2001-09-18 2003-08-26 Oki Electric Industry Co., Ltd. Read-only nonvolatile memory

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