JPS6141020B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a disk cache device in a disk subsystem within an information processing device.

Since disk devices involve mechanical operations when accessing data, the access time is longer than the processing time of the central processing unit CPU, which is a factor that reduces the performance of information processing systems. Therefore, a disk cache device has been proposed that is provided with a high-speed, small-capacity cache memory and stores some disk data in the cache memory to shorten the effective disk access time.

A common way to reduce the writing time of disk data using a disk cache device is to
This is a method in which a write operation end signal is returned to the host device at the point when the write data given from the host device, such as the host device, is written into the cache memory, and the rewritten data is then written to the disk. In this case, the point at which data is written to the disk is not directly controlled by the host device, so if it becomes impossible to write data to the disk due to a hardware failure, the point at which this becomes clear is that the process of the host device is progressing. is not synchronized with. Therefore, when it becomes clear that writing to the disk is not possible,
Processing in the host device may already be progressing and it may be too late to resolve the problem. For example, if the task or job that issued the write request related to the failure has already ended and disappeared from the system, it is extremely difficult to remedy the failure.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a disk cache device in which a host device can recognize disk cache-related failures within a period in which failure recovery processing is possible.

In order to achieve the above object, the present invention writes data on a disk cache to a disk based on a command from a host device.

According to the present invention, a cache memory stores data to be written to a disk provided from a host device, and data on this cache memory that has not yet been written to the disk is stored in accordance with a command from the host device. A disk cache device is obtained, comprising means capable of writing to the disk.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an information processing system using a disk cache device according to the present invention. The information processing system in FIG. 1 includes a central processing unit CPU11 including a channel, a disk device 12 including a disk control device (not shown), and a disk cache device 13.

The disk cache device 13 has a disk cache control device 14 and a cache memory 15. A part of the data from the disk device 12 is stored in the cache memory 15.
The disk cache control device 14 decodes commands for reading and writing data in the disk device 12 and other commands given from the CPU 11, and accesses the cache memory 15 if the accessed data is in the cache memory 15, and accesses the cache memory 15 if the accessed data is not there. If necessary, it accesses the disk device 12 and updates the cache memory 15 as necessary. Note that the disk cache device 15 does not necessarily have to be independent of the channel or disk control device, and can be incorporated into these devices.

FIG. 2 is a diagram showing the configuration of an embodiment of the present invention. In FIG. 2, the same components as in FIG. 1 are given the same reference numerals. The following explanation will be given with reference to FIG. 1. The disk cache control device 14 exchanges control information with the CPU 11 via a signal line a, and transfers control information to the disk drive 1 via a signal line b.
2 and the cache memory 15. The cache memory 15 is the disk device 1
It consists of a data field into which data block No. 2 is stored, an address field into which the address of the data block on the disk is stored, and a W bit field which becomes logic "1" when writing to the disk is not completed.

The address register 16 is a register that stores a data area to be flushed to the disk device 12.
The lower limit address and upper limit address of the data area are stored in 17 and 18, respectively. The comparator 19 inputs the addresses of the address section and W bit section of the cache memory 15, and the address of the address register 16, and determines the cache block to be flushed out. Further, c, d, and e are all data buses, and data is transferred under the control of the disk cache controller 14.

Next, the operation of the disk cache device according to the present invention will be explained with reference to FIG. To simplify the explanation below, it is assumed that data on a disk is recorded in fixed-length records called sectors, and that data is uniquely accessed by the sector address (volume number and sector number within the volume). . It is also assumed that one data access from the host device is one sector. The cache memory 15 also stores data in units of sectors, with the data section containing the contents of the sector, and the address section containing the sector address.

When a data write command is issued from the host device to the sector at address A, the disk cache controller 14 checks the address section of the cache memory 15 via signal line c and determines whether the sector with address A already exists in the cache. If so, write data to this data section via data buses d and e.
Write from CPU11. At the same time, this W bit part is set to "1" to indicate that this sector needs to be written to the disk.

If the accessed sector is not in the cache memory 15, an unnecessary sector of the cache memory is selected and A is written in the address field of this sector. The subsequent operations are the same as above. As an unnecessary cache sector, a sector whose W bit is not "1" is normally selected from among the sectors that have been referenced the earliest, but since this is not directly related to the present invention, a description thereof will be omitted.

In any of the above cases, when the data is written to the cache memory 15, the disk cache control device 14 notifies the CPU 11 of the host device of a write operation end signal via the signal line a at this point.
Thereafter, the disk cache control device 14 writes the data on the cache memory 15 to the disk device 12 via the data buses e and f, and sets the W bit to "0" when the writing is completed. With this control, from the perspective of the CPU 1, the data writing time is significantly improved compared to the disk.

However, at this point, when data is written from the cache memory 15 to the disk device 12, the disk cache device 13 or the disk device 1
Suppose that failure 2 occurs and the data in the cache memory cannot be written to the disk. Since the CPU 11 has already received the write end signal, it determines that this write has ended normally and continues processing. If the above-mentioned failure is notified to the CPU 11 at a stage when the processing has not progressed much, the CPU 11 determines that the above-mentioned write has ended in failure, returns the process to the point at which this write request was issued, and repeats this write operation again. Appropriate action can be taken. However, such treatment is not always possible. In other words, failure notification is delayed and CPU 11
If the processing has progressed considerably, the program that issued the write request may have already disappeared from the system, and in this case, the above-mentioned failure recovery measures cannot be taken.

Therefore, it is a feature of the present invention that the above-mentioned failure recovery measures can be taken, and the failure of the disk cache or the like can be known at the time when failure recovery is possible, and appropriate failure recovery processing can be performed.
That is, at a time when failure recovery is possible, for example, before the program disappears from the system, the CPU 11 issues a data flush command to the disk cache control device 14. This command sets the address range on the disk where the program has written data to the lower limit L.
This can be shown by the upper limit U. Upon receiving this command, the disk cache control device 14 stores the lower limit address L and the upper limit address U in registers 17 and 18, respectively.

Next, the disk cache control 14 sends the address part and the W bit part of the cache memory 15 one by one to the comparator 19. The comparator 19 compares this address A with the addresses L and U of the registers 17 and 18, and if A is between L and U and the W bit is 1, it outputs a logic "1"; otherwise, it outputs a logic "1". 0'' to the disk cache control device 14 by the signal line g.
Notify. When the disk cache controller 14 is notified of "1", it writes the corresponding data in the cache memory 15 to the disk 12 via buses e and f, and sets the corresponding W bit of the cache memory 15 to "0". do. If “0” is comparator 1
9, the disk cache controller 14 sends the next address of the cache memory 15 and the W bit to the comparator 19.

As described above, all data on the cache memory 15 whose addresses are between L and U are written (swept out) to the disk 12. At this time, if there is something that cannot be successfully flushed out to the disk due to a failure in the cache memory 15 or the disk 12, the disk cache control device 14 transfers it to the CPU 1 of the host device.
Tell 1. Therefore, CPU1 issued the sweep command.
1 can know at this point whether or not the writing was performed normally on the disk, and if the purge command is completed normally, the process proceeds, and if the purge ends unsuccessfully, some kind of failure has occurred. By recognizing that the problem has occurred, the above-mentioned fault handling can be taken.

In addition to the above, the sweep command also includes the following:
It is possible to specify two or more write data areas, or to specify data areas on all disks.

As explained above, the present invention allows data on the disk cache that has not been written to the disk to be written to the disk by a command from the host device, so that the host device can recover from the failure within the period during which failure recovery processing is possible. It has the effect of being able to recognize

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an information processing system to which the present invention is applied, and FIG. 2 is a diagram showing the configuration of an embodiment of the present invention. Explanation of symbols: 11 is the central processing unit (CPU), 1
2 is a disk device, 13 is a disk cache device, 14 is a disk cache control device, 15 is a cache memory, 16 is an address register, 1
9 represents a comparator, a, b, and c signal lines, d, e, and f a data bus, and g a signal line, respectively.

Claims (1)

[Claims] 1. A cache memory that stores data to be written to a disk given by a host device, and writing data on this cache memory that has not yet been written to the disk in accordance with a command from the host device. A disk cache device equipped with a means for performing.