JPS5892053A - Disc cash device - Google Patents

Abstract

PURPOSE:To recognize a failure from an upper-order device within a period possible for failure recovery processing, by writing the data on a disc cash not written on a disc through the instruction from the upper-order device. CONSTITUTION:In case of failure production, a data sweep-out instruction is given from a CPU to a disc cash controller 14 when the failure can be recovered. The controller 14 compares the address of a memory 15 with said address, and when the address is in a prescribed area and a W-bit is 1, logical ''1'' is informed and in other cases, logical ''0'' is informed. The controller 14 writes data in the memory 15 on a disc through the report of ''1'' and makes the W-bit of the memory 15 to ''0''. Through the report of ''0'', the next address of the memory 15 and the W-bit are transmitted to a comparator 19. If the sweep-out to the disc is unsuccessful, the controller 14 gives the information to the CPU, the CPU recognizes the success of write and makes countermeasures for the following processings.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a disk cache device in a disk subsystem within an information processing device.

Since disk devices involve mechanical operations when accessing data, the access time is longer than the processing time of a central processing unit (CPU), which is a factor that reduces the performance of information processing systems. Therefore, high-speed small-capacity cache memo IJ
Disk cache devices have been considered that reduce the effective disk access time by storing some disk data in a cache memory.

What is the general method for reducing the time required to load disk data using a disk cache device?

Write data given from a host device such as a CPU/',
This is a method in which a write operation completion signal is returned to the host device at the time the data is written to the cache memory, and the rewritten data is then written to the disk. In this case, the point at which booter 1 is loaded onto the disk is not directly controlled by the host device.

If it becomes impossible to write data to the disk due to a hardware failure, the time at which this becomes apparent is not synchronized with the progress of processing in the host device. Therefore, by the time it becomes clear that data cannot be written to the disk, the processing in the host device is already progressing, and it may be too late to handle the problem. For example, if the task or job that issued the write request related to the failure has already been completed and disappeared from the system, it is extremely difficult to remedy the failure.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a disk cache device in which a host device can recognize disk cache-related failures within a period in which failure recovery processing is possible.

In order to achieve the above object, the present invention transfers data on a disk cache to a disk K based on a command from a host device.
It is designed so that N can be included.

According to the present invention, there is provided a cache memory for storing data to be written to a disk provided from a host device, a booter whose data has not yet been written to the disk on this cache memory, and a booter that stores data to be written to a disk given from a host device; A disk cache device is obtained, which is equipped with a means for writing data into the disk.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an information processing system using a disc carriage device according to the present invention.

The information processing system in FIG. 1 includes a central processing unit (CPU) 11 including a channel, a disk device 12 including a disk control device (not shown). and a disk cache device 13.

The disk cache device 13 has a disk carriage control device 14 and a cache/unit memory 15. A portion of the data from the disk device 12 is stored in the cache memory 15.

The disk cache device 14 decodes commands for reading and writing data in the disk device 12 and other commands given from the CPU 11, and accesses the cache memory 15 if the accessed data exists in the cache memory 15, and otherwise accesses the cache memory 15. accesses the disk device 12IC, and updates the cache memory 15 as necessary.

Note that the disk cache device 15 does not necessarily have to be independent of the channel or the disk control device, and can be incorporated into these devices.

FIG. 2 is a diagram showing the configuration of an embodiment of the present invention. Second
In the figures, the same components as in FIG. 1 are given the same reference numerals. Explaining below with reference to FIG. 1, the disk cache control device 14 transfers control information to the CPU 11 via the signal line ai, and transfers control information to the disk device 12 and the cache memory 15 via the signal line. Deliver. The cache memory 15 is a data section into which data blocks of the disk device 12 are stored.

It consists of an address field into which the address of the data block on the disk is entered, and a W pit field which becomes logical 11' when writing to the disk is not completed.

The address register 16 is a register that stores a data area to be flushed to the disk device 12.

The lower limit address and upper limit address of the 17th and 18th data areas are stored, respectively. Comparator 19 is cache memory 1
The cache block to be flushed out is determined by inputting the addresses of the address section 5, the W bit section, and the address of the address register 16. Further, c, d, and e are all data buses, and data is transferred under the control of the disk cache control device 14.

Next, the operation of the disk cache device according to the present invention will be explained with reference to FIG. To simplify the explanation below, data on a disk is recorded in fixed-length records called sectors.

Data is assumed to be accessed at will by a sector address (volume number and sector number within the volume). It is also assumed that one data access from the host device is one sector.

In accordance with this, the cache memory 15 also stores data in units of sectors, with the data portion containing the contents of the sector, and the address portion containing the sector address.

When a data write command is issued from the host device to the sector at address A, the disk cache control device 14 checks the address section of the cache memory 15 via the signal line cVc and determines if the sector with the address A already exists in the cache. Data bus d
, e from the CPU 11. At the same time, the W bit part is set to 611 to indicate that this sector needs to be written to the entire disk.

If the accessed sector is not in the cache memory 15, select an unnecessary sector of the cache memory,
Write A to the address part of this sector. The subsequent operations are the same as above.

As an unnecessary cache sector, a sector whose W bit is not 11'' is usually selected from among the sectors most recently referenced, but since this is not directly related to the present invention, a description thereof will be omitted.

In any of the above cases, when data is written to the cache memory 15, the disk cache control device 14 notifies the CPU 11 of the host device of a write operation end signal via the signal line a at this point.

Thereafter, the disk cache control device 14 writes the data on the cache memory 15 to the disk device 12 via the data buses e and f, and when the writing is completed, W pinot)'! Set k to “0”. With this control, CPU1
1, data writing time is significantly improved compared to disk.

However, now at the time when data is written from the cache memory 15 to the disk device 12.

Disk can/u device 13 or disk device 12
Suppose that a failure occurs and data in cache memory cannot be written to disk.

Since the CPU 11 has already received the write-in completion signal, it determines that this writing has been completed normally and proceeds with the process. The above failure occurs when the processing is not very advanced.
If the PU 11 is notified, the CPU 11 can take appropriate measures such as determining that the write has failed, returning the process to the point in time when all 1 write requests have been issued, and repeating the write operation again. However, such treatment is not always possible. The notification of the block failure is delayed and the processing of the CPU 11 is progressing considerably.

The program that issued the write request may have already disappeared from the system, and in this case, the above failure recovery measures cannot be taken.

Therefore, it is a feature of the present invention that the above-mentioned failure recovery process can be performed, and the failure of the disk cache or the like can be known at the time when failure recovery is possible, and the appropriate failure recovery process can be performed. That is, the point at which failure recovery is possible, eg, before the program disappears from the system.

The CPU 11 issues a data flush command to the disk cache control device 14. This command is designed to indicate the address range on the disk into which the program has written data, using a lower limit and an upper limit U. When the disk cache control device 14 receives this command, it stores the lower limit address L and the upper limit address Ue registers 17 and 18, respectively.

Next, the disk cache control device 14 compares one address part and one W bit part of the cache memory 15 with a comparator 19.
send to. Comparator 19 inputs address A to register 4. Star 17. −, and if A is between L and U and the W bit is 1, the logic “1” r, otherwise the logic “OI” is sent to the disk cache control device 14 by the signal line g. When ``11'' is notified, the disk cache control device 14 outputs data i+buses e and f of the cache memory 15 corresponding to it.
k, write to disk 12, and write to cache memory 1
5 corresponding W bit 'i '0'. If 101
is notified from the comparator 19, the disk cache control device 14 selects the next address of the cache memory 15 and W
It is sent to the bintra comparator 19.

As described above, all of the data on the cache memory 15 whose addresses are between L and U are written (swept out) to the disk 12. At this time, if there is a problem in the cache memory 15 or the disk 12 that causes the flushing to the disk to be unsuccessful,
The disk cache control device 14 transfers this to C of the host device.
Inform PU11. Therefore, CPU1 issued the sweep command.
1 can know at this point whether or not the writing was successfully performed on the disk.

When the sweep command completes normally, the process proceeds.
If the cleaning is unsuccessful, it will be recognized that some kind of fault has occurred and the above-mentioned troubleshooting will be completed.

In addition, in the above, the sweep command is other than the above.

It is possible to specify two or more pledged data areas, or to specify data areas on all disks.

As described above, the present invention writes data on the disk cache that has not been written to the disk to the disk in response to a command from a host device, within a period in which failure recovery processing can be performed.

This has the effect that the host device can recognize failures.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an information processing system to which the present invention is applied, and FIG. 2 is a diagram showing the configuration of an embodiment of the present invention. Explanation of symbols; 11 is central processing unit (CPU), 12
Reference numeral 19 represents a comparator, signal lines a, b, and e, data buses d, e, and f, and signal line g.

Claims (1)

[Claims] 1. A cache memory that stores data to be written to a disk given from a higher-level device, and writing data on this cache memory that has not been committed to the disk in response to a command from the higher-level device. A disk cache device equipped with means capable of.