JPS6140586A - Electronic timepiece - Google Patents

Abstract

PURPOSE:To simplify the adjustment of clock rate, by setting the opening/closing timing of the switch with a clock rate adjusting value setting circuit by set one step unit for clock rate adjustment to make the adjusting range of one step constant regardless of any variation in a capacitor. CONSTITUTION:DELTAf is subdivided sufficiently with a resolution determined by a frequency division circuit 4 and several subdivided pieces are gathered to set the clock rate adjusting range of one step constant with a clock rate adjusting range setting circuit 3 by one step unit thus set to perform a clock rate adjustment with a clock rate adjusting range setting circuit 7. This can makes the adjusting range of one step constant regardless of any variation in a capacitor 2 to simplify the clock rate adjustment.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an electronic timepiece having a crystal oscillator equipped with a capacitor via a switch, and having means for adjusting the rate by opening and closing the switch, and particularly relates to the adjustment method thereof. .

[Conventional technology]

Conventionally, to adjust the rate of a clock, there were two methods: inserting a trimmer capacitor into the oscillation circuit system and increasing or decreasing its reactance component to change the oscillation frequency, or placing a variable divider after the oscillator to change the division ratio. A slow-paced method has been used.

However, as the accuracy of timepieces has changed in recent years, and more reliable and highly accurate timepieces have been required, it has become impossible to make adjustments using only the above two methods. Therefore, as shown in Fig. 2, a method was devised in which a frequency variable capacitor and capacitor 2 was installed in a crystal oscillator serving as a time standard via a switch 8, and the rate was adjusted by changing the oscillation frequency by opening and closing the switch. The details are, for example, in the Tokuko Sho 4
6-85007, Japanese Patent Application Laid-Open No. 58-148292, etc. With this method, it is possible to make fine b-rate adjustments in a short time, and furthermore, by combining it with the above-mentioned logical adjustment, adjustment can be made over a wide temperature range.

[Problem that the invention seeks to solve]

However, since the capacitor 2 to be switched has a small capacity, it is generally built on the circuit C together with the switch 8. Therefore, due to variations in the value of the capacitor 2, the capacitor 2 is connected to the crystal oscillator L. This causes variations in the oscillation frequency differential pressure between when there is noise and when there is no noise. Therefore, even if the switch 8 is controlled at the same timing to give the same ratio, the amount of adjustment varies from one to another, making rate adjustment extremely troublesome.

In particular, when a product leaves the manufacturer's hands and requires rate adjustment due to aging or other reasons, general watch stores do not have the data on the watch itself (it is difficult to attach this data to each watch). Since it is not known how much adjustment is possible with the adjustment means open to the user, it is necessary to gradually approach the desired value by the focusing method while measuring the rate, which is extremely difficult. It's a tedious and time-consuming task.

This will be explained a little more clearly using a diagram.

FIG. 3 shows the rate temperature characteristics of the oscillator 1 using a crystal resonator having second-order frequency temperature characteristics. (α)
(b) shows the case where the value of capacitor 2 is small due to variations, and (b) shows the case where it is large. In the figure, f, ct) are the characteristics when switch 3 is open (
(b) Crystals with the same characteristics are used for both (b) and (b). t t
(t) and i z (t) are the characteristics when the switch 8 is closed, and ΔfsxΔf2 is the frequency deviation when the switch 3 is opened and closed. Since Δf has a substantially constant value over the entire temperature range, let us now consider the apex temperature T of the quadratic curve. If an attempt is made to adjust Δf by dividing it into four adjustment steps, during each step of adjustment, there will be individual variations, such as 1 for (α) and 2 for (b).

Therefore, due to variations in the capacitor 12, the adjustment range varies from one unit to another, and it is not known how many steps the rate will need to be adjusted, so adjustment must be performed using the focusing method as described above. Therefore, an object of the present invention is to eliminate such inconveniences, provide a means for always keeping the amount of rate adjustment constant, and make it possible to easily and quickly adjust the rate.

[Means for solving problems]

The electronic timepiece of the present invention includes a frequency dividing circuit that generates a reference signal that determines the resolution of rate adjustment, a rate adjustment setting circuit that sets the rate adjustment amount of I step height, and a rate adjustment amount that sets the rate adjustment amount. It is characterized in that it has a timing circuit that controls the time ratio of connecting the setting circuit and the actance element to the crystal oscillator, and the rate is adjusted by the output of the timing circuit.

[Effect]

To describe the operation of the present invention, △f is sufficiently divided into 11 cm with the resolution determined by the above-mentioned frequency dividing circuit, and several of the subdivided parts are collected so that the rate adjustment amount of l step is always a constant value. Set in the rate adjustment setting circuit as follows,
Since the rate is adjusted by setting the opening/closing timing of the switch 8 using the rate adjustment amount setting circuit in units of one set step, the adjustment range of 1 step remains unchanged even if the capacitor 2 has a large variation, and the rate can also be adjusted. It becomes easy to do.

〔Example〕

FIG. 1 shows an outline of the present invention in the form of a block diagram. In FIG. 1, 1 to 8 are the same as those in FIG. 2 already described, 4 is a branch circuit that produces the reference signal IFo of the clock function 5 and the reference signal FIm'2 that determines the resolution of rate adjustment, and 6 is a branch circuit for rate adjustment. Adjustment setting circuit, 7 is rate adjustment amount setting circuit, 8 is timing circuit, 2 is the numerical value that determines the adjustment width, L! -, Lfi are terminals that set α, P is a numerical value that determines the amount of adjustment, and ÷1 to LM are terminals that set P. FIG. 4 is used to explain this circuit in an easy-to-understand manner.

61 F2 is the frequency, II'-1=1/P).

S is the rate adjustment amount of one step and is S; αd, and the rate adjustment amount setting circuit 6 realizes this calculation formula.

In other words, since the circuit is a constant value, d changes as △f varies, but by adjusting the coefficient α, Bl
#1 is set to a constant value. Here, α is an integer, so the resolution d needs to be high enough to set the adjustment step width S, which allows sufficient rate adjustment for the required clock accuracy, at any △f due to variations in the capacitor 2. .

Therefore, in the production process, △f is measured in advance.
By determining α for the desired S and setting the α in the rate adjustment amount setting circuit 6, the apparent adjustment width of one step can be made constant for all products. Once it is determined that one step is being adjusted, it is easy to determine how many steps should be adjusted to compensate for the rate deviation of the clock. In other words, if L in Figure 4 is the adjustment amount, then L: P
, El, the rate adjustment installation 7 constant circuit 7 defines this arithmetic expression and determines the overall adjustment amount. Therefore, by opening the setting of P to the user, it becomes possible to easily and speedily adjust the rate at a watch store. The timing circuit 8 is a circuit that forms the actual rate adjustment signal IT' by timing the result 74 (I'+ and Fl) calculated in 7.

The fifth example shows an example of the system explained above.
6, and its timing chart is shown in FIG.

A more specific explanation will be given below with reference to these figures. In Figure 5, 1 to 5 and 6 to 5 surrounded by a dashed line
8 is the same as in Figure 1, 9 surrounded by a broken line is a binary counter with a reset terminal, and 10 is a coincidence detection circuit.
1-"5 is the adjustment step width setting terminal, IJ6 to L9 are the adjustment amount setting terminals, and all symbols in FIG.
As shown in the figure, the frequency deviation Δf is divided into 512. Now, if Δf = 0.205 sec/day, then d = 0°0004 sec/dαV. Therefore, if the rate adjustment amount 1 step S for adjusting the rate at the desired clock accuracy is 0.0085ttc/day, %B=20. d, and by collecting the adjustment amount of d, we get 1
If the step adjustment switch 8 is closed, the adjustment amount d can be obtained.) The rate adjustment amount setting circuit 6 sets 'L1 to L5 in binary code α; Fs (20) can be obtained, and even if Δf changes due to variations in the capacitor 2 and α changes, by setting that α, the required Fs(α) can be obtained in the same way.

In addition, if α is not an integer in the calculation, the decimal places are rounded down or rounded up, but if the resulting error cannot be ignored in terms of accuracy, the resolution d is increased until it becomes negligible.
(increase the difference between 1P1 and F2) and increase the number of bits of circuit 6 by that amount. If α is measured and calculated in the production process and set in the circuit 6 in this manner, subsequent processing, that is, setting of the rate adjustment amount, can be made common to all products. In the example, the specific busyness is E = 0.008 sec/day, so if the required rate adjustment amount is 0.0565 eclday, the adjustment step P will be 7 steps from L = = P, S. Therefore, P of and Lb% of rate adjustment amount setting circuit 7
When set to L, F a (7) = 7- I
' s (20), and F 4 (P) representing the desired adjustment amount is obtained by the same operation as in the rate adjustment amount setting circuit described above. A signal F5 representing the ratio of F4(P) and Pl thus formed is formed by a timing circuit 8, and 1+
By controlling the switch 8 with '5, it becomes possible to perform desired rate adjustment. FIG. 6 shows the flow of each of the above signals.

Note that the configuration of the system according to the present invention is not limited to this embodiment. For example, circuits 6 and 7 can be configured using down counters having preset terminals, and circuit 8 can be configured by using a down counter with a preset terminal. When the value of lO- is large, it is necessary to take this into account.

〔Effect of the invention〕

If the present invention is used in conjunction with logical moderation using frequency dividing circuit operation, the setting method is exactly the same as the logic moderation method, but when viewed from the outside, it is simply an increase in the number of setting bits, which is impossible to achieve with logic moderation and moderation alone. Fine rate adjustments can be made easily. Therefore, the user can perform adjustment work without worrying about variations in individual products, considering only the specified rate adjustment and the clock rate that needs adjustment.
This is a very advantageous method in terms of after-sales service.

[Brief explanation of drawings]

Figure 1 - Block diagram of the electronic clock invented by the first wheel Figure 2...Schematic diagram of variable reactance system Figure 3 (α)
(b) in Figure 4... Temperature characteristics of crystal oscillator Figure 5...
An embodiment of the present invention Fig. 6 Timing chart of the circuit shown in Fig. 5 1 Crystal oscillator 2 Reactance element 3 Switch
4... Frequency divider 6... Rate adjustment amount setting circuit 7... Rate adjustment amount setting circuit 8... Timing circuit

Claims (1)

[Claims] A standard for determining the resolution of rate adjustment by dividing the output of the crystal oscillator in electronic watches in which a frequency variable capacitor is installed via a switch in a crystal oscillator serving as a time standard, and the rate is adjusted by opening and closing the switch. A frequency dividing circuit that generates a signal, a rate adjustment width setting circuit that sets the required rate adjustment width per step based on the resolution, and a rate adjustment amount that sets the rate adjustment amount based on the rate adjustment width. An electronic device comprising a setting circuit and a timing circuit that controls the opening/closing ratio of the switch according to the reference signal and the output of the rate adjustment amount setting circuit, and the rate is adjusted by the output of the timing circuit. clock.