JPH0259437B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a temperature-compensated electronic timepiece having a temperature-sensitive oscillator.

Traditionally, electronic watches have been equipped with temperature detection circuits,
Many methods have been proposed to compensate for the temperature of the reference signal source by sensing the temperature in a mobile phone, but they require an increase in the number of components and are difficult to suppress variations in the characteristics of the temperature sensing part and the crystal oscillator. Because of this, there are very few products that have been put into practical use.

In recent years, in addition to the conventional temperature compensation capacitor method and high frequency oscillation method using an AT-cut crystal resonator, temperature compensation has been performed using two tuning fork crystal resonators with different temperature characteristics. An electronic clock was developed.

Among these new methods, the method of connecting two crystal oscillators in parallel to a single amplifier has the advantage that there is no need for temperature detection, but the temperature compensation band is at most 0 to 0. It has little advantage over high-frequency oscillation types because the temperature is 40°C and the crystal oscillator must be specially made. In addition, if temperature information is obtained from the difference frequency between two crystal oscillators, there is a possibility of errors occurring due to interference or tuning phenomena between the two oscillators, and to avoid this, it is necessary to increase the physical distance between the two oscillators. The problem is that if the frequency divider is moved away, thermal equilibrium state cannot be guaranteed and the temperature information may be distorted. Also, the cycle time of the correction operation is long because the frequency divider is finely corrected, and special measuring equipment is required. There were problems such as the rate cannot be measured without using the .

In other words, the gate time of a normal rate measuring device is 2
You can choose a gate of seconds, 4 seconds, or even 10 seconds in some cases, but in any case, the cycle time of the temperature compensation operation should match this rate measuring device.
Failure to do so will not only cause inconvenience in terms of after-sales service, but also not be advantageous in terms of the production process.

Another method is a temperature compensation method that combines temperature measurement using a temperature-sensitive oscillator composed of MOS-FETs and frequency control by switching the capacitance of a crystal oscillator, which has already been proposed by the applicant. It has been done.

In this method, a capacitor configured to be intermittent by a switch such as a transmission gate is built into the IC for crystal oscillation, and this is controlled based on temperature information, so that the average rate depends on the intermittent time ratio. The maximum correction amount depends on the size of the switching capacitance. Although this method allows detailed correction in a short time, it also has drawbacks. In other words, in order to widen the temperature compensation range, the switching capacitance must be increased, but this will prevent the crystal oscillation conditions from being kept optimal, so there will be some sacrifice in both the compensation range and the oscillation conditions. There was a need to force it.

The purpose of the present invention is to solve the above problem, and to maintain the oscillation conditions of the crystal oscillator optimally,
An easy-to-handle, temperature-compensated electronic watch that is easy to handle and can be mass-produced. It is to provide watches.

In order to achieve the above object, the present invention provides a temperature compensation circuit having a temperature-sensitive oscillator constituted by a MOS transistor in the same IC chip as a clock circuit, and further includes a crystal resonator having quadratic temperature characteristics. The IC chip is mounted in close contact with the circuit board on which the temperature-sensitive oscillator and crystal resonator are mounted, and a capacitance switching method is used that allows precise correction to be made in a short time. The quadratic temperature characteristic is corrected into a step-like characteristic by the first correction means, and the step-like characteristic is flattened by the second correction means using a pulse interrupt method that can make large corrections at once. It is configured to correct to a straight line.

Hereinafter, the configuration of the present invention will be explained with reference to the drawings.

FIG. 1 is an embodiment block diagram showing the structure of an electronic timepiece according to the present invention.

1 is a crystal oscillator that can oscillate at two different frequencies by being equipped with a switch that changes the capacitance of the oscillation capacitor; 2 is a crystal oscillator that divides the signal from the crystal oscillator 1 and is equipped with an interrupt gate; A frequency divider circuit 3 is designed to be able to arbitrarily invert the frequency-divided signal in the middle, and 3 is a timer that synthesizes the signals from the frequency divider circuit 2 to create a time measurement signal and outputs a signal for displaying the time. The circuit 10 is a temperature compensation circuit that sends control signals to the switch of the crystal oscillator 1 and the interrupt gate of the frequency divider circuit 2.

Among the parts constituting the temperature compensation circuit 10,
4 has a temperature-sensitive oscillator and outputs digital information approximately proportional to the temperature; 9 has an internal 2
The temperature measuring circuit 4 has a multiplication means and a division means.
7 is a first storage means for storing the remainder calculated by the calculation circuit 9; A first register 8 is a second register as a second storage means for storing the quotient; 5 is a time-sharing circuit for sending control pulses to the switch of the crystal oscillator 1 while referring to the output information of the first register 7; This circuit constitutes the first correction means together with the switch. Reference numeral 6 denotes an interrupt circuit that sends a control signal to the interrupt gate of the frequency dividing circuit 2 while referring to the output information of the second register 8, and together with the interrupt gate constitutes a second correction means.

To explain the operation of FIG. 1, the crystal oscillator 1 oscillates at a lower frequency when the control signal potential from the time division circuit 5 is at a low level, and at a higher frequency when it is at a high level. The circuit 2 is configured to be accelerated every time the control signal from the interrupt circuit 6 is inverted.

The normal clock operation is always performed together with the clock circuit 3.

On the other hand, the temperature measuring circuit 4 and the arithmetic circuit 9 operate intermittently, and the temperature measuring circuit 4 measures the signal period of the internal temperature-sensitive oscillator and converts it into a numerical value, and also multiplies this numerical value by a specified constant or Add and
The resulting digital numerical information is output.

The arithmetic circuit 9 interprets the numerical information from the temperature measuring circuit 4 in sign using the most significant bit, squares it, further divides the squared result by a constant, and calculates the numerical information as a quotient and the numerical information as a remainder. Output.

The first register 7 stores numerical information as the remainder, and the second register 8 stores numerical information as the quotient. At this time, the first register 7 and the second register 8 hold the previous calculation result even during the calculation operation of the calculation circuit 9, and when a new calculation result is obtained, they are instantly rewritten at an optimal timing.

The time division circuit 5 operates in a 2-second cycle and constantly refers to information from the first register 7, and sends a pulse with a time width proportional to this information value to the crystal oscillator 1.
The voltage is applied to the changeover switch. The interrupt circuit 6 also operates in a 2-second cycle, constantly refers to information from the second register 8, and operates to invert the interrupt gate of the frequency divider circuit 2 a number of times equal to this information value.

In this embodiment, the 16KHz signal is inverted, so one interrupt operation is equivalent to a 15.26ppm correction.

FIG. 2 is a characteristic diagram showing the compensation characteristics of the temperature compensation circuit 4 in the present invention.

In the figure, the two quadratic curves indicated by broken lines are the frequency deviation Δf _L when the control pulse from the time division circuit 5 is at a low level, and the frequency deviation Δf _H when the control pulse is at a high level. The difference between the two (hereinafter referred to as Δf _SW ) is almost constant at any temperature.

Δf ₁ represents the characteristic when only the first correction means is activated, and represents how the quadratic curve, which is the original characteristic of the crystal, is corrected into a step-like characteristic by fine correction.

Δf ₂ indicates the case where both the first correction means and the second correction means work, and the stepped characteristic caused by the first correction means is further corrected by the second correction means, This shows that the temperature characteristics are flat over a wide temperature range. At this time,
At the peak temperature, Δf _H advances by more than 15 ppm,
The condition for Δf _L is that the deviation is zero, but this state may be achieved by adjusting the trimmer capacitor etc. after adjusting the temperature compensation circuit.
Since Δf _SW only needs to cover the difference in steps of the stairs, it can be smaller than the conventional method.

Further, the step difference in Δf ₁ that results in a step-like characteristic is determined by the value of the divisor used for division by the arithmetic circuit 9 and the magnitude of Δf _SW , and is determined by the correction step of the second correction means.
Adjusted to be approximately equal to 15.26ppm.
As a result, the step difference of Δf ₁ is exactly compensated for by the second correction means, and a flat characteristic is obtained.

FIG. 5 is a characteristic diagram illustrating in more detail the compensation characteristics conceptually shown in FIG. 2.

In the same figure, the two quadratic curves Δf _L ′ and Δf _H ′ indicated by broken lines are the quadratic curves Δf _L and Δf _H of FIG. 2, respectively.
The inverse quadratic curve Δf ₀ that makes the apex temperature equal to the quadratic curve Δf _L ′ is obtained by squaring the temperature information of the temperature measuring circuit 4. . In addition, the reverse quadratic curves Δf ₀₁ , Δf ₀₂ , Δf ₀₃ . . . shown by dashed-dotted lines are virtual shifts of the reverse quadratic curve Δf ₀ in order to explain the correction characteristics by the first correction means. be.

Furthermore, Δf ₂ ' is the corrected straight line Δf ₂ shown in FIG.
Although it is obtained by adding the two quadratic curves Δf _L ′ and Δf ₀ , the characteristic actually includes ripples due to digital correction. Next, the first correction characteristic and the second correction characteristic, which are the features of the present invention, will be explained.

First, a stepped characteristic curve Δf ₁ ' corresponding to Δf ₁ in FIG. 2 is obtained as a quotient obtained by dividing the inverse quadratic curve Δf ₀ which is correction data by a specified divisor. In principle, the value of the divisor is Δf _SW ′, which is the difference between the two quadratic curves Δf _L ′ and Δf _H ′, as shown in Figure 5, but in actual mass production, it is necessary to take into account the variation of each element. As shown in Figure 2, the value is set to be slightly smaller than Δf _SW .

By plotting the remainder versus temperature, a sawtooth characteristic curve Δf ₃ is then obtained. (The lower part of the sawtooth is satin-finished to make the curve easier to see.) This characteristic curve Δf ₃ is a sawtooth wave that repeats for each step width of the characteristic curve Δf ₁ ', and the slope of each sawtooth wave is shifted by 2. As can be seen from the fact that it is formed by the quadratic curves Δf ₀₁ , Δf ₀₂ . . . , it is the slope of the opposite quadratic curve Δf ₀ .

Next, the temperature correction operation using the above two characteristic curves Δf ₁ ' and Δf ₃ will be explained. First, in the case of temperature T ₁ , since there is no quotient, a corrected straight line Δf ₂ ' can be obtained by correcting only the value of the characteristic curve Δf ₃ , that is, the remainder. Also, in the case of temperature T ₂ , there is one quotient, so correction can be made by adding the value of the characteristic curve Δf ₃ to the value Δf _SW of the characteristic curve Δf ₁ ′, and furthermore, in the case of temperature T ₃ , the quotient is 3. Therefore, correction is performed by adding the value of the characteristic curve Δf ₃ to the value 3Δf _SW of the characteristic curve Δf ₁ '.

Also, to explain the above correction operation using the operation of the _circuit shown in _FIG . The second correction means, that is, the frequency dividing circuit performs variable frequency division once, and the first correction means performs frequency adjustment.
Furthermore, in the case of temperature T ₃ , the second correction means
At the same time, variable frequency division is performed twice, and frequency adjustment is performed by the first correction means.

By performing the above correction operation over the entire temperature range, a corrected straight line Δf ₂ ' can be obtained.

FIG. 3 is a circuit block diagram showing the configuration of FIG. 1 in more detail.

In the crystal oscillator 1, a crystal oscillator 22 is connected to an amplifier 21 including an inverter, a feedback resistor, and an oscillation capacitor, and a capacitor 25 that can be switched on and off by a changeover switch 24 is connected to the opposite side of a trimmer capacitor 23. It is structured as follows.

The frequency divider circuit 2 includes a frequency divider 26 which inputs the signal from the crystal oscillator 1 and divides the frequency by 1/2, and inverts its output signal _F1 by a control signal P6 from the interrupt circuit ₆ . , and a frequency divider 28 that further divides the frequency of the output signal F ₁ ' of the interrupt gate 27 to generate a time measurement unit signal and the like.

Among the parts constituting the temperature compensation circuit 4, the temperature measurement circuit 4 includes a temperature-sensitive oscillator 38 composed of a MOS-FET, etc., measures and digitizes the oscillation period τ of this oscillation signal, and also stores a memory described later. A cycle measuring circuit 39 multiplies the numerical information _K1 sent from the device 14, adds the numerical information _K2 , and further divides by a predetermined number to output the obtained remainder as temperature information T. It is configured.

In this embodiment, the predetermined number is ²⁸ ,
T is 8-bit temperature information.

The arithmetic circuit 9 has a squaring means and a division means, and the squaring means checks the sign of the temperature information T using the most significant bit, and then squares the remaining 7 bits to obtain the result. A squaring circuit 9 that outputs a signal P ₉₁ with a pulse width proportional to a 14-bit numerical value.
1, the dividing means consists of an AND gate 92 for using the signal _P91 as a gate signal, a first counter 93 that performs a counting operation using the frequency-divided signal passing through this gate 92 as an input signal, and this first counter 93. A matching circuit 95 detects a match between the value of a counter 1 counter 93 and numerical information K3 sent from a storage device ₁₄ to be described later and outputs a matching signal, and a matching circuit 95 receives the matching signal and a control signal _C1 as input signals. , an OR gate 96 that sends an output signal to the reset terminal of the first counter 93, and a second counter 94 that uses the control signal _C1 as an input signal to the reset terminal and counts the coincidence signal output from the coincidence circuit 95. It is composed of. 14 is a set value for regulating the operation of the temperature measurement circuit 4;
It is a storage device for storing K ₁ and K ₂ and a setting value K ₃ for regulating the operation of the arithmetic circuit 9, and K ₁ is numerical information specifying the sensitivity of temperature information T to temperature. , _K2 is numerical information for adjusting the offset of the temperature information T, and _K3 is numerical information specifying the divisor of the dividing means of the arithmetic circuit 9.

The first register 7 is an 8-bit latch circuit configured to read the value of the first counter 93 using the control signal _C2 as a synchronization signal.

The second register 8 is a 3-bit latch circuit and is configured to read the value of the second counter 94 using the control signal _C2 as a synchronization signal.

The time division circuit 5 that operates based on the information in the first register 7 is a negative trigger set type FF.
51 and a coincidence detection circuit 52, the coincidence detection circuit 52 inputs frequency-divided signals _F9 to _F16 of 512Hz to 0.5Hz as one data,
The configuration is such that 8-bit numerical information from the first register 7 is input as the other data.
The coincidence signal is input to the reset terminal of the FF 51.

The frequency divided signal F ₁₆ is also input to the set terminal of the FF 51, and the output pulse P ₅ of the time division circuit 5 is inputted to the set terminal of the FF 51.
is kept at a high level from the falling edge of _F16 until a match is detected. Therefore, the time division control pulse P ₅
is output once every 2 seconds, and its pulse width can be changed from 0 to about 2 seconds in steps of 1/128 seconds, and when this pulse is applied to the changeover switch 24 of the crystal oscillator 1, , ΔF _SW /256 ppm steps of correction can be made.

The interrupt circuit 6 includes a gate circuit for generating a pulse train whose input signals are the 3-bit information from the second register 8, the divided signals F ₁₄ and F ₁₅ from the frequency dividing circuit 2, and the inverted signals ₁₄ to ₁₆ ; The pulse train generation gate circuit is composed of a toggle type FF36.
a 4-input NAND 31 whose input signals are F ₁₄ , F ₁₅ , ₁₆ and the least significant bit of the second register 8;
A 3-input NAND 32 whose input signals are F ₁₄ , ₁₅ and the second-order bit of the second register 8; a 2-input NAND 33 whose input signals are _{F 14} and the most significant bit of the second register 8; and the three NANDs 31 ~
33, and an AND gate 35 which receives the output signal of the NAND 34 and the frequency-divided signal _F13 as input signals, and its output signal is applied to the toggle type FF36, After being frequency-divided by 2, it is sent to the frequency divider circuit 2 as an interrupt pulse _P6 .

As a result, the control signal P ₆ output from the interrupt circuit 6
The number of times F1 is inverted in two seconds matches the value of the second register 8, and is applied to the interrupt gate 27 of the frequency divider circuit 2, thereby inverting the 16KHz signal _F1 , so correction is performed in 15.26ppm steps. It turns out.

The storage device 14 is a P-ROM or a fuse.
The structure is such that the wiring pattern on the ROM or board is cut.

The operation shown in FIG. 3 will be explained in more detail as follows.

The oscillation period τ of the temperature-sensitive oscillator 38 included in the temperature measurement circuit 4 is, for example, 5×10 ^-4 seconds at 0°C and 7× at 50°C.
It has the characteristic that the oscillation period changes with temperature, such that it is 10 ^-4 seconds. Period measurement circuit 39
In order to convert this τ into temperature information T, τ is measured and digitized, and this value is multiplied by K ₁ and K ₂ is added.

A reference signal is required to measure τ, and in this embodiment, the frequency divided signal F ₂ from the frequency dividing circuit 2 is used, and the operation can be expressed as follows.

T=K ₁ ×τ×f _F2 +K ₂ −256×m ...(1) However, f _F2 is the frequency of the divided signal F ₂ , and m
is a positive integer, and assuming that there are more significant bits above the 8 bits representing T, this is the value of the more significant bits. In other words, τ is multiplied by K ₁ and the frequency divided signal F ₂
This shows that the remainder obtained by adding K ₂ to the time measurement result and dividing by 2 ⁸ is T. Note that this temperature measurement circuit has already been proposed by the applicant, so a detailed explanation will be omitted. It goes without saying that T is rounded down to an integer.

The temperature information T is again converted into time by the square means of the arithmetic circuit 9, and if the time length is t, then t
can be expressed as follows.

t=(T-128) ² /f _F ' ₁ (2) That is, t has the unit length of the period of the 16 KHz signal F' ₁ . Also, the most significant bit of T is treated as a sign bit. Note that depending on the circuit configuration of the squaring means, the following may occur.

t=(T−128) ² /f _F ′ ₁ (T≧128) t=(T−127) ² /f _F ′ ₁ (T<128) ……(3) Regarding this, there is an essential problem. Therefore, in this embodiment, the operation according to equation (2) is performed.
The value N obtained by counting the 2KHz signal _F4 using this time t as the gate time is as follows.

N=t/f _F4 , that is, N=(T-128) ² /8 (4) However, N is rounded down to an integer. Now, the second
If the value remaining in the counter 93 is N ₁ and the value remaining in the second counter 94 is N ₂ , then N and numerical information K ₃
The relationship is as follows.

N=K ₃ ×N ₂ +N ₁ (5) That is, N ₁ and N ₂ represent the remainder and quotient when N is divided by K ₃ . At this time, the correction amount _H1 by the first correction means is as follows.

H ₁ =Δf _SW ×N ₁ /256 [ppm] (6) Then, the correction amount H ₂ by the second correction means is as follows.

H ₂ = 15.26×N ₂ [ppm] …(7) Here, if the condition Δf _SW ×K ₃ = 15.26×256 is satisfied, the total correction amount H including both is N
It can be expressed in relation to

H=Δf _SW ×N/256 [ppm] or H=15.26×N/K ₃ [ppm]} ...(8) Since N is a quadratic function of T as shown in equation (4), The secondary characteristics of the crystal oscillator can be corrected by adjusting T to appropriate characteristics using the numerical information K ₁ and K ₂ .

Furthermore, by setting K ₃ , Δf _SW is 15.26ppm.
Even if the difference is larger than 15.26 ppm, the step of correction by the first correction means can be restricted to 15.26 ppm, and can be made to match the correction step of the second correction means, so that the cooperation between both correction means can be made smooth.

In this embodiment, the arithmetic circuit 9 has a squaring means and a dividing means, but by further having an adding means, it is possible to perform not only temperature compensation but also rate adjustment at the same time. You can do it as you like.

That is, based on the three numerical information K ₁ , K ₂ , K ₃ , the temperature compensation circuit 10 corrects the temperature characteristic to a flat straight line that touches the slower frequency temperature characteristic of the crystal oscillator at one point. In order to translate this flat characteristic and make the deviation zero, the trimmer capacitor must be rotated. This process is not much of a problem with regular electronic clocks that have a monthly difference of about 10 to 20 seconds, but it suddenly becomes a big problem when you try to achieve higher precision. It goes without saying that unless this problem is solved, high accuracy cannot be obtained no matter how flat the temperature characteristics are. The temperature compensation circuit of the present invention will be explained because a means for processing this rate adjustment by digital numerical setting can be easily introduced.

FIG. 4 shows, for the above purpose, that instead of resetting the first counter 93 and the second counter 94 in the arithmetic circuit 9 by the control signal _C1 at the start of computation, separately specified numerical information is preset. FIG. 2 is a circuit block diagram showing the configuration of an arithmetic circuit 9'.

The first counter 93' reads data in synchronization with the output signal of the OR gate 96, so it is preset every time there is a carry, and the second counter 94' is preset in synchronization with the control signal _C1 prior to the counting operation. be done. This preset numerical information is added to both counters 93' and 94', and the correction amount of the first correction means and the second correction means uniformly increases by this value at all temperatures. become. Therefore, by appropriately selecting this value, the flat characteristic due to temperature compensation can be made to have zero deviation.

Although the portion related to this preset operation overlaps with the division means, it can be considered as an addition means. Moreover, the addition means is not the preset method described above, but the first counter 93 and the second counter 93.
A method of adding numerical information using an adder after the counting operation of the counter is completed is also considered, and instead of providing an adding means in the arithmetic circuit 9, the time division circuit 5
Alternatively, the interrupt circuit 6 can be equipped with an adding means.

It goes without saying that the present invention can be easily implemented even when the oscillation frequency of the temperature-sensitive oscillator is proportional or inversely proportional to the temperature. Furthermore, the correction by the second correction means is not limited to 15.26ppm steps;
If the 32KHz signal is inverted and corrected, the step will be 7.63ppm, and if the 8KHz signal is inverted, the step will be 30.52ppm, and if the first correction means is corrected accordingly, it will be equally good. It is possible to realize a system that At this time, the number of bits in the second counter is not limited to 3 bits, but in particular
If the step is 7.63ppm, it should be increased.

As described above, the electronic timepiece of the present invention includes a temperature measurement circuit that outputs temperature information approximately proportional to temperature, a first correction means that controls the frequency of the crystal oscillator,
a second correction means for controlling the operation of the frequency dividing circuit;
By having a multiplication means and a division means or an addition means, the temperature information from the temperature measurement circuit is squared, and the squared result is divided by a specified divisor to calculate a quotient and a remainder, or the quotient and the remainder are calculated by an arithmetic circuit that adds a specified constant to the remainder; a first register that stores the remainder or the value obtained by adding a constant to the remainder; and a first register that stores the quotient or the value obtained by adding another constant to the quotient. a second register, the first correction means is controlled by the value of the first register, and the second correction means is controlled by the value of the second register. It realizes temperature compensation over a uniquely wide temperature range and also performs rate adjustment at the same time, and can maintain high accuracy even when stored in any environment where humans can live. Because the cycle time is short, rate measurement can be performed quickly, and it also provides an excellent temperature compensation method that avoids the increase in rate adjustment process that is common with high-precision products, and in fact reduces it, which will lead to the future development of electronic watches. This will greatly contribute to the

[Brief explanation of the drawing]

FIG. 1 is an embodiment block diagram showing the basic configuration of the present invention, FIG. 2 is a temperature characteristic diagram showing the temperature compensation operation of the present invention, FIG. 3 is a circuit block diagram showing the configuration of FIG. 1 in more detail, and FIG. FIG. 4 is a main circuit block diagram showing another embodiment. FIG. 5 is a characteristic diagram illustrating in detail the compensation characteristics of the present invention. 4... Temperature compensation circuit, 5... Time division circuit, 6...
...Interrupt circuit, 7...First register, 8...Second register, 9...Arithmetic circuit.

Claims (1)

[Scope of Claims] 1. A crystal oscillator whose frequency-temperature characteristics are approximately quadratic, a frequency dividing circuit that creates a time measurement unit signal from the output of the crystal oscillator, and a temperature measurement circuit that outputs temperature information approximately proportional to temperature. A temperature compensated electronic timepiece comprising: a first correction means for controlling the oscillation frequency of the crystal oscillator; a second correction means for controlling the operation of the frequency dividing circuit; an arithmetic circuit having a squaring means for squaring numerical information of , and a division means for further dividing the squaring result by a specified divisor to calculate a quotient and a remainder; and a first circuit for storing the remainder. storage means and a second storage means for storing the quotient, the first correction means is controlled by information from the first storage means, and the second correction means is controlled by information from the second storage means.
An electronic timepiece with temperature compensation, characterized in that the temperature-compensated electronic timepiece is configured to control a correction means. 2. The temperature compensated electronic timepiece according to claim 1, wherein the arithmetic circuit has addition means for adding a separately specified constant to the quotient and remainder obtained by division.