JPH0241713B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention corrects changes in the frequency of a crystal oscillator with respect to temperature using the digital output of a temperature measurement circuit.
The present invention relates to a temperature-compensated electronic timepiece that obtains a timekeeping unit signal that is independent of temperature.

Conventionally, many methods have been proposed for sensing ambient temperature and temperature-compensating a crystal oscillator serving as a reference oscillator, and several methods have been put to practical use in small electronic devices such as electronic watches. Among these, a frequency divider as a unit signal generation circuit is equipped with a correction means such as pulse insertion, for example, in an electronic watch having a crystal oscillation circuit with an oscillation frequency in the 32KHz range,
It is a coarse resolution correction of 1/32768 seconds per second,
In order to increase the resolution, corrections must be made every few tens of seconds, which requires a special rate measuring device for watches.

Furthermore, when a crystal oscillation circuit is provided with correction means such as time-division switching of the oscillation capacitance and the compensation temperature range is widened, a design that can accommodate large changes in the oscillation capacitance value is required. In other words, conventional electronic watches with temperature compensation have limitations in terms of measurement and design.

An object of the present invention is to eliminate the above-mentioned limitations, and to provide a temperature compensated electronic timepiece that can easily measure the rate in a short time using a general electronic timepiece rate measuring device, has an easy crystal oscillator design, and has a wide compensation temperature range. It's about doing. Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the basic configuration of an electronic timepiece according to an embodiment of the present invention, in which 1 is a crystal oscillation circuit as a reference crystal oscillator equipped with a first correction means 1c for controlling the oscillation frequency, and 2 is a pulse 3 is a display device including a display mechanism and a circuit for driving the same; 4 is a temperature measurement circuit including a temperature sensor and a temperature register 4r. 5 is a correction signal synthesis circuit that generates frequency correction signals Pc and Pi for temperature compensation of the first correction means 1c and the second correction means 2c based on the signal of the temperature register 4r.

FIG. 2 is a circuit block diagram showing the above configuration in detail. The crystal oscillation circuit 1 includes a 32768 Hz crystal oscillator 1a, an oscillation inverter 1b, a stabilizing resistor R ₁ , a feedback resistor R ₂ , an input side capacitance C _io , and an output side It is constructed by a well-known configuration including a capacitor _Cput , a switch 1c constituting the first correction means, and a switching capacitor _CSW switched by the switch 1c. This switch 1c
are turned off and on by the logic "1" and logic "0" of the time-series pulse signal Pc, which will be described later, and when the oscillation frequencies of the crystal oscillation circuit 1 are F _H and F _L , respectively, the output capacitance of the oscillation inverter 1b is is the output side capacitance C _put when the switch 1c is off, and becomes the output side capacitance C _put plus the switching capacitance C _SW when the switch 1c is on, so that F _H > F _L
becomes. Here, we set F _SW =F _H −F _L , and in this application, we consider the range of normal use, so F _SW
is treated as constant.

The frequency dividing circuit 2 has a well-known configuration of an initial frequency dividing circuit 11, a first frequency dividing circuit 12 following it, a second frequency dividing circuit 13 following it, and an exclusive OR circuit 2c constituting a second correction means. configured. This exclusive OR circuit 2c receives an interrupt pulse signal Pi, which will be described later.
This constitutes a known means for interrupting the time measurement unit signal generation circuit 2.

That is, excluding the first correction means 1c and the second correction means 2c, the crystal oscillation circuit 1, the frequency dividing circuit 2,
The display device 3 constitutes a normal crystal electronic timepiece.

The temperature measuring circuit 4 has an internal temperature sensor and outputs temperature information as a linear digital value with respect to temperature, and is similar to a general digital thermometer. However, the temperature information value is not an absolute value of temperature, but is set in the temperature register 4r as an appropriate function value according to the setting conditions of the crystal oscillation circuit 1, as described later.
This temperature register 4r outputs a 10-bit temperature information signal T of T ₀ , T _{1 .} . . T ₉ .

The correction signal synthesis circuit 5 is the time series pulse generation circuit 1
8 and an interrupt pulse generation circuit 17.
The time-series pulse generation circuit 18 includes a first comparator 15, a second comparator 14, and a pulse synthesis circuit 16, and the first correction means of the crystal oscillation circuit 1 uses the lower 8 bits of the temperature information signal T. A time-series pulse signal Pc is created to control the on/off of the switch 1c in a time-series manner.

The interrupt pulse generation circuit 17 receives the temperature information signal T.
Thus, an interrupt pulse signal Pi to be input to the exclusive OR circuit 2c, which is the second correction means of the frequency dividing circuit 2, is created.

In the correction signal synthesis circuit 5, the time series pulse generation circuit 18 and the interrupt pulse generation circuit 17 are circuits that generate signals for controlling the first and second correction means, respectively. The second correction means directly controls the oscillation frequency of the crystal oscillation circuit 1, and the second correction means controls the number of pulses in the clock unit signal generation circuit 2, so each circuit can be discussed completely independently. can.

Next, the time series pulse generation circuit 18 and the interrupt pulse generation circuit 17 will be explained in order.

FIG. 3 is a circuit block diagram for explaining the time-series pulse generation circuit 18 in detail.

The first stage frequency divider 11 consists of two flip-flops (hereinafter abbreviated as FF), and the first and second frequency dividers 1
2 and 13 consist of seven FFs, and the outputs from the FFs of the first and second frequency dividers are connected to the first comparator 15 and the second comparator 14, respectively. 1st
The comparator 15 receives the 7-bit input signal F ₀ on the frequency divider side.
Compares the FF15b that falls triggered by the negative edge _{of F6 of F6, the lower 7 bits T0 to T6 of the temperature} information signal T, and the input signal on the frequency divider side, and outputs a matching signal; The second comparator 14 also includes the FF 14b and the coincidence circuit 14.
They have exactly the same configuration due to a. The pulse synthesis unit 16 includes an AND gate 16b whose input signals are T ₇ of the temperature information signal T and the output pulses P ₁ and P ₂ of the first comparator 15 and the second comparator 14;
It is composed of a NOR gate 16c and an OR gate 16a which receives the signals from both gates as input signals.

Next, time series pulse generation circuit 1 having the above configuration
8 will be explained below. Lower 7 of temperature information signal T
The value indicated by bits T ₀ to _{T 6} is set to n, and the first frequency divider 12
Both comparators 15 when the signal period of F ₀ is 1,
The periods of the 14 output pulses P ₁ and P ₂ are respectively
128 and 16384, and the time ratio of logic "1" to the duty, that is, the period, of the signal waveform is both n/128. The pulse synthesis unit 16 fixes the output of the NOR gate 16c to logic "0" when _T7 of the temperature information signal T is logic "1", and fixes the output of the NOR gate 16c to logic "0".
, outputs an AND signal P ₁ .P ₂ of P ₁ and P ₂ , passes through an OR gate, and becomes a time-series pulse signal Pc. Therefore, the time during which this signal Pc is logic "1" during the period of 16384 is ⁿ² , and the time ratio (hereinafter referred to as correction factor) is as follows.

= n ² / 16384 On the other hand, when T ₇ is logic “0”, AND gate 1
The output of 6b is fixed to logic "0", and the inverted signal ₁ of _P1 and the inverted signal ₂ of P2 _are output from the NOR gate 16c.
Outputs AND signals ₁ and ₂ with OR gate 1
6a to become a time-series pulse signal Pc. Therefore, the time when this signal Pc is logic “1” is (128−
n) becomes ² . From the above, the above n is the temperature information signal T
The lower 8 bits are the 8-bit temperature information signal.
It has the following relationship with Tc.

n=Tc (0≦Tc<128) n=Tc−128 (128≧Tc≦255) Therefore, the correction factor is as follows.

= (Tc−128) ² /16384 (0≦Tc≦255) In this way, the time series pulse generation circuit 18 in the electronic watch of the present invention converts Tc, which is temperature information, into 2
It is converted to the following function.

FIG. 4 is a temperature characteristic diagram of the electronic timepiece of the present invention, in which FIG. 4a shows the temperature characteristics of the crystal oscillation circuit 1 and the timekeeping unit signal, and FIG. 4b shows the logic "1" of the time-series pulse signal Pc. FIG. 4c shows the temperature characteristic of the temperature information signal T. Note that the horizontal axis θ represents temperature, but the fourth
The relative temperature is determined relatively from the frequency deviation relationship shown in Figure a.

In Fig. 4a, the vertical axis is taken as the relative deviation of the frequency, and the crystal oscillation circuit 1 changes the oscillation frequencies F _H and F _L with respect to the logic "1" and logic "0" of the time-series pulse signal Pc by switching. It has already been explained that the difference between the frequencies is F _SW , but F _L is a frequency that does not lead or lag the clock at the peak temperature ZT, that is, it is adjusted to zero deviation, and the deviation of each frequency is calculated as the peak temperature. The frequency of F _L at ZT, that is, the reference frequency F ₀ is expressed by the following equation.

f _L =F _L /F ₀ =a×(θ−ZT) ² f _H =F _H /F ₀ =a×(θ−ZT) ² +f _SW However, f _SW =F _SW /F ₀ Note that θ is the temperature , a is the quadratic temperature coefficient, ZT is the peak temperature, and as mentioned above, F _SW is constant due to F _SW
is also constant. Also, fc in the figure is a time series pulse signal
This is the average frequency as a result of temperature compensation by Pc, and is equal to the frequency deviation averaged within the period of the most significant bit of the second frequency divider 13, that is, in this embodiment, in 2 seconds. Note that f _W will be described later.

The correction factor can be thought of as the time ratio of oscillation at _fH , and as already explained, it becomes a quadratic function as shown in FIG. 4b.

At this time, the average frequency deviation fc can be expressed as fc=f _L ×(1−)+f _H ×. If we rewrite it further, we get fc=a×(θ−ZT) ² +f _SW ×(Tc−128) ² /16384, and since it is ideal for this to be zero, considering the conditions for T It can be seen that fc=0 when . According to this equation, T needs to be set by a linear function of θ, and this is set by a generally known method as already explained.

In FIG. 4c, the strictly stepped digital values of the 10-bit temperature information signal T are shown as solid lines, and the 8-bit temperature information value Tc consisting of the lower 8 bits of this temperature information signal T is similarly shown as the broken line. It is shown. Here, the upper 2 bits of the temperature information signal T (T ₈ , T ₉ )
The regions where the values are (1, 1), (0, 0), and (0, 1) are defined as the left region, middle region, and right region, and temperature compensation in these ranges will be described below.

In Figure 4a, the middle region where the frequency deviation is zero between f _H and f _L can be temperature compensated to zero frequency deviation,
At this time, the 8-bit temperature information signal Tc is set to take a value between 0 and 255 as shown in FIG. 4c. Since the temperature is compensated in the same way in the left and right regions, the secondary characteristics are compensated as shown in Figure 4a.
It shows first-order characteristics with respect to temperature. The interrupt pulse signal Pi, which will be explained next, compensates for this primary characteristic in the left and right regions by temperature, and as shown in Figure 4a, the average frequency deviation of the final unit signal for timekeeping, that is, the clock rate.
f _W is obtained.

FIG. 5 is a circuit block diagram for explaining the interrupt pulse generating circuit 17 in detail.

71 is a timer which outputs a pulse signal every certain period TM to the preset enable input terminal PE of the up-down counter 72 and the set reset FF.
It is supplied to the set input terminal S of 73. The up-down counter 72 inputs the most significant bit _T9 of the temperature information signal from the up-down mode input terminal UD, that is, the up-down counter 72 inputs the most significant bit _T9 of the temperature information signal from the up-down mode input terminal UD. It operates as a down counter, and is initially set to the 8-bit temperature information signal Tc, that is, _T0 to _T7 , by the input signal from the preset enable terminal PE, and performs up or down counting operation by the input signal from the input terminal IN. , which has a known specification in which a zero detection signal is output from the zero detection output terminal Z when the contents of the counter become zero.

The reset FF 73 has a set input terminal supplied with a pulse signal from the timer 71, and a reset input terminal R supplied with a zero detection signal from the up-down counter 72. The AND gate 74 receives a signal from the output terminal Q of the set reset FF73, an output signal from an OR gate 75 which receives the upper two bits _T8 and _T9 of the temperature information signal T, and an 8KHz signal as a synchronization signal. The output signal is supplied to the input terminal IN of the up-down counter 72, and passes through a known delay circuit 76 to become an interrupt pulse signal Pi. Note that the pulse interrupt means using the delay circuit 76 and the exclusive OR circuit 10 is already known.

Next, the interrupt pulse generation circuit 17 having the above configuration
Explain the operation.

When both T ₈ and T ₉ are logic “0”, that is, in the middle region, the OR gate 75 outputs logic “0” and the AND
Gate 74 is closed and no interrupt pulse signal Pi is output. T ₈ and T ₉ are respectively logic “1” and logic “0”,
That is, in the right region, the up-down counter 72 operates as a down counter, and this down counter is preset by the timer 71 to the value of the 8-bit temperature information signal Tc every time TM.
The AND gate passes the synchronization signal until the contents of this counter become zero, counts down the counter, and outputs the synchronization signal through the delay circuit 76 as an interrupt pulse signal Pi.

As a result, if the average frequency deviation f right due to the interrupt pulse signal Pi is considered as an average over time TM, it can be expressed by the following equation.

f right=Tc/F ₀ ×TM When both T ₈ and T ₉ are logic “1”, that is, in the left region, the operation is similar to that in the right region described above, except that the up-down counter 73 operates as an up counter. The average frequency deviation f left due to the interrupt pulse signal Pi in this left region is similarly expressed by the following equation.

f left = 256-Tc/F ₀ ×TM The average frequency deviation due to this interrupt pulse signal Pi is proportional to Tc and 256-Tc in the right region and left region, respectively, and f _c in Figure 4 a and c From the relationship of Tc,
If the period TM of the timer 71 is selected appropriately, Fig. 4a
It can be seen that the clock rate f _W as shown in can be realized. The period of this timer 71 is determined by the following equation.

TM=-256/8×9×ZT ² ×F ₀ For example, a=-0.035ppm/℃ ² , ZT=25°, F ₀ =
At 32768Hz, TM is approximately 44.6 seconds. Regarding the setting of this timer period TM, it is possible to set it using an external terminal or using a ROM, but in practice, when it is stable for mass production, it is fixed at TM = 45 seconds in the above numerical example. can be handled.

Next, this example will be explained with specific numerical values. In Figure 4 a, ZT is 25℃ and the relative temperature θ
Consider the case where is made equal to the absolute temperature.

When the secondary temperature coefficient a=-0.035, f _SW =|a×(θ−ZT) ² |, so f _SW becomes 21.875 ppm, which is a value that can be easily achieved by switching the capacitance. At this time, the middle range is 0 to 50°C, which covers the normal ambient temperature and rate measurement temperature of electronic watches. In this medium range, this embodiment can measure the rate in units of 2 seconds. Therefore, in the left and right regions, the only problem is the lead or lag in the integration of the electronic clock, and this embodiment corrects this by using a pulse interrupt every period TM.

As described above, according to the present invention, the first correction means for correcting the oscillation frequency of the crystal oscillation circuit and the second correction means for correcting the frequency division ratio of the frequency dividing circuit are used together, so that Compared to the conventional method using a single correction means, it is possible to correct the quadratic curve of the frequency-temperature characteristic of the crystal oscillation circuit with high precision over a wide temperature range, and moreover, it is possible to correct the quadratic curve of the frequency-temperature characteristic of the crystal oscillation circuit with high precision over a wide temperature range. zero temperature coefficient temperature
In the vicinity of ZT, the first correction method is correction using only changes in the oscillation frequency, making it possible to measure the rate of a watch in a short period of time. It enables faster market service.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the electronic timepiece of the present invention;
1 is a circuit block diagram for explaining in detail the circuit shown in FIG. 1, and FIGS. Figure 4 is the first
FIG. 3 is a temperature characteristic diagram for explaining the temperature characteristics of the electronic timepiece shown in the figure. 1... Crystal oscillation circuit, 2... Frequency dividing circuit, 1c...
...First correction means, 2c...Second correction means, 4
r...temperature register, 5...correction signal synthesis circuit,
17... Interrupt pulse generation circuit, 18... Time series pulse generation circuit.

Claims (1)

[Claims] 1. A temperature-compensated electronic timepiece that includes a crystal oscillator whose frequency-temperature characteristic is a quadratic curve, a frequency dividing circuit that creates a time measurement unit signal from the output of the crystal oscillator, and a temperature measurement circuit. The temperature measurement circuit detects the ambient temperature, and provides middle region information including a zero temperature system region of a quadratic curve in the crystal oscillator, left region information on a lower temperature side than the middle region information, and information on a left region on a lower temperature side than the middle region information. a first correcting means for controlling the oscillation frequency of the crystal oscillator; and a second correcting means for controlling the operation of the frequency dividing circuit.
the first correction means is operated according to the middle region information from the temperature measurement circuit to control the crystal oscillator, and the first correction means is operated according to the left region information and the right region information 1. An electronic timepiece with temperature compensation, characterized in that temperature compensation is performed over a wide range by combining oscillation frequency control and frequency division ratio control by operating the correction means of 2 to control the frequency dividing circuit.