JPS6025485A - Electronic timepiece - Google Patents

Abstract

PURPOSE:To make a fast-slow adjustment easily by incorporating a circuit which calculates a fast-flow corrected value and a circuit which corrects it in a timepiece. CONSTITUTION:A 1/2 frequency dividing circuit 8 is used as a counter and pulses are applied from a reference pulse signal input terminal 2 exactly for eight seconds to detect an error of about 1/8Hz. An arithmetic circuit 3 calculates a capacity value to be corrected and the switch of an oscillation circuit OSC is controlled on the basis of the result to correct the capacity. A capacitor 10 for correction is set to such a capacity value that a delay of 10sec monthly difference is correctable, a capacity 11 for correction is set to such a capacity value that a delay of 20sec monthly difference is correctable, and a capacity 12 for correction is set to such a capacity value that a delay of 40sec monthly difference is correctable, so that the arithmetic circuit 3 may merely be a state storage circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece having a speed adjustment function.

Generally, a crystal oscillator is used as the reference time signal source for electronic watches, and in order to reduce power consumption, it is combined with a complementary MOS F'KT' (hereinafter abbreviated as C1-MOS) inverter. The oscillation circuit is f? It's four years old. Oscillation by a crystal oscillator is extremely stable.
Although it is an excellent product with little change over time, when it was produced in large quantities, it was found that variations in the natural resonant frequency of the crystal resonator,
The oscillation frequency fluctuates due to variations in the oscillation circuit constants. Such fluctuations in the oscillation frequency are an error in the reference time signal and cause the clock to become incorrect, so even in crystal oscillation electronic watches, the reference time signal must be able to be adjusted by some means. . 1 like this
What is the timing of the L child clock? JI MM
A conventionally well-known method for this purpose is to change the capacitance of a trimmer capacitor, as shown in FIG. In this method, the oscillation frequency is changed by changing the oscillation circuit constants. In addition, there is another method called so-called logical adjustment. In this method, as shown in FIG. 4, the combined capacitance 17t of the capacitor is changed by changing the switch to obtain the same effect as the regression shown in FIG. 3. fL9η Theory, Slow, Rapid B (Another method of the it node circuit is the circuit shown in No. 5 [4]. In this method,
Although the oscillation frequency itself is not changed, the frequency division ratio is changed by the logic circuit.

In the logical adjustment circuit, the trimmer capacitor shown in FIG. 3 can be omitted, so it is possible to reduce the size of the circuit. Furthermore, since the natural resonance frequency of the crystal resonator can be varied over a wide range, the cost of components can be reduced overall. In addition, when a temperature sensor is used in combination, it is possible to correct fluctuations in the oscillation frequency due to changes in 11'1^1), making it possible to create extremely accurate timing. Although the electronic circuit part is somewhat complicated, it is not a problem because it is integrated into many circuits along with the clock circuit. As described above, the logical slowdown N7j faj method has many advantages, but on the other hand, it also has the drawback that the slowdown/speed loop N7j faj method becomes very complicated. Unless specifically shown in Figure 4, the oscillation frequency of the circuit must be measured when the oscillation frequency of the circuit is not changed by Yj. Oscillation frequency, i.e. f1
It is necessary to calculate the difference between the frequency and the frequency at which there is no delay at all, and how much correction is necessary. Then, the obtained correction value must be set, and finally, the h-th step must be performed to determine whether the correction has been performed as intended. For this reason, a special adjustment device for the adjustment is required, and since it takes a long time to adjust one clock, the production cost for the completed clock increases. Furthermore, as a method to set the correction value, it would normally be desirable to use a switch, etc., but due to the desire to make watches smaller and cheaper, switches etc. are not used, and the method of setting the correction value is such as cutting or shorting the circuit wiring. In many cases, the correction value is set using a method, but if correction is performed through such destructive work, the value to be corrected may be wrong, or the oscillation frequency of time bar 1 may fluctuate due to aging. hand,
Furthermore, even if correction becomes necessary, there is also the disadvantage that it cannot be corrected again. In addition, one -, rearrangement 1j
Since it is impossible to adjust many watches to the same 110° angle at the same time, this becomes an obstacle in mass production.

In order to eliminate the above-mentioned drawbacks, the present invention has a built-in circuit for calculating a slow/sudden correction value and a circuit for correcting it.

In other words, by a standard time signal applied externally,
Jigen 1 itself is characterized by internal calibration.

The present invention will be described in detail below based on Examples. FIG. 1 shows an embodiment of the present invention, in which 1 is a clock circuit equipped with a conventional logic adjustment circuit, 2 is a reference pulse signal input terminal, and 3 is a clock circuit equipped with a conventional logic adjustment circuit.
4 is a correction value calculation circuit, and 4 is a control circuit. Currently, 32,768 KHz crystals are used for watches! Ribs are often used. If a clock made using this crystal oscillator advances by 10 seconds in one month, the i12 frequency at this time is calculated backwards as 52.768126KH2. Only O,l 26 Hz was out of order. In order to detect such a slight deviation in fl: using a frequency counter, repeated counting must be continued for at least 8 seconds. In this embodiment, the frequency dividing circuit is used as a counter as it is, and by adding an accurate 8 second pulse from the reference pulse signal input terminal 2, J:'),
An error of about 1/8 Hz is detected. and,
Calculate the capacitance ze that should be corrected using the arithmetic circuit 3,
Based on the results, the switches of the oscillation circuit are controlled and the capacitance is corrected. To perform the most simple correction, set the correction capacitor 10 to a capacity value that can correct a 10 second delay per month, and set the correction capacitor 11 to a capacitance value that can correct a 20 second delay per month. If the capacitance value of the lens 12 is set to a value that can correct a 40 second delay per month, the arithmetic circuit may be fJ, a simple bright memory circuit as shown in Fig. 2. because,
If the output 20 of the first stage flip-flop is at logic level II 11I, the monthly difference is 10 seconds, and the output 21 of the second stage flip-flop is at logic level °
This is because ``1'' indicates an advance of 20 seconds per month, and if the output 22 of the third stage flip-flop is at logic level 1'', each independently indicates an advance of 40 seconds per month. . With the above constants, it is possible to correct for advances of up to 70 seconds per month. Since further correction is not possible, the crystal resonator should be manufactured so that its characteristic fluctuations fall within this range. If it is necessary to detect that correction is impossible, it can be easily detected by determining the outputs of the fourth and subsequent flip-flops using a logic circuit. In addition, as another embodiment, it is also possible to apply a method of logically slowing down or slowing down RL'i fj'l by changing the frequency division ratio, as shown in FIG. 5, or using these two methods at the same time. It is also effective to do so. In addition, since temperature correction can also be performed by adding the signal from the temperature sensor to the arithmetic circuit, it is possible to obtain extremely high precision and high stability electronic operation. In either case, a control circuit or arithmetic circuit is required, but in most cases,
Since they are composed of relatively simple logic circuits, there is no problem in actual Jj:Ij.

t "Oh, in the actual Jiffi example, the frequency divider circuit inside the clock is used as a frequency counter, but the embodiment of this patent is not limited to this. For example, the basic 75 hour signal generated in a clock Whether it is a method of comparing the pulse 1llAI of 1llAI and a standard pulse width supplied from the outside, or a method of counting the oscillation frequency and the standard frequency and finding the difference, as long as the processing is performed inside the clock circuit, σ] which basically has the same effect.

As explained above, by using unexploded 1uJ, the practicality of the logical adjustment method will be significantly increased. In other words, the conventional system required a special dedicated adjustment device to adjust the speed and speed of the clock, but by implementing the present invention, a large number of standard time signal source devices can be used with just one standard time signal source device. Since the speed and speed adjustment of several watches can be performed at the same time, the time required for adjustment of each watch can be extremely shortened, which is very advantageous in Watch Production-1-1. Furthermore, since the cost of the device for adjustment is low, combined with the above-mentioned effects, it becomes possible to reduce the cost of adjusting the watch. Use of the present invention also provides advantages in terms of after-sales service. This is because in the conventional logical adjustment method, a dedicated y
:a Due to the need for adjustment equipment and (,'jj:, 1 so! setting of correction values,
It has not been possible to carry out FJiΔ harm at general timepiece stores or watch repair shops, but if the present invention is applied in practice, it will be possible to perform the FJIΔ problem no matter where there is a signal source (1 hour signal source). This is because you will be able to perform sudden nL'l!fii+.Furthermore, due to repairs etc., the crystal oscillator, circuit)
Even if the 11ζ product is replaced, or even if the time Wl becomes incorrect due to age-related changes in the oscillation circuit components, as mentioned above, the 3% slow and fast adjustment can be performed. Benefits also arise.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of an electronic watch that implements the invention, t('S
21! ''' is a diagram showing an example of an arithmetic circuit of a Yu-sen-ny meter embodying the present invention, and FIG. 3 is a diagram showing an example of a crystal oscillation circuit for electronic mode. Figure 4 shows the conventional logical moderation W, + (with clause function -
FIG. 5 is a diagram showing an example of the structure of another conventional logical bond sharpening fWj method, and the numbers in each figure are 1. [The one shown is shown below.] 1...Construction diagram of an electronic H1 meter with conventional logical slowing/slowing MfRj 4-wave function 2...Reference time signal input terminal 3...Arithmetic circuit 4...・・Control circuit 5・・・Crystal oscillator 6・・・Oscillation inverter 7・・・Trimmer capacitor for slow/sudden adjustment 8°
,,,172 Frequency divider circuit 9...1/1o Frequency divider circuit 10.11.12...Capacitor for adjusting speed and above Applicant Suwa Seikosha Co., Ltd. Kokozutaku 5 concave

Claims (1)

[Claims] In an electronic clock that has a part that generates a reference time signal, electrically processes the reference time signal to produce a time signal, and displays this, the standard time signal supplied from the outside and the time signal are 41i sub-clock, characterized in that it has a built-in circuit for comparing the reference time signal generated internally with the reference time signal, and a circuit for correcting the speed and speed of the watch.