JPS6057030B2 - electronic clock - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece having two oscillation circuits using crystal oscillators, etc., and which performs gate switching to double-play the frequency error of each oscillator, thereby achieving highly accurate timekeeping. The purpose is to enable display.

In electronic watches, such as watches that use a crystal oscillator,
There is usually one crystal oscillator circuit, but in this case, the frequency accuracy of the crystal oscillator must be within a predetermined tolerance range depending on the daily or monthly difference of the clock that uses it. .

For example, in a watch that guarantees a daily difference of ±0.1 seconds, the tolerance of the crystal oscillator is approximately 0.1 x 10-5, which means that the daily difference is ±0.0 seconds.
The crystal oscillator frequency tolerance of the watch that provides the 'th guarantee is approximately 2 x 10-7. This is the result of fixing the electronic circuits that make up the crystal clock, especially the counter circuit, and placing all of the clock accuracy on the oscillation circuit. Therefore, although the productivity of the clock circuit section is extremely high, the manufacturing process of the crystal resonator itself becomes complicated and the cost of the resonator increases. The resonator manufacturing process involves cutting out the resonator using etching and other techniques.
A multi-stage adjustment process including primary miscellaneous adjustment and secondary precision adjustment is required. Furthermore, in order to obtain the desired accuracy, a trimmer capacitor is finally added to the circuit for fine adjustment. Vibrators that are found to be unable to achieve the desired accuracy through a series of these steps or during the process are rejected as defective products. Therefore, in order to increase the yield of crystal, the management of each process must be several orders of magnitude higher in quality than the management of general electronic components, and it is necessary to This is why it is considered a high-cost component compared to electronic components. Furthermore, in the case of a quartz watch with a single oscillator, the temperature coefficient of the quartz crystal was a factor that determined the accuracy.

The temperature frequency characteristics of crystal oscillators used in watches are usually 2.
It is expressed by the following or cubic curve, and it has been difficult to perform temperature correction over a wide range. It is generally recognized that it is better to adopt an AT-cut type crystal oscillator for watches that are expected to have high precision especially over a wide temperature range, but the AT-cut type crystal has a lower vibration frequency than other types. , which is more than two orders of magnitude higher than others in terms of circuit response, power consumption, etc. The present invention aims to eliminate these drawbacks and provide an electronic timepiece that can be expected to have high accuracy at a low cost.

The explanation will be given below according to the drawings. FIG. 1 shows a conventional electronic clock circuit block, in which 1 is a crystal oscillation circuit, 2 is a fixed counter for frequency division to extract the second signal, and 3 is a second,
A counter 4 is used to display minutes, hours, etc., and 4 is a display section that receives the output from 3 and displays the time. In FIG. 1, since all the counter groups are fixed, the precision of the display time is the precision of the crystal oscillation circuit itself, and the necessity of matching the precision of the crystal to the circuit can be understood from the figure.

FIG. 2 shows one example of the electronic timepiece according to the present invention using circuit blocks.

5 and 6 represent oscillation circuits.

7 and 8 are respective oscillation circuit output buffers.

Reference numerals 9 and 10 indicate that only one of the gate circuits for selecting the output of the oscillation circuit is in the selected state.

11 is a second signal output counter, 12 is a display counter, 1
3 represents a display section.

14 generates a signal for selecting the output of either 5 or 6 as an input signal of the counter 11 by an appropriate output signal or signal group set in advance from a series of counter groups 11 or 12. 14 is hereinafter referred to as a gate control circuit.

Assume that the counter groups in FIGS. 1 and 2 have a common frequency division ratio. Assuming that an error of ±0 can be displayed using the circuit diagram of FIG. 1, the oscillation frequency at this time will be referred to as the reference oscillation frequency t below. The oscillation frequency in FIG. 2 is expressed as +α, and the oscillation frequency in 6 is expressed as FO-β. When the gate 9 is kept ON all the time and the clock is operated only by the oscillation circuit 5, the clock advances only one second.

Conversely, when the gate 9 is set to 0FF1 and the gate 10 is set to ON and the clock is operated only by the oscillation circuit 6, the time will be delayed by one second.

These values represent errors in a conventional clock based on the circuit of FIG. On the other hand, in the present invention, the gate 9
, 10 are switched alternately to use both oscillation circuit outputs. Assuming that the 0N10FF ratio of gates 9 and 10 is 1:1, the average advance time of 1 second is as follows. If a clock is to be manufactured in which the frequency tolerance calculated from the daily or monthly difference standard is expressed as ±γ, the crystal oscillator shown in FIG. 1 is limited to a frequency satisfying the following formula.

In FIG. 2, the gate 0N. ．． When the 0FF time is set on a one-to-one basis, a watch that satisfies the above standard can be obtained by combining a pair of crystals with a combination of α and β that satisfies the inequality resulting from the above-mentioned results.

FIG. 3 shows an example of a vibration frequency distribution curve during mass production of crystal resonators.

The vertical axis 15 shows quantity, and the horizontal axis 16 shows frequency error. The center 0 is the frequency FO. Generally, the distribution is F as shown in Figure 3. It is safe to assume that it is symmetrical around the center and decreases as you move away from the center. 17 in Figure 3
The other crystal combination that satisfies the standard for the crystal with a positional error α shown in is distributed in the shaded area 18. Also, the other crystal that can be paired with the crystal α″ at position 19 is 2
It is distributed in the shaded area of 0. It is clear from FIG. 3 that according to the present invention, whereas conventionally all crystals with an error outside the tolerance range of ±γ were considered defective in the non-standard range, even crystals with an error of ±γ or more can achieve the same or higher accuracy. becomes possible.
However, through selection, all mass-produced crystals can be used as good quality. Alternatively, the adjustment process can be simplified in the vibrator manufacturing process. Furthermore, α that satisfies the same standard,
We will discuss how to expand the range of combinations of β.

The gate control circuit 14 in FIG. 2 may be a simple binary counter. This can be achieved with one stage of flip-flops, and the duty of the output pulse of the gate control circuit can be changed by the duty ratio of the input clock. That is, the switching ratio of both oscillation circuits can be arbitrarily changed using one stage of flip-flops. FIG. 4 shows the temperature characteristic curve.

21 is a temperature, 22 is a frequency error, and 23 and 24 are examples of oscillation frequency characteristics of two crystals.

According to the above explanation, in the operating temperature range, 23 and 2 are set so that the combined error satisfies the standard for the error of 23 and 24.
In addition to selecting the characteristics of M.4. (It is clear that by setting 5n, temperature countermeasures can be taken in the circuit according to the present invention.

Regarding the phase error at the time of gate switching, the switching period may be set sufficiently long with respect to the oscillation frequency so that the error component generated at the time of switching falls within the allowable error. Furthermore, these errors that occur during switching are statistically ±0, and it is considered that no accumulation of errors will occur over a long period of time.

[Brief explanation of the drawing]

Fig. 1 shows a conventional clock circuit block, Fig. 2 shows an example of a clock circuit block diagram according to the present invention, Fig. 3 shows a frequency distribution of a mass-produced resonator, and Fig. 4 shows a temperature characteristic curve of a crystal. It is.

Claims (1)

[Claims] 1. A first oscillation circuit having an error component with respect to a reference oscillation frequency, a second oscillation circuit having an error component with an opposite sign to the error component, and a first selection gate inputting the output of the first oscillation circuit. a second selection gate circuit that inputs the output of the second oscillation circuit, a frequency division counter that inputs both the signals from the first and second gate circuits, divides the frequency, and outputs a time signal; A gate control circuit including a binary counter that receives a signal from the frequency dividing counter and outputs a signal for alternately selecting the first and second gate circuits to the first and second gate circuits. An electronic clock characterized by: