JPS6140146B2 - - Google Patents
Info
- Publication number
- JPS6140146B2 JPS6140146B2 JP53102963A JP10296378A JPS6140146B2 JP S6140146 B2 JPS6140146 B2 JP S6140146B2 JP 53102963 A JP53102963 A JP 53102963A JP 10296378 A JP10296378 A JP 10296378A JP S6140146 B2 JPS6140146 B2 JP S6140146B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- window
- type
- buried oxide
- oxide pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
- H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
- H10D84/0116—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including integrated injection logic [I2L]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/65—Integrated injection logic
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
- Element Separation (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL7709363A NL7709363A (nl) | 1977-08-25 | 1977-08-25 | Werkwijze ter vervaardiging van een halfgeleider- inrichting en halfgeleiderinrichting vervaardigd onder toepassing van een dergelijke werkwijze. |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5446485A JPS5446485A (en) | 1979-04-12 |
JPS6140146B2 true JPS6140146B2 (en, 2012) | 1986-09-08 |
Family
ID=19829072
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10296378A Granted JPS5446485A (en) | 1977-08-25 | 1978-08-25 | Method of producing semiconductor |
Country Status (9)
Country | Link |
---|---|
US (1) | US4199378A (en, 2012) |
EP (1) | EP0001300B1 (en, 2012) |
JP (1) | JPS5446485A (en, 2012) |
AU (1) | AU517646B2 (en, 2012) |
CA (1) | CA1118532A (en, 2012) |
DE (1) | DE2861353D1 (en, 2012) |
ES (1) | ES472793A1 (en, 2012) |
IT (1) | IT1098127B (en, 2012) |
NL (1) | NL7709363A (en, 2012) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02121143U (en, 2012) * | 1989-03-15 | 1990-10-01 |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4269636A (en) * | 1978-12-29 | 1981-05-26 | Harris Corporation | Method of fabricating self-aligned bipolar transistor process and device utilizing etching and self-aligned masking |
JPS5852339B2 (ja) * | 1979-03-20 | 1983-11-22 | 富士通株式会社 | 半導体装置の製造方法 |
JPS5696852A (en) * | 1979-12-29 | 1981-08-05 | Fujitsu Ltd | Semiconductor device |
EP0044721A3 (en) | 1980-07-23 | 1982-05-12 | Jarl Sundseth | Air filters |
JPS57149770A (en) * | 1981-03-11 | 1982-09-16 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
JPS57194572A (en) * | 1981-05-27 | 1982-11-30 | Clarion Co Ltd | Semiconductor device and manufacture thereof |
US4961102A (en) * | 1982-01-04 | 1990-10-02 | Shideler Jay A | Junction programmable vertical transistor with high performance transistor |
US4624046A (en) * | 1982-01-04 | 1986-11-25 | Fairchild Camera & Instrument Corp. | Oxide isolation process for standard RAM/PROM and lateral PNP cell RAM |
CA1188418A (en) * | 1982-01-04 | 1985-06-04 | Jay A. Shideler | Oxide isolation process for standard ram/prom and lateral pnp cell ram |
US4444605A (en) * | 1982-08-27 | 1984-04-24 | Texas Instruments Incorporated | Planar field oxide for semiconductor devices |
US4507848A (en) * | 1982-11-22 | 1985-04-02 | Fairchild Camera & Instrument Corporation | Control of substrate injection in lateral bipolar transistors |
US4498227A (en) * | 1983-07-05 | 1985-02-12 | Fairchild Camera & Instrument Corporation | Wafer fabrication by implanting through protective layer |
US4860082A (en) * | 1984-07-08 | 1989-08-22 | Nec Corporation | Bipolar transistor |
JPS61220465A (ja) * | 1985-03-27 | 1986-09-30 | Toshiba Corp | 半導体装置 |
US4622738A (en) * | 1985-04-08 | 1986-11-18 | Advanced Micro Devices, Inc. | Method of making integrated bipolar semiconductor device by first forming junction isolation regions and recessed oxide isolation regions without birds beak |
US4700461A (en) * | 1986-09-29 | 1987-10-20 | Massachusetts Institute Of Technology | Process for making junction field-effect transistors |
GB2238658B (en) * | 1989-11-23 | 1993-02-17 | Stc Plc | Improvements in integrated circuits |
US5389553A (en) * | 1993-06-30 | 1995-02-14 | National Semiconductor Corporation | Methods for fabrication of transistors |
KR100384560B1 (ko) * | 1995-06-30 | 2003-08-06 | 주식회사 하이닉스반도체 | 반도체소자및그제조방법 |
KR0171000B1 (ko) * | 1995-12-15 | 1999-02-01 | 양승택 | 자동 정의된 베이스 전극을 갖는 바이폴라 트랜지스터 구조 및 그 제조방법 |
JP2001217317A (ja) | 2000-02-07 | 2001-08-10 | Sony Corp | 半導体装置およびその製造方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3748187A (en) * | 1971-08-03 | 1973-07-24 | Hughes Aircraft Co | Self-registered doped layer for preventing field inversion in mis circuits |
US3928091A (en) * | 1971-09-27 | 1975-12-23 | Hitachi Ltd | Method for manufacturing a semiconductor device utilizing selective oxidation |
US3992232A (en) * | 1973-08-06 | 1976-11-16 | Hitachi, Ltd. | Method of manufacturing semiconductor device having oxide isolation structure and guard ring |
GB1457139A (en) * | 1973-09-27 | 1976-12-01 | Hitachi Ltd | Method of manufacturing semiconductor device |
NL180466C (nl) * | 1974-03-15 | 1987-02-16 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een halfgeleiderlichaam voorzien van een in het halfgeleiderlichaam verzonken patroon van isolerend materiaal. |
DE2429957B2 (de) * | 1974-06-21 | 1980-08-28 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Verfahren zur Herstellung einer dotierten Zone eines bestimmten Leitungstyps in einem Halbleiterkörper |
JPS5329555B2 (en, 2012) * | 1974-11-22 | 1978-08-22 | ||
DE2605641C3 (de) * | 1976-02-12 | 1979-12-20 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Hochfrequenztransistor und Verfahren zu seiner Herstellung |
US4066473A (en) * | 1976-07-15 | 1978-01-03 | Fairchild Camera And Instrument Corporation | Method of fabricating high-gain transistors |
JPS5338984A (en) * | 1976-09-22 | 1978-04-10 | Hitachi Ltd | Manufacture of semiconductor device |
US4111720A (en) * | 1977-03-31 | 1978-09-05 | International Business Machines Corporation | Method for forming a non-epitaxial bipolar integrated circuit |
-
1977
- 1977-08-25 NL NL7709363A patent/NL7709363A/xx not_active Application Discontinuation
-
1978
- 1978-07-31 EP EP78200122A patent/EP0001300B1/en not_active Expired
- 1978-07-31 DE DE7878200122T patent/DE2861353D1/de not_active Expired
- 1978-08-15 CA CA000309394A patent/CA1118532A/en not_active Expired
- 1978-08-18 US US05/935,025 patent/US4199378A/en not_active Expired - Lifetime
- 1978-08-22 IT IT26940/78A patent/IT1098127B/it active
- 1978-08-23 ES ES472793A patent/ES472793A1/es not_active Expired
- 1978-08-23 AU AU39177/78A patent/AU517646B2/en not_active Expired
- 1978-08-25 JP JP10296378A patent/JPS5446485A/ja active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02121143U (en, 2012) * | 1989-03-15 | 1990-10-01 |
Also Published As
Publication number | Publication date |
---|---|
AU3917778A (en) | 1980-02-28 |
IT7826940A0 (it) | 1978-08-22 |
EP0001300A1 (en) | 1979-04-04 |
CA1118532A (en) | 1982-02-16 |
DE2861353D1 (en) | 1982-01-28 |
EP0001300B1 (en) | 1981-11-25 |
US4199378A (en) | 1980-04-22 |
ES472793A1 (es) | 1979-03-16 |
NL7709363A (nl) | 1979-02-27 |
JPS5446485A (en) | 1979-04-12 |
IT1098127B (it) | 1985-09-07 |
AU517646B2 (en) | 1981-08-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS6140146B2 (en, 2012) | ||
EP0052450B1 (en) | Method of manufacturing a semiconductor device with polycrystalline semiconductor cum metal electrodes | |
EP0094891B1 (en) | Method of fabricating a vertical power mosfet structure | |
US4445268A (en) | Method of manufacturing a semiconductor integrated circuit BI-MOS device | |
EP0422940B1 (en) | Method of forming a DMOS transistor | |
EP0034910B1 (en) | A method of manufacturing a semiconductor device, and a device so manufactured | |
EP0083816B1 (en) | Semiconductor device having an interconnection pattern | |
JPS622708B2 (en, 2012) | ||
EP0036319B1 (en) | Semiconductor device | |
KR0166052B1 (ko) | 고전압 병합 바이폴라/cmos 및 그 제조 방법 | |
US4323913A (en) | Integrated semiconductor circuit arrangement | |
US4473941A (en) | Method of fabricating zener diodes | |
JP2619340B2 (ja) | 半導体素子の高電圧トランジスタ構造及びその製造方法 | |
KR970011641B1 (ko) | 반도체 장치 및 제조방법 | |
EP0030147A1 (en) | Method for manufacturing a semiconductor integrated circuit | |
US4691436A (en) | Method for fabricating a bipolar semiconductor device by undercutting and local oxidation | |
EP0337823A2 (en) | MOS field effect transistor having high breakdown voltage | |
US4224631A (en) | Semiconductor voltage reference device | |
GB1593937A (en) | I2l integrated circuitry | |
EP0242893B1 (en) | Method of manufacturing a semiconductor device | |
JP2775765B2 (ja) | 半導体装置の製造法 | |
US4762804A (en) | Method of manufacturing a bipolar transistor having emitter series resistors | |
US4216038A (en) | Semiconductor device and manufacturing process thereof | |
US4469535A (en) | Method of fabricating semiconductor integrated circuit devices | |
EP0110773A2 (en) | Control of substrate injection in lateral bipolar transistors |