JPS5446485A - Method of producing semiconductor - Google Patents

Method of producing semiconductor

Info

Publication number
JPS5446485A
JPS5446485A JP10296378A JP10296378A JPS5446485A JP S5446485 A JPS5446485 A JP S5446485A JP 10296378 A JP10296378 A JP 10296378A JP 10296378 A JP10296378 A JP 10296378A JP S5446485 A JPS5446485 A JP S5446485A
Authority
JP
Japan
Prior art keywords
producing semiconductor
semiconductor
producing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10296378A
Other languages
English (en)
Other versions
JPS6140146B2 (ja
Inventor
Antoniusu Andoreasu F Yohanesu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of JPS5446485A publication Critical patent/JPS5446485A/ja
Publication of JPS6140146B2 publication Critical patent/JPS6140146B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H01L21/8226—Bipolar technology comprising merged transistor logic or integrated injection logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233—Integrated injection logic structures [I2L]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
JP10296378A 1977-08-25 1978-08-25 Method of producing semiconductor Granted JPS5446485A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7709363A NL7709363A (nl) 1977-08-25 1977-08-25 Werkwijze ter vervaardiging van een halfgeleider- inrichting en halfgeleiderinrichting vervaardigd onder toepassing van een dergelijke werkwijze.

Publications (2)

Publication Number Publication Date
JPS5446485A true JPS5446485A (en) 1979-04-12
JPS6140146B2 JPS6140146B2 (ja) 1986-09-08

Family

ID=19829072

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10296378A Granted JPS5446485A (en) 1977-08-25 1978-08-25 Method of producing semiconductor

Country Status (9)

Country Link
US (1) US4199378A (ja)
EP (1) EP0001300B1 (ja)
JP (1) JPS5446485A (ja)
AU (1) AU517646B2 (ja)
CA (1) CA1118532A (ja)
DE (1) DE2861353D1 (ja)
ES (1) ES472793A1 (ja)
IT (1) IT1098127B (ja)
NL (1) NL7709363A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5696852A (en) * 1979-12-29 1981-08-05 Fujitsu Ltd Semiconductor device
JPS6037775A (ja) * 1983-07-05 1985-02-27 フエアチアイルド　カメラ　アンド　インストルメント　コーポレーシヨン 集積回路構成体の製造方法
JPS61220465A (ja) * 1985-03-27 1986-09-30 Toshiba Corp 半導体装置

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4269636A (en) * 1978-12-29 1981-05-26 Harris Corporation Method of fabricating self-aligned bipolar transistor process and device utilizing etching and self-aligned masking
JPS5852339B2 (ja) * 1979-03-20 1983-11-22 富士通株式会社 半導体装置の製造方法
JPS57149770A (en) * 1981-03-11 1982-09-16 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS57194572A (en) * 1981-05-27 1982-11-30 Clarion Co Ltd Semiconductor device and manufacture thereof
CA1188418A (en) * 1982-01-04 1985-06-04 Jay A. Shideler Oxide isolation process for standard ram/prom and lateral pnp cell ram
US4961102A (en) * 1982-01-04 1990-10-02 Shideler Jay A Junction programmable vertical transistor with high performance transistor
US4624046A (en) * 1982-01-04 1986-11-25 Fairchild Camera & Instrument Corp. Oxide isolation process for standard RAM/PROM and lateral PNP cell RAM
US4444605A (en) * 1982-08-27 1984-04-24 Texas Instruments Incorporated Planar field oxide for semiconductor devices
US4507848A (en) * 1982-11-22 1985-04-02 Fairchild Camera & Instrument Corporation Control of substrate injection in lateral bipolar transistors
US4860082A (en) * 1984-07-08 1989-08-22 Nec Corporation Bipolar transistor
US4622738A (en) * 1985-04-08 1986-11-18 Advanced Micro Devices, Inc. Method of making integrated bipolar semiconductor device by first forming junction isolation regions and recessed oxide isolation regions without birds beak
US4700461A (en) * 1986-09-29 1987-10-20 Massachusetts Institute Of Technology Process for making junction field-effect transistors
JPH02121143U (ja) * 1989-03-15 1990-10-01
GB2238658B (en) * 1989-11-23 1993-02-17 Stc Plc Improvements in integrated circuits
US5389553A (en) * 1993-06-30 1995-02-14 National Semiconductor Corporation Methods for fabrication of transistors
KR100384560B1 (ko) * 1995-06-30 2003-08-06 주식회사 하이닉스반도체 반도체소자및그제조방법
KR0171000B1 (ko) * 1995-12-15 1999-02-01 양승택 자동 정의된 베이스 전극을 갖는 바이폴라 트랜지스터 구조 및 그 제조방법
JP2001217317A (ja) * 2000-02-07 2001-08-10 Sony Corp 半導体装置およびその製造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5338984A (en) * 1976-09-22 1978-04-10 Hitachi Ltd Manufacture of semiconductor device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3748187A (en) * 1971-08-03 1973-07-24 Hughes Aircraft Co Self-registered doped layer for preventing field inversion in mis circuits
US3928091A (en) * 1971-09-27 1975-12-23 Hitachi Ltd Method for manufacturing a semiconductor device utilizing selective oxidation
US3992232A (en) * 1973-08-06 1976-11-16 Hitachi, Ltd. Method of manufacturing semiconductor device having oxide isolation structure and guard ring
GB1457139A (en) * 1973-09-27 1976-12-01 Hitachi Ltd Method of manufacturing semiconductor device
NL180466C (nl) * 1974-03-15 1987-02-16 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een halfgeleiderlichaam voorzien van een in het halfgeleiderlichaam verzonken patroon van isolerend materiaal.
DE2429957B2 (de) * 1974-06-21 1980-08-28 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Herstellung einer dotierten Zone eines bestimmten Leitungstyps in einem Halbleiterkörper
JPS5329555B2 (ja) * 1974-11-22 1978-08-22
DE2605641C3 (de) * 1976-02-12 1979-12-20 Siemens Ag, 1000 Berlin Und 8000 Muenchen Hochfrequenztransistor und Verfahren zu seiner Herstellung
US4066473A (en) * 1976-07-15 1978-01-03 Fairchild Camera And Instrument Corporation Method of fabricating high-gain transistors
US4111720A (en) * 1977-03-31 1978-09-05 International Business Machines Corporation Method for forming a non-epitaxial bipolar integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5338984A (en) * 1976-09-22 1978-04-10 Hitachi Ltd Manufacture of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5696852A (en) * 1979-12-29 1981-08-05 Fujitsu Ltd Semiconductor device
JPS6152575B2 (ja) * 1979-12-29 1986-11-13 Fujitsu Ltd
JPS6037775A (ja) * 1983-07-05 1985-02-27 フエアチアイルド　カメラ　アンド　インストルメント　コーポレーシヨン 集積回路構成体の製造方法
JPS61220465A (ja) * 1985-03-27 1986-09-30 Toshiba Corp 半導体装置

Also Published As

Publication number Publication date
EP0001300A1 (en) 1979-04-04
NL7709363A (nl) 1979-02-27
JPS6140146B2 (ja) 1986-09-08
IT7826940A0 (it) 1978-08-22
IT1098127B (it) 1985-09-07
US4199378A (en) 1980-04-22
CA1118532A (en) 1982-02-16
ES472793A1 (es) 1979-03-16
AU3917778A (en) 1980-02-28
DE2861353D1 (en) 1982-01-28
AU517646B2 (en) 1981-08-13
EP0001300B1 (en) 1981-11-25

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