JPS6139949U - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JPS6139949U JPS6139949U JP1984124261U JP12426184U JPS6139949U JP S6139949 U JPS6139949 U JP S6139949U JP 1984124261 U JP1984124261 U JP 1984124261U JP 12426184 U JP12426184 U JP 12426184U JP S6139949 U JPS6139949 U JP S6139949U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- heat sink
- semiconductor equipment
- peripheral edge
- edge portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/183—Connection portion, e.g. seal
- H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
第1図は本考案の一実施例に係る放熱板の斜視図で、第
2図はそのB−B線にて切断した断面図、第3図は切欠
き部を有する放熱板の平面図、第4図と第5図は本考案
の一実施例に含まれる放熱板の凸部の形状を変形例を示
す側面図、第6図は樹脂封止型半導体装置の一例の平面
図で、第7図はその一面図、第8図は従来の放熱板の斜
視図で、第9図はそのA−A線にて切断した断面図であ
る。 2・・・・・・半導体素子、3・・・・・・リード部、
5・・・・・・樹脂材、7・・・・・・放熱板、7a・
・・・・・凸部、7b・・・・・・凹部。
2図はそのB−B線にて切断した断面図、第3図は切欠
き部を有する放熱板の平面図、第4図と第5図は本考案
の一実施例に含まれる放熱板の凸部の形状を変形例を示
す側面図、第6図は樹脂封止型半導体装置の一例の平面
図で、第7図はその一面図、第8図は従来の放熱板の斜
視図で、第9図はそのA−A線にて切断した断面図であ
る。 2・・・・・・半導体素子、3・・・・・・リード部、
5・・・・・・樹脂材、7・・・・・・放熱板、7a・
・・・・・凸部、7b・・・・・・凹部。
Claims (1)
- 放熱板に半導体素子を固定すると共に、リード部と半導
体素子の電極とを電気的に接続し、半導体素子を含む主
要部を樹脂材にて被覆したものにおいて、放熱板の半導
体素子固定部近傍に、凹部を形成するとともに、少なく
とも半導体素子に最も近い放熱板周縁部を折り返し、該
周縁部に凸部を形成したことを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984124261U JPS6139949U (ja) | 1984-08-13 | 1984-08-13 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984124261U JPS6139949U (ja) | 1984-08-13 | 1984-08-13 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6139949U true JPS6139949U (ja) | 1986-03-13 |
Family
ID=30682987
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1984124261U Pending JPS6139949U (ja) | 1984-08-13 | 1984-08-13 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6139949U (ja) |
-
1984
- 1984-08-13 JP JP1984124261U patent/JPS6139949U/ja active Pending
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