JPS6139740B2 - - Google Patents

Info

Publication number
JPS6139740B2
JPS6139740B2 JP56193519A JP19351981A JPS6139740B2 JP S6139740 B2 JPS6139740 B2 JP S6139740B2 JP 56193519 A JP56193519 A JP 56193519A JP 19351981 A JP19351981 A JP 19351981A JP S6139740 B2 JPS6139740 B2 JP S6139740B2
Authority
JP
Japan
Prior art keywords
substrate
semiconductor device
wiring area
package
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56193519A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5892248A (ja
Inventor
Takashi Kondo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56193519A priority Critical patent/JPS5892248A/ja
Publication of JPS5892248A publication Critical patent/JPS5892248A/ja
Publication of JPS6139740B2 publication Critical patent/JPS6139740B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
JP56193519A 1981-11-28 1981-11-28 大規模実装化半導体装置 Granted JPS5892248A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56193519A JPS5892248A (ja) 1981-11-28 1981-11-28 大規模実装化半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56193519A JPS5892248A (ja) 1981-11-28 1981-11-28 大規模実装化半導体装置

Publications (2)

Publication Number Publication Date
JPS5892248A JPS5892248A (ja) 1983-06-01
JPS6139740B2 true JPS6139740B2 (enrdf_load_stackoverflow) 1986-09-05

Family

ID=16309412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56193519A Granted JPS5892248A (ja) 1981-11-28 1981-11-28 大規模実装化半導体装置

Country Status (1)

Country Link
JP (1) JPS5892248A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62216250A (ja) * 1985-11-06 1987-09-22 Shinko Electric Ind Co Ltd プリント基板型ｐｇａパツケ−ジの製造方法

Also Published As

Publication number Publication date
JPS5892248A (ja) 1983-06-01

Similar Documents

Publication Publication Date Title
US6956294B2 (en) Apparatus for routing die interconnections using intermediate connection elements secured to the die face
JP3209320B2 (ja) マルチチップモジュールパッケージ
JP2819285B2 (ja) 積層型ボトムリード半導体パッケージ
US6326244B1 (en) Method of making a cavity ball grid array apparatus
US6331939B1 (en) Stackable ball grid array package
US4949224A (en) Structure for mounting a semiconductor device
US6531338B2 (en) Method of manufacturing a semiconductor structure having stacked semiconductor devices
JP4476482B2 (ja) ロープロファイルボールグリッドアレイ半導体パッケージ、集積回路、印刷回路板、プロセサシステム、ロープロファイルボールグリッドアレイ半導体パッケージを製造する方法、および、半導体ダイを搭載する方法
US6891257B2 (en) Packaging system for die-up connection of a die-down oriented integrated circuit
JP3304957B2 (ja) 多重チップ半導体モジュールとその製造方法
JPH0613436A (ja) キャリアのない集積回路パッケージ
JP2907127B2 (ja) マルチチップモジュール
JP3656861B2 (ja) 半導体集積回路装置及び半導体集積回路装置の製造方法
JPS6220707B2 (enrdf_load_stackoverflow)
JPH0563138A (ja) 半導体集積回路装置
JPH0823047A (ja) Ｂｇａ型半導体装置
JPS6139740B2 (enrdf_load_stackoverflow)
JP3150560B2 (ja) 半導体装置
US5434450A (en) PGA package type semiconductor device having leads to be supplied with power source potential
USRE43112E1 (en) Stackable ball grid array package
JP2822990B2 (ja) Ｃｓｐ型半導体装置
JPH04139737A (ja) 半導体チップの実装方法
JP2786047B2 (ja) 樹脂封止型半導体装置
KR100352115B1 (ko) 반도체패키지
JPH03236245A (ja) 半導体装置