JPS6136942A - Apparatus for electronic part - Google Patents

Apparatus for electronic part

Info

Publication number
JPS6136942A
JPS6136942A JP15815384A JP15815384A JPS6136942A JP S6136942 A JPS6136942 A JP S6136942A JP 15815384 A JP15815384 A JP 15815384A JP 15815384 A JP15815384 A JP 15815384A JP S6136942 A JPS6136942 A JP S6136942A
Authority
JP
Japan
Prior art keywords
conductive
electronic component
electrodes
chip
adhesive body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15815384A
Other languages
Japanese (ja)
Inventor
Yuichi Matsubara
松原 裕一
Takashi Ando
尚 安藤
Masashi Okunaga
奥長 正志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP15815384A priority Critical patent/JPS6136942A/en
Publication of JPS6136942A publication Critical patent/JPS6136942A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To conduct electrical and mechanical joining between a chip-shaped electronic part and a conductive pattern on a film carrier collectively and simply by joining the conductive pattern, the electronic part and a protective plate by a conductive anisotropic adhesive body. CONSTITUTION:A chip part 10 is loaded onto a cradle 30 functioning as a hot plate in combination. A conductive anisotropic adhesive body 28 is positioned onto the part 10, and conductive patterns 22-24 for a film 19a are positioned so as to be brought onto electrodes 13-15 for the part 10. An insulating protective plte 29 is positioned onto the conductive patterns 22-24, and the part 10, the conductive patterns 22-24 and the protective plate 29 are joined by the conductive anisotropic adhesive body 28 by a contact-bonding jig 31 conducting an ultrasonic vibration and the cradle 30. Consequently, the electrodes 13-15 and the conductive patterns 22-24 are joined electrically by solder grains 28a in the adhesive body 28. Since the adhesive body 28 has insulating properties in the surface direction, the electrodes are not short-circuited. Accordingly, the electrical and mechanical joining of the part 10 and the conductive patterns 22-24 is conducted collectively and simply.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、電子部品例えばICチップ部品の電極と所定
の導電・やターンとを電気的に接続してなる電子部品装
置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an electronic component device in which an electrode of an electronic component, such as an IC chip component, and a predetermined conductive turn are electrically connected.

背景技術とその問題点 従来、ICチップ部品の電極とリード線の役割をなす所
定の導電パターンとを電気的に接続してなる電子部品装
置においては、例えば金線ワイヤーによるいわゆるワイ
ヤーポンディングにより第1図のように導電パターンと
電子部品の電極との電気的接続をなしていた〇 第1図において、(1)及び(2)は銅箔により形成さ
れ、所望の電気的接続をなすのに適するリード線の役割
をなす導電パターンを示し、この導電パターン(1)及
び(2)は基材(3)及び(4)上に所定・やターンに
て形成されている。また、(5)はICチップ部品を示
し、このICチップ部品(5)には所定位置に電極(6
)及び(7)が配され、金線ワイヤー(8)及び(9)
にて導電・ぐターン(1)及び(2)と電極(6)及び
(7)とが電気的に接続され、ICチップ部品(5)に
係る所定の配線がなされることになる。
BACKGROUND TECHNOLOGY AND PROBLEMS Conventionally, in electronic component devices in which electrodes of IC chip components are electrically connected to predetermined conductive patterns that serve as lead wires, electrical connections are made using so-called wire bonding using, for example, gold wire. As shown in Figure 1, electrical connection was made between the conductive pattern and the electrode of the electronic component. In Figure 1, (1) and (2) are formed of copper foil, and it is necessary to make the desired electrical connection. A conductive pattern serving as a suitable lead wire is shown, and the conductive patterns (1) and (2) are formed on the substrates (3) and (4) in a predetermined turn. Further, (5) indicates an IC chip component, and this IC chip component (5) has an electrode (6) at a predetermined position.
) and (7) are arranged, gold wire (8) and (9)
The conductive grooves (1) and (2) are electrically connected to the electrodes (6) and (7), and predetermined wiring for the IC chip component (5) is completed.

ところで、金線ワイヤー(8)及び(9)の半田付けに
よる電気接続に直接係る電極(6)及び(7)の正方形
端面は所定の広さの程度が必要で100μmX100μ
m程度の広さであれば十分にワイヤーポンディングで対
応できる。
By the way, the square end faces of the electrodes (6) and (7) that are directly connected to the electrical connection by soldering the gold wires (8) and (9) need to have a predetermined width of 100 μm x 100 μm.
Wire bonding can be used for areas as large as 1.5 m.

しかし、ICチップ部品(5)の小型化に伴ない例えば
電極(6)の端面広さが40μm×40μm程度まで小
さくした場合、ワイヤー鱈?ンデイングでは電極相互の
短絡の可能性も大きくなり良好に電気的接続ができない
不都合があった。また、金線ワイヤーを用いるワイヤー
がンディングによった場合には、金線ワイヤー自体高価
なため電子部品装置の製造費が嵩んだ。また、ワイヤー
デンディングによる接着速度は金線ワイヤー一本の半田
付けにつき0.2秒を要するので電極数の多いものKつ
きワイヤーメンディングを使用すると製造時間が多くか
かシ、電子部品装置の生産性が悪くなる欠点もあった。
However, with the miniaturization of IC chip components (5), if the end face width of the electrode (6) is reduced to about 40 μm x 40 μm, for example, will it become a wire cod? In the case of bonding, the possibility of short circuiting between the electrodes becomes large, and a good electrical connection cannot be achieved, which is disadvantageous. Further, when the wire using gold wire is bonded, the manufacturing cost of the electronic component device increases because the gold wire itself is expensive. In addition, the bonding speed with wire ending requires 0.2 seconds for soldering one gold wire, so if wire ending with K is used for items with a large number of electrodes, it will take a lot of manufacturing time. It also had the disadvantage of decreasing productivity.

また、第2図は熱超音波圧接法(TAB法)により所望
の電気的接続を行なって得る電子部品装置の従来例を示
す。この第2図において第1図との対応部分には同一符
号を付しそれらの詳細な説明は省略する。
Further, FIG. 2 shows a conventional example of an electronic component device obtained by making desired electrical connections by thermo-ultrasonic pressure bonding (TAB method). In FIG. 2, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

この従来例では、半田若しくは金などのバンプ(8)及
び(9)をICチップ部品(5)の電極(6) (7)
に導電・♀ターン(3) 、 (4)に対応させて形成
した上で電極(6)及び(7)を導電ノ母ターン(3)
及び(4)をバンプ(8)及び(9)を介在させて圧着
し、所定の導通をとると共にICチップ部品(5)を機
械的に固定して電子部品装置を得ている。また第3図は
、バンプ01及び0])を導電ノぐターン(3)及び(
4)側に形成してTAB法にょシミ子部品装置を得る他
の例を示す。
In this conventional example, bumps (8) and (9) made of solder or gold are connected to electrodes (6) (7) of an IC chip component (5).
Conductive turns (3) and (4) are formed to correspond to the conductive turns (3) and (4), and then the electrodes (6) and (7) are connected to the conductive mother turns (3).
and (4) are crimped with bumps (8) and (9) interposed therebetween to establish a predetermined conductivity and mechanically fix the IC chip component (5) to obtain an electronic component device. Figure 3 also shows bumps 01 and 0]) conductive through turns (3) and (
4) Another example of obtaining a shimiko component device by TAB method will be shown.

このTAB法により電子部品装置を得るにはワイヤーが
不要となる分だけ安価になるが、バンプo1及び(11
)を形成するための費用がかがる。また、導電ノ(ター
ン相互、あるいは電極相互の間隔が狭くなると、バンプ
αQ及び0])をなしている半田等の流出により、隣接
電極、隣接導電パターンを短絡させる可能性が高くなシ
、電子部品装置の小型化に適さない不都合があった。ま
た、ICチップ部品(5)の電極(6)及び(7)にバ
ンプを形成する工程自体、バンプ00及びθカの高さの
精度を高精度とすることが難しいことからも電子部品装
置の電気的接続の信頼性の低い欠点があった。
To obtain an electronic component device using this TAB method, the cost is reduced as no wire is required, but bumps o1 and (11
) is expensive to form. In addition, there is a high possibility that adjacent electrodes or conductive patterns may be short-circuited due to leakage of solder forming conductive lines (bumps αQ and 0 when the distance between turns or between electrodes becomes narrower). This has the disadvantage that it is not suitable for miniaturization of component devices. In addition, in the process of forming bumps on the electrodes (6) and (7) of the IC chip component (5), it is difficult to make the heights of the bumps 00 and θ with high accuracy, so it is difficult to The disadvantage was that the electrical connection was unreliable.

発明の目的 本発明は上述の点に鑑みてなされたもので、煩わしい工
程がなく、簡単に電子部品の電極について必要な電気的
接続及び電子部品の機械的結合が一括して良好にできる
電子部品装置を提供することを目的とする。
Purpose of the Invention The present invention has been made in view of the above-mentioned points, and provides an electronic component in which the necessary electrical connection of the electrodes of the electronic component and the mechanical connection of the electronic component can be easily achieved all at once without any troublesome steps. The purpose is to provide equipment.

発明の概要 本発明電子部品装置は、フィルムキャリアにチップ状電
子部品を載置してなる電子部品装置において、フィルム
キャリア上の導電パターンとチップ状電子部品上の電極
とが導電異方性接着体により電気的・機械的に接合され
るとともに、導電パターンの電子部品の反対側に保護板
が接合されてなるものである。かかる本発明によれば煩
わしい工程なく簡単に電子部品のパッド部との必要な電
気的接続及び電子部品の機械的接合が一括して良好に行
なえるものである。
Summary of the Invention The electronic component device of the present invention is an electronic component device in which a chip-shaped electronic component is mounted on a film carrier, in which a conductive pattern on the film carrier and an electrode on the chip-shaped electronic component are formed of a conductive anisotropic adhesive. In addition to electrically and mechanically bonding, a protective plate is bonded to the opposite side of the conductive pattern to the electronic component. According to the present invention, the necessary electrical connection with the pad portion of the electronic component and the mechanical bonding of the electronic component can be easily and satisfactorily performed at once without any troublesome steps.

実施例 υ下館4図乃至第6図を参照して本発明電子部品装置の
一実施例について説明しよう。
Embodiment υ An embodiment of the electronic component device of the present invention will be described with reference to FIGS. 4 to 6 Shimodate.

第4図において、00はICチップ部品を示し、このI
Cチップ部品θ1には100μm X 100μmの正
方形端面となされた外部アルミ電極α1)02θ304
α→αQ0η0樟が設けられている。またa場はフィル
ムキャリアを全体として示し、このフィルムキャリアは
例えばポリイミドよりなる厚さ130μmのフィルム(
19a)に、所定のリード線のノリ―ンをなす、厚さ1
8μm1幅70μmの銅にすずめつきを施した導N”タ
ーン(ホ)(ハ)(イ)(21(ハ)(ハ)(ハ)に)
が配されている。ここで、パターン先端付近の幅は電極
(11)〜0杼の端面の面積が小さくなっても電極01
)〜0&の大きさに対応してパターン幅を所定区間だけ
例えば幅狭となしいかなる小面積の電極にも対応できる
ものである。また、この導電パターン翰〜(イ)と電極
(l])〜0綽との間には導電異方性接着体(ハ)を介
在させて対応する導電パターンと電極との電気的接続を
なしている。
In FIG. 4, 00 indicates an IC chip component, and this I
The C chip component θ1 has an external aluminum electrode α1)02θ304 with a square end face of 100 μm x 100 μm.
α → αQ0η0 camphor is provided. In addition, field a indicates the film carrier as a whole, and this film carrier is, for example, a 130 μm thick film made of polyimide (
19a) with a thickness of 1 which forms the predetermined line of the lead wire.
Conductive N” turn (E) (C) (A) (21 (C) (C) (C)) made of tinned copper with a width of 8μm and a width of 70μm.
are arranged. Here, even if the area of the end face of electrode (11) to 0 is small, the width near the tip of the pattern is
) to 0&, the pattern width is narrowed in a predetermined section, for example, so that it can be applied to electrodes of any small area. In addition, a conductive anisotropic adhesive (c) is interposed between the conductive pattern (1) and the electrode (1) to establish electrical connection between the corresponding conductive pattern and the electrode. ing.

この導電異方性接着体(ハ)は、介在させる面の垂直方
向には導電性をもたせ対応する電極0】)〜0綺と導電
パターン(ホ)〜に)の端部との電気的接続をなすよう
にすると共に、介在させる面の面方向には絶縁性をもた
せ短絡してはならない隣接した導電パターン相互あるい
は隣接した電極相互の短絡を防止する導電異方性をもた
せたものである。
This electrically conductive anisotropic adhesive (c) has electrical conductivity in the direction perpendicular to the intervening surface and electrically connects the corresponding electrode 0]) to the end of the conductive pattern (e) to In addition, the intervening surface has insulating properties in the plane direction and conductive anisotropy to prevent short-circuits between adjacent conductive patterns or between adjacent electrodes.

この導電異方性接着体(ハ)の形成につき第6図を参照
して詳述する。
The formation of this conductive anisotropic adhesive body (c) will be described in detail with reference to FIG. 6.

導電異方性接着体(28)の形成には、先ず、次なる組
成の絶縁性樹脂液を用意する。
To form the conductive anisotropic adhesive body (28), first, an insulating resin liquid having the following composition is prepared.

この組成の絶縁性の樹脂液にこの液の固形分100容量
部に対し10容量部の低融点半田金属粒−R28a)を
分散させる。この金属粒子(28a)はPb−8Ω合金
KSbとBiを添加し、融点140℃とされた平均粒径
20μmの半田金属粒子を用いる。このように絶縁性樹
脂液に低融点半田金属粒子(28a)が分散された接着
剤塗料を乾燥後の厚さが40μmとなるように例えば図
示せずも剥離シート上にコーターによって塗布して導電
異方性接着体−を得る。
In an insulating resin liquid having this composition, 10 parts by volume of low melting point solder metal particles -R28a) are dispersed per 100 parts by volume of the solid content of this liquid. The metal particles (28a) are solder metal particles having an average particle size of 20 μm and having a melting point of 140° C., to which Pb-8Ω alloy KSb and Bi are added. An adhesive paint in which low melting point solder metal particles (28a) are dispersed in an insulating resin liquid is applied to a release sheet (not shown) using a coater, for example, so that the thickness after drying is 40 μm to make it conductive. An anisotropic adhesive body is obtained.

また、翰は例えばガラスよりなる保護板を示し、この保
護板は導電パターン(ハ)(財)及び翰の上下面のうち
電子部品の接続されない側に厚さ0.35mで形成する
。この例ではこのガラス板(ハ)の大きさをチップ状電
子部品の大きさに対応させて100μmX100μmの
正方形状とする。
Further, the fence represents a protective plate made of glass, for example, and this protective plate is formed with a thickness of 0.35 m on the side of the conductive pattern (C) and the upper and lower surfaces of the fence where electronic components are not connected. In this example, the size of the glass plate (c) is made into a square shape of 100 μm×100 μm, corresponding to the size of the chip-shaped electronic component.

次に本発明電子部品装置の一実施例の製造方法について
説明しよう。
Next, a method of manufacturing an embodiment of the electronic component device of the present invention will be explained.

第5図のように1先ずヒータ付きの熱板を兼ねる受台(
1)を用意する。この受台(イ)上にICチップ部品α
1を電極α1)〜0棒を上向きにして積載する。そして
、導電異方性接着体をその上にfftt!、フィルム(
19m)の所定の導電パターン(至)〜(イ)を電気的
に接続しようとするICチップ部品の電極αη〜08の
上忙くるように位置決めする。
As shown in Figure 5, 1. First of all, the cradle (
Prepare 1). Place the IC chip component α on this pedestal (A).
1 is loaded with the electrodes α1) to 0 facing upward. Then, place the conductive anisotropic adhesive on top of it! ,film(
The predetermined conductive patterns (19m) to (19m) are positioned so that they are directly above the electrodes αη to 08 of the IC chip component to be electrically connected.

また翰は導電・母ターンの電子部品α1の反対側から接
合した絶縁劇料からなる保護板を示し、この保護板−は
例えばガラスによりICチップ部品(10の大きさに対
応して100μmX100μmの正方形状に形成する。
In addition, the wire indicates a protective plate made of an insulating material bonded from the opposite side of the conductive/mother-turn electronic component α1, and this protective plate is made of, for example, a glass IC chip component (100 μm x 100 μm square corresponding to the size of 10). form into a shape.

このガラス板(ハ)の上から例えば2000 Hzの超
音波振動を与える超音波振動発生器ともなる圧着治具0
1)によシ圧着する。
A crimping jig 0 that also serves as an ultrasonic vibration generator that applies ultrasonic vibrations of, for example, 2000 Hz from above this glass plate (c)
1) Crimp firmly.

ここで、これらの電子部品装置の製造装置により加熱加
圧する条件としては例えば受台(ト)の温度を200〜
300℃とし、治具01)による圧力を0.1ψ鼠超音
波撮動数2000Hz、加熱圧着時間0.1〜20秒と
して行なうことができる。
Here, as the conditions for heating and pressurizing with the manufacturing equipment of these electronic component devices, for example, the temperature of the pedestal (G) is 200 to 200℃.
The temperature can be set at 300° C., the pressure using the jig 01) is 0.1 ψ, the frequency of ultrasonic imaging is 2000 Hz, and the heat and pressure bonding time is 0.1 to 20 seconds.

このような条件下で加熱圧着すると導電異方性接着体(
ハ)中の絶縁性接着剤が加熱によって流動性を呈し、導
電パターンとこれに対応する電極との間に介在する絶縁
性接着剤の多くが側方に押し出され、これらの導電パタ
ーンと電極との間において半田粒子(28a)がその加
熱加圧によって溶融圧潰され、対応する導電パターンと
電極間が半田づけされて両者が電気的接続され良好な導
通抵抗が得られた。また、電気的接続をなす導電パター
ンと電極との間から押し出された絶縁性接着剤が導電性
を有する金属粒子を良好に包み込み且つ隣り合う導電パ
ターン相互間、隣り合う電極相互間に多量に存在するた
め絶縁性が保たれると共に両者は強固に固着された。
When heated and pressed under these conditions, a conductive anisotropic adhesive (
c) The insulating adhesive inside becomes fluid due to heating, and much of the insulating adhesive interposed between the conductive patterns and the corresponding electrodes is pushed out to the side, causing the conductive patterns and electrodes to become fluid. The solder particles (28a) were melted and crushed by the heating and pressurization between them, and the corresponding conductive pattern and the electrode were soldered to electrically connect them and obtain good conduction resistance. In addition, the insulating adhesive extruded from between the conductive pattern and the electrode that makes the electrical connection wraps the conductive metal particles well, and is present in large quantities between the adjacent conductive patterns and between the adjacent electrodes. As a result, insulation was maintained and the two were firmly attached.

このような導電異方性接着体−の加熱圧着時流動現象が
効果的に生じ、導通抵抗を0.1Ωυ下、絶縁抵抗を1
07Ω以上、好壕しくは109ΩとするKは、絶縁性接
着剤の加熱接合時のM、F、1. (メルト・フロー・
インデックス)は、0.001以上好ましくは0.00
5v上とする。このM、F、1.は、ASTM。
Such a flow phenomenon occurs effectively during heat and pressure bonding of the conductive anisotropic adhesive, and the conduction resistance is reduced to 0.1Ωυ or less, and the insulation resistance is reduced to 1.
K should be 07Ω or more, preferably 109Ω, and M, F, 1. (melt flow
index) is 0.001 or more preferably 0.00
5v higher. This M, F, 1. is ASTM.

DI 238のA法またはJIS 、に7210のA法
に規定された装置で、所定の圧着温度において2160
.litの荷重を印加したときにオリフィスから10分
間に流出する樹脂のグラム数を示すものである。また、
導電異方性接着体(ハ)の厚さは、各接続部間に生じる
空間体積の10〜300%好ましくは30〜200%と
し、その厚さは5〜200μmとすることが望ましい。
2160 at a predetermined compression temperature using equipment specified in DI 238 method A or JIS 7210 method A.
.. It shows the number of grams of resin that flows out from the orifice in 10 minutes when a load of 1.1 lit is applied. Also,
The thickness of the electrically conductive anisotropic adhesive (c) is 10 to 300%, preferably 30 to 200%, of the volume of the space created between each connection part, and the thickness is preferably 5 to 200 μm.

以上述べたように、本実施例によれば、フィルムキャリ
ア(至)の導電パターン(イ)〜(ロ)に対応させてI
Cチップ部品α1の電極C11)〜(18の存する面の
すべてが導電異方性接着体により電気的・機械的に一括
して接合されるので、煩わしい工程なく簡単に信頼性の
高い小型化に適した電子部品装置を得ることができる。
As described above, according to this embodiment, I
All surfaces of the C-chip component α1 containing electrodes C11) to (18) are electrically and mechanically bonded together using a conductive anisotropic adhesive, making it easy to achieve highly reliable miniaturization without any troublesome processes. A suitable electronic component device can be obtained.

また、ガラス板四により導電異方性接着体による接続部
の保護ができると共に接着強度を増加させることができ
る利益がある。また、ガラス板翰及びrcチップ部品(
10に受台(7)及び治具01)が当接しつつ加熱圧着
することになるので連続して接着しても圧着装置に接着
剤が付着することがなく大量生産に適する利益がある。
Further, the glass plate 4 has the advantage that the connection portion can be protected by the conductive anisotropic adhesive and the adhesive strength can be increased. In addition, we also offer glass plate ducts and RC chip parts (
Since the pedestal (7) and the jig 01) are in contact with the pedestal 10 during the heat and pressure bonding, the adhesive does not adhere to the pressure bonding device even when bonding is performed continuously, which is advantageous for mass production.

また、保護板の材料の選定により放熱性耐湿性の改善を
図ることも可能である。また、超音波振動を加えずに加
熱圧着のみで電子部品装置を得ることを可とする。
It is also possible to improve heat dissipation and moisture resistance by selecting the material of the protective plate. Furthermore, it is possible to obtain an electronic component device only by heat compression bonding without applying ultrasonic vibration.

なお、本発明は上述実施例に限らず本発明の要旨を逸脱
することなくその他種々の構成が取り得ることは勿論で
ある。
Note that the present invention is not limited to the above-described embodiments, and it goes without saying that various other configurations may be adopted without departing from the gist of the present invention.

発明の効果 本発明電子部品装置は、フィルムキャリアにチップ状電
子部品を載置してなる電子部品装置において、フィルム
キャリア上の導電パターンとチップ状電子部品の電極と
が導電異方性接着体により、電気的機械的に接合される
と共に導電パターンの前記電子部品の反対側圧保護板が
接合されてなるもので、導電異方性接着体により一括し
て接合できるので煩わしい工程なく簡単に信頼性高く小
型化に適した電子部品装置を得ることができる利益があ
る。また、保護板により接着強度を増加でき接合部を保
護できる利益もある。また、連続して接着しても加熱圧
着時に接着剤が付着することがなく大量生産に適する利
益もある。
Effects of the Invention The electronic component device of the present invention is an electronic component device in which a chip-shaped electronic component is mounted on a film carrier, in which the conductive pattern on the film carrier and the electrode of the chip-shaped electronic component are formed by a conductive anisotropic adhesive. , which is electrically and mechanically bonded and a pressure protection plate on the opposite side of the electronic component of the conductive pattern is bonded.Since it can be bonded all at once using a conductive anisotropic adhesive, it is easy and highly reliable without any troublesome processes. There is an advantage that an electronic component device suitable for miniaturization can be obtained. Further, the protective plate has the advantage of increasing adhesive strength and protecting the joint. Further, even if the adhesive is bonded continuously, the adhesive will not adhere during heat-pressing, making it suitable for mass production.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図及び第3図はそれぞれ従来の電子部品装
置の例を示す線図、第4図及び第5図は本発明電子部品
装置の一実施例を示す線図、第6図は第4図に示す例の
要部の例を示す線図である。 01はrcチップ部品、◇1)〜01lIlはそれぞれ
電極、0呻はフィルムキャリア、(19m)はフィルム
、−〜(財)はそれぞれ導電パターン、(ハ)はガラス
板である。 ・“[・1y −’)n’t
1, 2 and 3 are diagrams showing an example of a conventional electronic component device, FIGS. 4 and 5 are diagrams showing an example of an electronic component device of the present invention, and FIG. 6 is a diagram showing an example of a conventional electronic component device, respectively. FIG. 5 is a diagram showing an example of a main part of the example shown in FIG. 4; 01 is an rc chip component, ◇1) to 01lIl are electrodes, 0 is a film carrier, (19m) is a film, - to (goods) are conductive patterns, and (c) is a glass plate.・“[・1y −')n't

Claims (1)

【特許請求の範囲】[Claims]  フィルムキャリアにチップ状電子部品を載置してなる
電子部品装置において、前記フィルムキャリア上の導電
パターンと前記チップ状電子部品の電極とが導電異方性
接着体により電気的・機械的に接合されると共に、該導
電パターンの前記電子部品の反対側に保護板が接合され
てなるようにしたことを特徴とする電子部品装置。
In an electronic component device in which a chip-shaped electronic component is mounted on a film carrier, the conductive pattern on the film carrier and the electrode of the chip-shaped electronic component are electrically and mechanically bonded by a conductive anisotropic adhesive. An electronic component device characterized in that a protective plate is bonded to a side of the conductive pattern opposite to the electronic component.
JP15815384A 1984-07-28 1984-07-28 Apparatus for electronic part Pending JPS6136942A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15815384A JPS6136942A (en) 1984-07-28 1984-07-28 Apparatus for electronic part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15815384A JPS6136942A (en) 1984-07-28 1984-07-28 Apparatus for electronic part

Publications (1)

Publication Number Publication Date
JPS6136942A true JPS6136942A (en) 1986-02-21

Family

ID=15665419

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15815384A Pending JPS6136942A (en) 1984-07-28 1984-07-28 Apparatus for electronic part

Country Status (1)

Country Link
JP (1) JPS6136942A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0229256A (en) * 1988-05-26 1990-01-31 Boehringer Mannheim Gmbh Freezing dry of biological and chemical substance

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0229256A (en) * 1988-05-26 1990-01-31 Boehringer Mannheim Gmbh Freezing dry of biological and chemical substance
JPH0450830B2 (en) * 1988-05-26 1992-08-17 Boehringer Mannheim Gmbh

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