JPS61174643A - Method of connection for wiring substrate - Google Patents

Method of connection for wiring substrate

Info

Publication number
JPS61174643A
JPS61174643A JP1400785A JP1400785A JPS61174643A JP S61174643 A JPS61174643 A JP S61174643A JP 1400785 A JP1400785 A JP 1400785A JP 1400785 A JP1400785 A JP 1400785A JP S61174643 A JPS61174643 A JP S61174643A
Authority
JP
Japan
Prior art keywords
conductive
metal particles
bonding pads
integrated circuit
circuit chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1400785A
Other languages
Japanese (ja)
Inventor
Tsuneo Hanada
花田 常雄
Tomozo Miyazaki
宮崎 智三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dexerials Corp
Original Assignee
Sony Chemicals Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Chemicals Corp filed Critical Sony Chemicals Corp
Priority to JP1400785A priority Critical patent/JPS61174643A/en
Publication of JPS61174643A publication Critical patent/JPS61174643A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To extremely lessen the conductive resistance of a wiring substrate and to enable to perform a highly reliable connection of the wiring substrate with a semiconductor integrated circuit chip by a method wherein a bonding agent layer obtainable by dispersing low-melting point metal particles in an insulative bonding agent is provided between the conductive patterns and the conductive materials to corespond to the conductive patterns, both of the conductive patterns and the conductive materials are pressed and heated and are electrically connected, and after that, both of the conductive patterns and the conductive materials are cooled to the prescribed temperature in a state being pressed. CONSTITUTION:A release sheet is peeled off from a coupling sheet and a bonding agent layer 5 using the release sheet as its supporting material is placed on parts of the surfaces of conductive leads 4, 4... on a substrate, where the conductive leads 4, 4... should be at least connected with the bonding pads 2, 2... of a semiconductor integrated circuit chip 1, in such a way as to be continuously placed on the parts as one layer. Then, the integrated circuit chip 1 is placed on the bonding agent layer 5 in such a way that the bonding pads 2, 2... are superposed on the parts, where the bonding pads 2, 2... should be mutually connected with the conductive leads 4, 4... to correspond to the bonding pads 2, 2..., through the bonding agent layer 5, and both of the bonding pads 2, 2... and the conductive leads 4, 4... are heated and pressed. Accordingly, solder metal particles 7 are fused and crushed and both of the bonding pads 2, 2... and the conductive leads 4, 4... are soldered and are electrically connected. After that, both of the bonding pads and the conductive leads are cooled in a state that the pressing to both thereof is continued intact.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、例えば半導体集積回路チップをフィルムキャ
リアテープ等の配線基板に接続するのに使用して好適な
配線基板の接続方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring board connection method suitable for use, for example, in connecting a semiconductor integrated circuit chip to a wiring board such as a film carrier tape.

〔従来の技術〕[Conventional technology]

一般に半導体集積回路チップ(1)は第4図に示す如く
例えば−辺が51の正方形と比較的小さく、この5mの
一辺に例えば30個の100μmX100μ簿のがンデ
イング/JFツド(2)が設けられている。従来斯る半
導体集積回路チップ(1)の電極であるボンディングパ
ッド(2)と、例えばフィルムキャリアテープの外部リ
ード(4)との接続はワイヤーンデイング法により行わ
れていた。このワイヤーンデイング法はAu線またaA
I線等の極めて細いワイヤによって半導体集積回路チッ
プ(1)のがンデイングI#ツドと外部リードとの接続
を行う方法であるが、このがンデイング作業に熟練を要
し、作業性も悪くまたIンデインダミスを起こしやす(
歩留りが悪い等の欠点があった。
In general, a semiconductor integrated circuit chip (1) is relatively small, for example, a square with 51 sides as shown in FIG. ing. Conventionally, bonding pads (2), which are electrodes of such a semiconductor integrated circuit chip (1), and, for example, external leads (4) of a film carrier tape have been connected by a wire ending method. This wiring method uses Au wire or aA wire.
This is a method of connecting the mounting I# of the semiconductor integrated circuit chip (1) with the external leads using extremely thin wires such as I wires, but this mounting requires skill and is not easy to work with. prone to hindrance (
There were drawbacks such as poor yield.

そこで先に本願出願人は、特願昭58−250786号
に示す如く絶縁性接着剤に低融点金属粒子が分散された
接着剤を使用して接続する方法を提案した。
Therefore, the applicant of the present application previously proposed a connection method using an adhesive in which low-melting point metal particles are dispersed in an insulating adhesive, as shown in Japanese Patent Application No. 58-250786.

この半導体集積回路チップ(1)をフィルムキャリアテ
ープ上に配する場合につき説明するに、このフィルムキ
ャリアテープは第1図、第5図に示す如くポリイミドよ
り成るフレキシブル基板(3)上に被着された厚さ18
μmのCu箔が選択的にエツチングされノターン化され
て半導体集積回路チップ(1)ノ複数のビンディングパ
ッド(2) 、 (21・・・・・・K対応して電気的
に接続される複数の導電性リード(41、(41・・・
・・・が形成されたものである。
To explain the case where this semiconductor integrated circuit chip (1) is placed on a film carrier tape, this film carrier tape is adhered to a flexible substrate (3) made of polyimide as shown in FIGS. 1 and 5. thickness 18
A Cu foil with a thickness of μm is selectively etched and notarized to form a plurality of binding pads (2), (21...K) on a semiconductor integrated circuit chip (1), which are electrically connected in correspondence with each other. Conductive lead (41, (41...
... was formed.

この半導体集積回路チップ(1)をフィルムキャリアテ
ープ上に接続固定するのに剥離シート上に接着剤層(5
)を塗布した連結シートを用意する。
To connect and fix this semiconductor integrated circuit chip (1) on the film carrier tape, an adhesive layer (5
) Prepare a connecting sheet coated with

この連結シートの接着剤層(5)は、ホットメルトタイ
プの絶縁性接着剤(6)に、半田金属粒子(7)を分散
した塗料を用いた。絶縁性接着剤(6)は次の組成とし
た。
The adhesive layer (5) of this connection sheet used a paint in which solder metal particles (7) were dispersed in a hot melt type insulating adhesive (6). The insulating adhesive (6) had the following composition.

この組成の絶縁性接着剤K、これの固形分100容量部
に対し、10容量部の低融点半田金属粒子(7)を分散
させた。この金属粒子は、Pb−8n合金にsbとBi
を添加してその融点が140Cとされた平均粒径20μ
簿の半田金属粒子を用いた。このように絶縁性接着剤(
6) K低融点半田金属粒子(7)が分散された接着剤
塗料を乾燥後の厚さが20μmとなるように剥離シート
上にコーターによって塗布して連結シートを得た。この
ようにして得た連結シートの剥離シートを剥離して基板
(3)上の各導電性リード(4)上の少くとも半導体集
積回路チップ(1)のIンデイング/IFツド(2)と
接続すべき部分に差し渡ってその接着剤層(5)を載せ
、これの上に、第2図に示すようK、集積回路チップ(
1)をその各がンデイングノ母ツド(2)が対応する導
電性リード(4)上に、互いに接続すべき部分が接着剤
層(5)を介して重なり合うように載せ、両者を170
C下で50ky/チツプで15秒間加圧圧着した。この
ようにすると、接着剤層(5)中の接着剤が加熱によっ
て流動性を呈するので、特に基板(3)及び集積回路チ
ップ(1)の互いの対向面より実質的突出しているため
に圧力が掛けられる導電性リード(4)とこれに対応す
るIンデイング74ツド(2)との間に介在する絶縁性
接着剤(6)の多くが側方に押し出され、これら導電性
リード(4)とぎ・ンデイングパッド(2)との間にお
いて半田金属粒子(7)が、その加熱加圧によって第3
図に示すように溶融圧潰され、導電性リード(4)とデ
ンデイングノヤツド(2)ヒ0間が半田づけされて両者
が電気的に接続される。
10 parts by volume of low melting point solder metal particles (7) were dispersed in 100 parts by volume of the solid content of the insulating adhesive K having this composition. These metal particles are added to the Pb-8n alloy with sb and Bi.
The average particle size was 20μ with the melting point of 140C.
The solder metal particles of the book were used. Insulating adhesive (
6) An adhesive paint in which K low melting point solder metal particles (7) were dispersed was applied onto a release sheet using a coater so that the thickness after drying was 20 μm to obtain a connection sheet. The release sheet of the connection sheet thus obtained is peeled off and connected to at least the I/IF leads (2) of the semiconductor integrated circuit chip (1) on each conductive lead (4) on the substrate (3). Place the adhesive layer (5) over the desired area, and place the integrated circuit chip (K) on top of this as shown in Figure 2.
1) are placed on the conductive leads (4) corresponding to the conductive leads (2) so that the parts to be connected to each other overlap via the adhesive layer (5), and both are bonded at 170°C.
Pressure bonding was carried out under C for 15 seconds at 50 ky/chip. In this way, since the adhesive in the adhesive layer (5) becomes fluid when heated, pressure is applied, especially since the adhesive in the adhesive layer (5) substantially protrudes from the mutually facing surfaces of the substrate (3) and the integrated circuit chip (1). Much of the insulating adhesive (6) interposed between the conductive lead (4) on which the wire is hung and the corresponding indexing 74 (2) is pushed out to the side, and these conductive leads (4) The solder metal particles (7) are heated and pressurized between the sharpening/nding pad (2) and the third
As shown in the figure, it is melted and crushed, and the conductive lead (4) and the connecting wire (2) are soldered to electrically connect them.

この場合加熱加圧によって、流動性に富んだ状態とされ
た絶縁性接着剤(6)が、導電性リード(4)とダンデ
ィング/IPツド(2)との間から外側に押し出され、
両者が半田金属によって良好に融着され、その接続部外
に押し出された絶縁性接着剤(6)が導電性を有する金
属粒子(7)を良好に包み込み、且つ隣り合う接続部間
にこの接着剤(6)が多量に存在することKよって基板
(3)と半導体集積回路チップ(1)とが強固に固着さ
れる。
In this case, by heating and pressurizing, the insulating adhesive (6) in a highly fluid state is extruded outward from between the conductive lead (4) and the danding/IP lead (2),
The two are well fused together by the solder metal, and the insulating adhesive (6) pushed out of the connection area wraps the conductive metal particles (7) well, and this adhesion is maintained between the adjacent connection areas. Due to the presence of a large amount of the agent (6), the substrate (3) and the semiconductor integrated circuit chip (1) are firmly fixed to each other.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら斯るゲンデイング/母ツド(2)とこれに
対応する導電性リード(4)との間の導通抵抗はバラツ
キが大きく、平均が100以上もあった。これにつき本
発明者が種々研究したところ、この導通抵抗が比較的大
きいのは例えば170Cに加熱したままの状態で加圧を
止めたときは、−ンデイング14ツド(2)である例え
ばAjスパッタ面への半田金属粒子(7)の所謂1ぬれ
”があまり良くないことから、その後冷却するに従いこ
の半田金属粒子(力のAIl側への接触面積が小さくな
ってしまうためであることがわかった。
However, the conduction resistance between the gendering/mother wire (2) and the corresponding conductive lead (4) varied widely, with an average of 100 or more. The present inventor has conducted various studies on this and found that this conduction resistance is relatively large when the pressure is stopped while heating to 170C, for example, when the Aj sputtering surface is 14° (2). It was found that this is because the so-called "1 wetting" of the solder metal particles (7) to the solder metal particles (7) was not very good, and as the solder metal particles (7) were cooled thereafter, the contact area of the solder metal particles (to the A1 side of the force) became smaller.

本発明は斯る点に鑑み半導体集積回路チップ(11のが
ンデイングI4ツド(2)と1例えばフィルムキャリア
テープの導電性リード(4)との間の導電抵抗値を小さ
くする様にし、信頼性の高い接続が出来る様にすること
を目的とする。
In view of this point, the present invention is designed to reduce the conductive resistance value between the semiconductor integrated circuit chip (11) and the conductive leads (4) of a film carrier tape, for example, to improve reliability. The purpose is to enable high-quality connections.

〔問題点を解決するための手段〕[Means for solving problems]

本発明配線基板の接続方法は第1図に示す如(複数の導
電/母ターン(4) 、 (41・・・・・・が配され
た基板(3)と、この複数の導電・ダターン(4) 、
 (41・・・・・・K対応して電気的に接続される複
数の導電体(2) 、 (21・・・・!・とを有し、
この導電/#ターン(4) 、 (4)・・曲とこれに
対応する導電体(21、(21・・・・・・とが重ね合
せられて両者間に、絶縁性接着剤(6)に低融点金属粒
子(7)が分散された接着剤層(5)を配して、加圧加
熱されてこの導電/4’ターン(4)、(4)・・・・
・・とこれに対応する導電体(2) 、 (2) 曲・
・とをこの金属粒子(7)の溶融により電気的に接続し
、この加圧状態のまま所定の温度まで冷却する様忙した
ものである。
The method of connecting the wiring board of the present invention is as shown in FIG. 4),
(41...K) has a plurality of electrically connected conductors (2), (21...!...),
These conductive/# turns (4), (4)... and the corresponding conductors (21, (21...) are superimposed and an insulating adhesive (6) is applied between them. An adhesive layer (5) in which low-melting point metal particles (7) are dispersed is placed on the surface of the adhesive layer (5), and the conductive/4' turns (4), (4) are heated under pressure.
...and the corresponding conductor (2), (2) song...
* and are electrically connected by melting the metal particles (7), and are then cooled down to a predetermined temperature while maintaining this pressurized state.

〔作用〕[Effect]

斯る本発明に依れば、導電パターン(41、(41・・
曲とこれに対応する導電体(21、(2+・・曲との間
に絶縁性接着剤(6)に低融点金属粒子(7)が分散さ
れた接着剤層(5)を配して、これ等間を加圧加熱して
金属粒子(7)の溶融によりこの導電ノ々ターン(41
、(41・・−と導を体(21、(2+・・・・・・と
を電気的に接続し、その後加圧状態のまま所定の温度ま
で冷却する様にしたので、低融点金属粒子(7)と導電
・母ターン(4) 、 (41・曲・及び導電体(2+
 、 (21・・・・・・との接触面積がこの金属粒子
(7)の溶融時と変わることなく、この導電−ぐターン
(4)、(4)・・・と導電体(2+ 、 (2)・・
曲との間の導電抵抗は極めて小さく全て例えば1Ω以下
となり信頼性の高い接続ができる。
According to the present invention, the conductive patterns (41, (41...
An adhesive layer (5) in which low melting point metal particles (7) are dispersed in an insulating adhesive (6) is arranged between the song and the corresponding conductor (21, (2+...), The conductive no-turns (41) are melted by applying pressure and heating between these metal particles (7).
, (41. (7) and conductive/mother turn (4), (41/curve/and conductor (2+
, (21...) are the same as when the metal particles (7) are melted, and the conductive turns (4), (4)... and the conductors (2+, ( 2)...
The conductive resistance between the cable and the cable is extremely small, for example, less than 1Ω, allowing a highly reliable connection.

〔実施例〕〔Example〕

以下図面を参照しながら本発明配線基板の接続方法の一
実施例につき説明しよう。
An embodiment of the wiring board connection method of the present invention will be described below with reference to the drawings.

本例に於いては第1図、第5図に示す如く複数個例えば
各辺に30個のゲンディングノ譬ツド(2) 、 (2
)・・・・・・をフィルムキャリアテープの導電性リー
ド(4)。
In this example, as shown in FIGS. 1 and 5, there are a plurality of ending nodes (2), (2
) is the conductive lead (4) of the film carrier tape.

(4)・・・・・・K接続するのに以下述べる如くして
行う。このフィルムキャリアテープは前述の如く一すイ
ミドより成るフレキシブル基板(3)上に被着された厚
す18μmのCu箔が選択的にエツチングされIり一ン
化されて半導体集積回路チップ(1)の複数のゲンディ
ングノ譬ツド(21、(2+・・・・・・K対応して電
気的に接続される複数の導電性リード(4) 、 (4
)・・曲が形成されたものである。
(4)...K connection is performed as described below. As mentioned above, this film carrier tape is made by selectively etching a 18 μm thick Cu foil adhered to a flexible substrate (3) made of monoimide to form a semiconductor integrated circuit chip (1). A plurality of conductive leads (4) , (4
)...is what the song was formed from.

この半導体集積回路チップ(1)をフィルムキャリアテ
ープ上に接続固定するのに剥離シート上に接着剤層(5
)を塗布した連結シートを用意する。この連結シートの
接着剤層(5)は前述同様の本のでホットメルトタイプ
の絶縁性接着剤(6)に半田金属粒子(7)を分散し九
ものである。
To connect and fix this semiconductor integrated circuit chip (1) on the film carrier tape, an adhesive layer (5
) Prepare a connecting sheet coated with The adhesive layer (5) of this connection sheet is made of a hot-melt type insulating adhesive (6) with solder metal particles (7) dispersed in the same manner as described above.

この連結シートの剥離シートを剥離して基板(3)、上
の各導電性リード(4) 、 (4)・・・・・・上の
少な(とも半導体集積回路チップ(1)のゴンデイング
Δツド(2) 、 (2)・・・と接続すべき部分に差
し渡って、その接着剤層(5)を載せ、これの上に第2
図に示すように、集積回路チップ(1)をその各がンデ
ィングノ々ツド(21、(21・・・が対応する導電性
リード(41、(4)・・・・・・上に互いに接続すべ
き部分が接着剤層(5)を介して重なり合うように載せ
、両者を17or:、 5oky/チツプで15秒間加
熱加圧する。この場合接着剤層(5)中の絶縁性接着剤
が加熱によって流動性を呈するので、特に基板(3)及
び集積回路チップ(1)の互いの対向面より実質的に突
出しているために圧力が掛けられる導電性リード(41
、(4)・・・・・・とこれに対応するがンディングパ
ッド(2) 、 (21・・・・・・との間に介在する
絶縁性接着剤(6)の多くが側方に押し出され、これら
導電性リード(4)。
Peel off the release sheet of this connection sheet to remove the conductive leads (4), (4)... Place the adhesive layer (5) over the parts to be connected to (2), (2)..., and place the second adhesive layer on top of this.
As shown in the figure, an integrated circuit chip (1) is connected to each other on a corresponding conductive lead (41, (4)... The parts to be bonded are placed on top of each other with the adhesive layer (5) interposed between them, and both are heated and pressed for 15 seconds using 17or:, 5oky/chip.In this case, the insulating adhesive in the adhesive layer (5) is heated. The conductive leads (41) exhibit fluidity and are therefore subject to pressure, especially since they substantially protrude from the mutually facing surfaces of the substrate (3) and the integrated circuit chip (1).
, (4)... and the corresponding landing pad (2), (21...), much of the insulating adhesive (6) is pushed out to the side. These conductive leads (4).

(4)・・・・・・とゲンディングノ臂ツド(21、(
21・・・・・・との間において半田金属粒子(])が
、その加熱加圧によって第3図に示すように溶融圧潰さ
れ、導電性リード(4)。
(4)...... and Gending's arm (21, (
As shown in FIG. 3, the solder metal particles (]) are melted and crushed between the conductive leads (4) by heating and pressurizing them between the conductive leads (4).

(4)・・・・・・と?ンディングパッド(2) 、 
(2)・・・・・・との間が半田付けされて両者が電気
的Km続される。
(4)...and? landing pad (2),
(2) . . . are soldered to electrically connect them.

本例に於いてはその後この両者間の50 kf/fツブ
の加圧をそのまま継続した状態でこの両者が例えば60
11なるまで冷却する。
In this example, after that, while the pressure of 50 kf/f between the two is continued, the pressure is increased to 60 kf/f, for example.
Cool until it reaches 11.

このようにしたがンディングパッド(2) 、 (2)
・・曲ト導電性リード(41、(41・・曲との接続部
における導通抵抗はlΩ以下であり、隣り合う接続部間
の絶縁抵抗は109Ω以上であった。
Landing pad (2), (2)
... Curved conductive lead (41, (41...) The conduction resistance at the connection part with the bend was less than 1Ω, and the insulation resistance between adjacent connection parts was 109Ω or more.

このように接続部における導通抵抗が充分小さくされ、
接続部間の絶縁抵抗を充分大となし得るのは上述したよ
うに加熱加圧によって、流動性に富んだ状態とされた絶
縁性接着剤(6)が導電性+7 wド(41、(41・
・・・・・と?ンディング/譬ツド(2) 、 (21
・・・・・・との間から外側に押し出され、両者が半田
金属によって良好に融着され、その接続部外に押し出さ
れた絶縁性接着剤(6)が導電性を有する金属粒子(7
)を良好に包み込み、且つ隣り合う接続部間にこの絶縁
性接着剤(6)が多量に存在するととkよって基板(3
)と半導体集積回路チップ(1)とが強固に固着される
In this way, the conduction resistance at the connection part is made sufficiently small,
The reason why the insulation resistance between the connecting parts can be made sufficiently high is that the insulating adhesive (6), which has been made highly fluid by heating and pressurizing, has a conductivity of +7 w (41, (41・
·····and? Ending/Marriage (2), (21
The insulating adhesive (6) is extruded outward from between the two, and the two are well fused together by the solder metal, and the insulating adhesive (6) extruded out of the connection is bonded to the conductive metal particles (7).
), and if there is a large amount of this insulating adhesive (6) between adjacent connection parts, the substrate (3)
) and the semiconductor integrated circuit chip (1) are firmly fixed.

この場合本例に於いては導電性リード(41、(41・
・・・・・・・・とダンディングパッド(21、(2)
・・−・・とが半田金属粒子(7)によって良好に融着
された後この両者間の加圧を保持したままで600まで
冷却するのでそのままで絶縁性接着剤(6)が固まり、
半田金属粒子(7)と導電性リード(4) 、 (41
・・・・・・及びゴンデイング/ダツド(2)。
In this case, in this example, the conductive leads (41, (41・
...... and Danding Pad (21, (2)
After the solder metal particles (7) have successfully fused the .
Solder metal particles (7) and conductive leads (4), (41
...and Gonding/Datsud (2).

(2)・・・・・・との接触面積が、この半田金属粒子
(7)の溶融時と変わることなく、この導電性リード(
41、(41・・・・・・とダンディングパッド(21
、(2)・・・・・・との間の導電抵抗を極めて小さく
接続部の全てを例えば1Ω以下とでき信頼性の高い接続
ができる。
(2)... The contact area with this conductive lead (
41, (41...... and danding pad (21
, (2) . . . can be made extremely small, and all of the connecting portions can be, for example, 1Ω or less, and a highly reliable connection can be achieved.

尚、上述の接合時の加熱温度、云い換えれば。In addition, the heating temperature during the above-mentioned bonding, in other words.

金属粒子の融点は50C〜350C1好ましくは800
〜260Cに選定される。ここにこの加熱温度、すなわ
ち金属粒子の融点を50C以上、好ましくは80C以上
に選定するのは、集積回路装置の例えば電子様器への実
装状態、すなわち使用状態で、50C未満、好ましくは
80C未満の外囲温度で、導電性リード(4)とがンデ
ィングパッド(2)トの接続部において両者間を融着す
る金属が再溶融して剥離や接続不良が発生するような信
頼性の低下を回避するためであり、350C以下、好ま
しくは260C以下に選定するのはこれを超えるような
加熱処理に耐える基板材料の選定が困難となり、また加
熱手段、作業が煩雑となり、工業的に不利益となってく
ることに因る。
The melting point of the metal particles is 50C to 350C1, preferably 800C
~260C. The heating temperature, that is, the melting point of the metal particles, is selected to be 50C or higher, preferably 80C or higher, because the integrated circuit device is mounted in, for example, an electronic device, that is, in use, and is lower than 50C, preferably lower than 80C. At an ambient temperature of In order to avoid this, selecting a temperature of 350C or less, preferably 260C or less makes it difficult to select a substrate material that can withstand heat treatment exceeding this temperature, and the heating means and work become complicated, which is an industrial disadvantage. It depends on what is happening.

また上述例では60Cまで冷却したが、この温度は低融
点金属粒子(7)の融点以下であり、絶縁性接着剤(6
)が流動性を失う温度以下実際的には80C以下で常温
までの所定の温度である。
Further, in the above example, the temperature was cooled to 60C, but this temperature was below the melting point of the low melting point metal particles (7), and the insulating adhesive (60C) was cooled to 60C.
) loses its fluidity, which is actually a predetermined temperature of 80C or less, up to room temperature.

また、金属粒子は、七〇粒径を、導電性リード(4)と
これItするがンデイングノ々ツド(2)との接続部間
の間隔、すなわち隣り合う導電性リード(4)間、隣り
合うIンデイング・臂ツド(2)間の間隔の捧以下程度
に選定されることが望ましく、このようにするときは、
隣り合う接続部間が金属粒子によって短絡されるような
事故を確実に回避できることを確めた。
In addition, the metal particles have a particle diameter of 70 mm, which corresponds to the distance between the conductive leads (4) and the connecting nodes (2), that is, the distance between adjacent conductive leads (4), and the distance between adjacent conductive leads (4). It is desirable that the distance between the indentation and armpit (2) be selected to be less than or equal to the distance between the two.
It has been confirmed that accidents such as short circuits between adjacent connections due to metal particles can be reliably avoided.

また、上述した導電性リードとこれに対応するがンデイ
ングパツド間に介在させる予めシート状とされた或いは
基板上に予め塗布される接着剤層中の接着剤と金属粒子
との混合割合は、接着剤(固形分)100容量部に対し
て、金属粒子は0.5〜50容量部に選定する。これは
0.5未満では低抵抗接続が不充分となる場合があり、
50容量部を越えると接続部以外における金属粒子相互
の絶縁が不完全となったり、機械的接着強度が不充分と
なってくる場合があるととKよる。
Furthermore, the mixing ratio of the adhesive and metal particles in the adhesive layer that is pre-formed into a sheet or that is pre-coated on the substrate to be interposed between the conductive leads and the corresponding bonding pads is determined by the adhesive layer. (Solid content) 0.5 to 50 parts by volume of metal particles is selected for 100 parts by volume. If this is less than 0.5, low resistance connection may be insufficient.
According to K, if the amount exceeds 50 parts by volume, the insulation between the metal particles other than the connection portion may become incomplete or the mechanical adhesion strength may become insufficient.

また、これに用いられる絶縁性接着剤としては、上述し
た接合時の加圧加熱条件下で少くともm−は、流動性が
得られる接着剤、例えばゴム系、或いはエチレン−酢酸
ビニル系のいわゆるホットメルトタイプ、或いは熱架橋
する工fキシ系の熱硬化型の接着剤を用いることができ
る。
In addition, the insulating adhesive used for this purpose is an adhesive that has at least m-flow properties under the pressure and heating conditions during bonding described above, such as a rubber-based adhesive or an ethylene-vinyl acetate-based adhesive. A hot-melt type adhesive or a thermosetting adhesive based on a thermosetting resin that undergoes thermal crosslinking can be used.

また上述した例においては、複数の導電性リードとこれ
に対応して接続されるべきがンデイングI4ットとを予
めシート状にされた接着剤層を介在させ、て重ねるか、
導電性リード上に接着剤層を塗布しておくか貼り合せて
おいてこの接着剤層を介して重ね合せて加熱加圧するこ
とによって互いに重なる導電性リードとがンデイングパ
ツドとの間から多くの絶縁性接着剤を他部にその流動性
によって排除して金属粒子によって良好に導電性−リー
ドとがンデイング/4ツド間の融着を行い、且つその接
続部外に押し出された絶縁性接着剤が導電性を有する金
属粒子を良好に包み込み、且つ隣り合う接続部間にこの
接着剤が多量に存在することKよって機械的に強固にそ
の固着を行うものであるが、このような現象が効果的に
生じ、導通抵抗を0.1Ω以下、絶縁抵抗を107Ω以
上、好ましくは109Ωとするkは、絶縁性接着剤の加
熱接合時のM@F@I(メルト・フロー・インデックス
)は、0.001以上、好ましくはo、oos以上とす
る。このM@F・■は、ASTM 、 D1238のA
法またはJIS。
Further, in the above-mentioned example, a plurality of conductive leads and corresponding conductive leads to be connected are layered by interposing an adhesive layer formed in advance into a sheet, or
By applying an adhesive layer on the conductive leads or pasting them together, and applying heat and pressure to the conductive leads through the adhesive layer, a large amount of insulation can be created between the conductive leads and the bonding pad that overlap each other. The adhesive is expelled to other parts by its fluidity, and the metal particles provide good conductivity - bonding/welding between the leads and the four terminals, and the insulating adhesive pushed out of the connection part becomes conductive. The presence of a large amount of this adhesive between adjacent joints allows for a strong mechanical fixation, but this phenomenon is not effective. k, which makes the conduction resistance 0.1Ω or less and the insulation resistance 107Ω or more, preferably 109Ω, is M@F@I (melt flow index) during heat bonding of the insulating adhesive, and is 0.001. The above is preferably o, oos or more. This M@F・■ is ASTM, D1238 A
law or JIS.

K7210のA法に規定された装置で、所定の圧着温度
において2160 fの荷重を印加した時にオリアイス
(孔)から10分間に流出する樹脂のグラム数を示す本
のである。また、絶縁性接着剤層の厚さは、各接続部間
に生じる空間体積の10〜300%好ましくは30〜2
00%とし、その淳さは5〜200μmとすることが望
ましい。
This is a book that shows the number of grams of resin that flows out of an oriice (hole) in 10 minutes when a load of 2160 f is applied at a predetermined compression temperature using a device specified by Method A of K7210. Further, the thickness of the insulating adhesive layer is 10 to 300% of the space volume generated between each connection part, preferably 30 to 2%.
00%, and its thickness is preferably 5 to 200 μm.

また本発明は上述実施例に限らず本発明の要旨を逸脱す
ることなくその他種々の構成が取り得ることは勿論であ
る。
Furthermore, it goes without saying that the present invention is not limited to the above-described embodiments, and can take various other configurations without departing from the gist of the present invention.

〔発明の効果〕〔Effect of the invention〕

本発明に依れば、導電パターン(41、(4)・・・・
・・とこれに対応する導電体(21、(21・・−・・
との間に絶縁性接着剤(6) k低融点金属粒子(7)
が分散され九接着剤層(5)を配して、2等間を加圧加
熱して金属粒子(7)の溶融によりこの導電ノダターン
(4) 、 (4)・・・・・・と導電体(2) 、 
(2)・・・・・・とを電気的に接続し、その後この加
圧状態のまま所定の温度まで冷却する様にしたので低融
点金属粒子(7)と導電I4ターン(4) 、 (4)
・・・・・・及び導電体(2)。
According to the present invention, the conductive pattern (41, (4)...
... and the corresponding conductor (21, (21...
Insulating adhesive (6) k Low melting point metal particles (7)
are dispersed, a nine adhesive layer (5) is arranged, and the metal particles (7) are melted by applying pressure and heating between the two equal parts, thereby making the conductive particles (4), (4)... conductive. Body (2),
(2) ...... and then cooled to a predetermined temperature in this pressurized state, so that the low melting point metal particles (7) and the conductive I4 turns (4), ( 4)
...and conductor (2).

(2)・・・・・・どの接触面積がこの金属粒子(7)
の溶融時と変ることなく、この導電ノ母ターン(41、
(4)・・・・・・と導電体(2+ 、 (2+・・・
・・・どの間の導電抵抗は極めて小さく、例えば1Ω以
下とでき信頼性の高い接続ができる利益がある。
(2)...What contact area is this metal particle (7)
This conductive mother turn (41,
(4)... and conductor (2+, (2+...
... The conductive resistance between the two is extremely small, for example, 1Ω or less, which has the advantage of allowing highly reliable connections.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図及び第3図は夫々本発明配線基板の接続
方法の一実施例の説明に供する線図、第4図は半導体集
積回路チップの例を示す底面図、第5図は配線基板の要
部の拡大平面図である。 (1)は半導体集積回路チップ、(2)はがンデイング
ノ母ツド、(3)は基板、(4)は導電性リード、(5
)は接着剤層、(6)は絶縁性接着剤、(7)は半田金
属粒子である。 第4図 第5図
FIGS. 1, 2, and 3 are diagrams for explaining an embodiment of the wiring board connection method of the present invention, FIG. 4 is a bottom view showing an example of a semiconductor integrated circuit chip, and FIG. FIG. 3 is an enlarged plan view of main parts of the wiring board. (1) is a semiconductor integrated circuit chip, (2) is a metal bonding motherboard, (3) is a substrate, (4) is a conductive lead, (5)
) is an adhesive layer, (6) is an insulating adhesive, and (7) is a solder metal particle. Figure 4 Figure 5

Claims (1)

【特許請求の範囲】[Claims]  複数の導電パターンが配された基板と、前記複数の導
電パターンに対応して電気的に接続される複数の導電体
とを有し、前記導電パターンとこれに対応する前記導電
体とが重ね合せられて両者間に、絶縁性接着剤に低融点
金属粒子が分散された接着剤層を配して、加圧加熱され
て前記導電パターンとこれに対応する前記導電体とを、
前記金属粒子の溶融により電気的に接続し、その後前記
加圧状態のまま所定の温度まで冷却することを特徴とす
る配線基板の接続方法。
It has a substrate on which a plurality of conductive patterns are arranged, and a plurality of conductors that are electrically connected in correspondence with the plurality of conductive patterns, and the conductive patterns and the corresponding conductors are overlapped. An adhesive layer having low melting point metal particles dispersed in an insulating adhesive is placed between the two, and the conductive pattern and the corresponding conductor are heated under pressure.
A method for connecting wiring boards, comprising electrically connecting by melting the metal particles, and then cooling to a predetermined temperature while maintaining the pressurized state.
JP1400785A 1985-01-28 1985-01-28 Method of connection for wiring substrate Pending JPS61174643A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1400785A JPS61174643A (en) 1985-01-28 1985-01-28 Method of connection for wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1400785A JPS61174643A (en) 1985-01-28 1985-01-28 Method of connection for wiring substrate

Publications (1)

Publication Number Publication Date
JPS61174643A true JPS61174643A (en) 1986-08-06

Family

ID=11849151

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1400785A Pending JPS61174643A (en) 1985-01-28 1985-01-28 Method of connection for wiring substrate

Country Status (1)

Country Link
JP (1) JPS61174643A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5323535A (en) * 1991-02-25 1994-06-28 Canon Kabushiki Kaisha Electrical connecting member and method of manufacturing the same
US5819406A (en) * 1990-08-29 1998-10-13 Canon Kabushiki Kaisha Method for forming an electrical circuit member
US6015081A (en) * 1991-02-25 2000-01-18 Canon Kabushiki Kaisha Electrical connections using deforming compression
WO2023234056A1 (en) * 2022-05-31 2023-12-07 株式会社レゾナック Method for producing circuit connection structure, and circuit connection device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5819406A (en) * 1990-08-29 1998-10-13 Canon Kabushiki Kaisha Method for forming an electrical circuit member
US5323535A (en) * 1991-02-25 1994-06-28 Canon Kabushiki Kaisha Electrical connecting member and method of manufacturing the same
US6015081A (en) * 1991-02-25 2000-01-18 Canon Kabushiki Kaisha Electrical connections using deforming compression
WO2023234056A1 (en) * 2022-05-31 2023-12-07 株式会社レゾナック Method for producing circuit connection structure, and circuit connection device

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