JPS6135704B2 - - Google Patents

Info

Publication number
JPS6135704B2
JPS6135704B2 JP52044269A JP4426977A JPS6135704B2 JP S6135704 B2 JPS6135704 B2 JP S6135704B2 JP 52044269 A JP52044269 A JP 52044269A JP 4426977 A JP4426977 A JP 4426977A JP S6135704 B2 JPS6135704 B2 JP S6135704B2
Authority
JP
Japan
Prior art keywords
region
forming
substrate
dielectric layer
iil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52044269A
Other languages
English (en)
Japanese (ja)
Other versions
JPS53129589A (en
Inventor
Osamu Inoe
Tsuneo Funatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4426977A priority Critical patent/JPS53129589A/ja
Publication of JPS53129589A publication Critical patent/JPS53129589A/ja
Publication of JPS6135704B2 publication Critical patent/JPS6135704B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/65—Integrated injection logic
    • H10D84/658—Integrated injection logic integrated in combination with analog structures

Landscapes

  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Logic Circuits (AREA)
JP4426977A 1977-04-18 1977-04-18 Integrated circuit unit Granted JPS53129589A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4426977A JPS53129589A (en) 1977-04-18 1977-04-18 Integrated circuit unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4426977A JPS53129589A (en) 1977-04-18 1977-04-18 Integrated circuit unit

Publications (2)

Publication Number Publication Date
JPS53129589A JPS53129589A (en) 1978-11-11
JPS6135704B2 true JPS6135704B2 (enrdf_load_stackoverflow) 1986-08-14

Family

ID=12686787

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4426977A Granted JPS53129589A (en) 1977-04-18 1977-04-18 Integrated circuit unit

Country Status (1)

Country Link
JP (1) JPS53129589A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59145538A (ja) * 1983-10-21 1984-08-21 Hitachi Ltd 半導体装置の製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS517594B2 (enrdf_load_stackoverflow) * 1972-07-07 1976-03-09
JPS5179591A (enrdf_load_stackoverflow) * 1975-01-06 1976-07-10 Hitachi Ltd
DE2507366C3 (de) * 1975-02-20 1980-06-26 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Unterdrückung parasitärer Schaltungselemente

Also Published As

Publication number Publication date
JPS53129589A (en) 1978-11-11

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