JPS6135467U - Synchronous signal processing circuit - Google Patents
Synchronous signal processing circuitInfo
- Publication number
- JPS6135467U JPS6135467U JP11741084U JP11741084U JPS6135467U JP S6135467 U JPS6135467 U JP S6135467U JP 11741084 U JP11741084 U JP 11741084U JP 11741084 U JP11741084 U JP 11741084U JP S6135467 U JPS6135467 U JP S6135467U
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- signal processing
- synchronization signal
- processing circuit
- equalization
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Synchronizing For Television (AREA)
- Television Signal Processing For Recording (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【図面の簡単な説明】
第1,2図は、それぞれこの考案の同期信号処理回路の
一実施例を示す概略回路構成図及び回路各部の信号波形
図、第3,4図は、それぞれ従来の同期信号処理回路の
一例を示す概略回路構成図及び回路各部の信号波形図で
ある。
2・・・同期分期回路、3・・・積分回路、11・・・
同期−信号処理回路、12・・・ゲーl・回路、12a
・・・単安定マルチバイブレータ、12b・・・アンド
ゲート回路、13・・・リトリガラブル単安定マルチバ
イブレータ。[Brief Description of the Drawings] Figures 1 and 2 are schematic circuit configuration diagrams and signal waveform diagrams of various parts of the circuit, respectively, showing one embodiment of the synchronous signal processing circuit of this invention, and Figures 3 and 4 are diagrams of conventional synchronous signal processing circuits, respectively. 1 is a schematic circuit configuration diagram showing an example of a synchronization signal processing circuit and a signal waveform diagram of each part of the circuit; FIG. 2...Synchronous period circuit, 3...Integrator circuit, 11...
Synchronization-signal processing circuit, 12... game circuit, 12a
... Monostable multivibrator, 12b... AND gate circuit, 13... Retriggerable monostable multivibrator.
Claims (1)
変動が予想される同期信号が供給され、この同期信号中
の垂直同期信号の前後に挿入された等化バルスを抜き取
るゲート回路と、このゲート回路が抜き取った等化パル
スが供給され、前挿入の等化パルスから後挿入の等化パ
ルスまでを含む期間中持続するパルスを形成し、このパ
ルスを擬似垂直同期信号とする信号処理回路とからなる
同期信号処理回路。A gate circuit that is supplied with a synchronization signal in which a variation in the pulse width of a cutting pulse inserted into the vertical synchronization signal is expected, and extracts equalization pulses inserted before and after the vertical synchronization signal in the synchronization signal; and this gate circuit. A signal processing circuit that is supplied with the equalization pulse extracted by the controller, forms a pulse that lasts during the period from the pre-inserted equalization pulse to the post-inserted equalization pulse, and uses this pulse as a pseudo vertical synchronization signal. Synchronous signal processing circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11741084U JPS6135467U (en) | 1984-07-31 | 1984-07-31 | Synchronous signal processing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11741084U JPS6135467U (en) | 1984-07-31 | 1984-07-31 | Synchronous signal processing circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6135467U true JPS6135467U (en) | 1986-03-04 |
Family
ID=30676321
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11741084U Pending JPS6135467U (en) | 1984-07-31 | 1984-07-31 | Synchronous signal processing circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6135467U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63201861U (en) * | 1987-06-19 | 1988-12-26 |
-
1984
- 1984-07-31 JP JP11741084U patent/JPS6135467U/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63201861U (en) * | 1987-06-19 | 1988-12-26 | ||
JPH0544205Y2 (en) * | 1987-06-19 | 1993-11-09 |
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