JPS6135375A - Interruption control circuit of digital circuit inspecting device - Google Patents

Abstract

PURPOSE:To allow the inspecting device to judge an interruption mode automatically and to also control the signal direction of an interruption terminal by masking every interruption request terminal in interruption mode through operator's switch operation. CONSTITUTION:An interruption control switch 22 which masks an interruption request from a circuit board 6 to be inspected, level by level, and a signal direction control switch 22' which controls the direction of a signal in two directions of a specific interruption terminal are provided on a repeater (POD)2. Then, a necessary interruption request signal among signals from the circuit board 6 to be indpected is gated with a signal from a switch 22 and outputted as it is, and the remaining interruption request signals are gated with the signal from the switch 22 and then outputted through a tristate buffer whose signal direction is controlled with the switch 22'. Consequently, such trouble that a gate output and processor output short-circuit each other never occurs and proper interruption control is performed.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention is applied to an interrupt control circuit of a digital circuit testing device, and more specifically, the present invention is applied to an interrupt control circuit of a digital circuit testing device. The present invention relates to an interrupt control circuit for a digital circuit testing device in which the signal direction of an interrupt terminal can be controlled by a switch operation.

(Prior Art) In recent years, with the progress and development of semiconductor technology, microprocessors (microcomputers) have come to be used in all industrial fields.

Most of the conventional digital circuits (especially control circuits) have been replaced with microprocessors, making the circuits more compact and improving their reliability. On the other hand, the conversion of digital circuits into microprocessors has also caused the following problems.

In other words, investigating the state of a circuit has become a skill. In the case of a conventional digital circuit using 10, the waveforms of most parts of the circuit can be observed with a logic analyzer or an oscilloscope, making it easy to find faulty locations.

On the other hand, in the case of a digital circuit with a built-in microprocessor, most of the operations are performed inside the microprocessor, so its internal state cannot be directly observed. In such a case, it is impossible to completely inspect the circuit state using a logic analyzer or an oscilloscope as in the past. Therefore, a digital circuit testing device called a microprocessor analyzer or a personal debugger has appeared in order to test the operating state of a digital circuit incorporating a microprocessor. This type of device has its own built-in microprocessor, and the circuit board under test (user board).
For example, a probe is connected to the data bus, the state of the data bus is synchronized with the internal clock or the clock on the circuit board under test, and the operating state of the circuit is determined based on this data. There is.

FIG. 4 is a diagram showing the basic concept of this type of device. In the figure, 1 is the digital circuit testing device main body, 2 is the POD
It is. POD is a repeater between the inspection device main body 1 and the circuit board 6 to be tested. The microprocessor mounted on the POD 2 matches that in the circuit board 6 to be tested.

The POD 2 and the inspection device main body 1 are connected by a cable 3.

4 is a probe attached to the tip of the POD via a cable 5. The probe 4 is connected to the processor socket of the circuit board 6 to be tested as shown in the figure. A digital circuit surrounding a microprocessor is attached to the circuit board 6 to be tested. Note that most of them are connected to the circuit board 6 to be tested using a socket.

In such a digital circuit testing device, the probe 4 is attached to the digital bus of the circuit board to be tested 6, and the state on the data bus at a certain time is captured internally by a clock from inside the testing device or from outside. , and sent to the inspection device main body 1. Inspection device body 1
The machine processes the captured data according to a predetermined algorithm, and displays the results on the built-in CRT. Operator (user)
By looking at this display, the operating state of the circuit board 6 to be tested (for example, whether it is normal or abnormal) can be known. Alternatively, depending on the case, the testing apparatus itself may be provided with a function of determining whether or not the operation of the circuit board 6 to be tested is normal, and the determination result may be displayed on the CRT.

(Problems to be Solved by the Invention) By the way, in this type of inspection device, the microprocessor (hereinafter simply referred to as a processor) installed in the POD2 (see Figure 4) is, for example, Intel's 1
APX186 is used.

This 1APX186 has four interrupt terminals from INTφ to lNT3, and among these, lNT2 and lNT
3 is bidirectional. This microprocessor has three interrupt modes as shown in FIG.

In the same figure (A), all interrupt signals from the interrupt signal generation source are input to the interrupt terminals INTφ to IN of the processor 11.
When input to T3, (b) and (c) of the same figure show that among the interrupt terminals of the processor 11, INTφ, lNT1 are input terminals, lNT2 . The cases in which lNT3 is used as an output terminal are shown respectively.

In FIG. 3(0), an interrupt signal lNT generated from a programmable interrupt controller 12.13 enters interrupt terminals INTφ, lNT1 of the processor 11, and interrupt terminals rNT2. Programmable interrupt controller 1 as an interrupt confirmation signal from processor 11 from INT3, respectively.
It is output to the INTAI child of 2.13. Note that as the programmable interrupt controller 12.13, for example, 8259A manufactured by Intel Corporation is used. In the case of (c) in the same figure, the interrupt signal INT output from the programmable interrupt controller 14 enters the processor 11 interrupt terminal INTφ. Then, from the processor 11, an acknowledge signal of the interrupt signal inputted to the INTφ terminal is outputted from the NT2 terminal, and the
Enter the TA terminal. On the other hand, the programmable interrupt controller 14 outputs a decoding signal to the cascade address decoder 15. Then, the interrupt control [1
-The input signal from La 15 is ¥! A 1-keyed interrupt signal is generated and input to the interrupt terminal lNT1 of the processor 11. An interrupt terminal INT3 of the processor 11 outputs a signal for activating an interrupt to the programmable interrupt controller 14.

The above-mentioned interrupt mode is determined by the processor's internal control block (internal registers in memory and I10).
This is done by accessing the map (which can be set and accessed for each block so that the position can be re-specified on the map) with software and writing mode selection information. Therefore, it cannot be observed from the outside in terms of hardware. Therefore, when used in the modes shown in Figures 5(b) and 5(c), the interrupt terminal of the processor is set to output mode when using the conventional method of gating the line to the processor to cut the input signal. If this happens, there will be a problem that the gate output and the processor output will be short-circuited.

The present invention has been made in view of the above points, and its purpose is to enable an inspection device to mask each interrupt request terminal in interrupt mode by a switch operation by an operator (user). The object of the present invention is to realize an interrupt control circuit for a digital circuit testing device that can automatically determine the interrupt mode and also control the signal direction of one interrupt terminal.

(Means for Solving the Problems) The present invention solves the above-mentioned problems, when a POD equipped with a microprocessor capable of multi-level interrupts is used to test a circuit board to be tested. Equipped with an interrupt control switch on the top that masks interrupt requests from the circuit board under test for each level, and a signal direction control switch that controls the direction of signals in both directions only for specific interrupt terminals. Among the interrupt request signals from the circuit board under test, a predetermined later signal is gated by the signal from the interrupt control switch and output as is, and the remaining interrupt request signals are output from the interrupt control switch. The present invention is characterized in that the signal is ligated and then output via a tri-state buffer whose direction of the signal is controlled by a signal direction control switch.

(Embodiment) FIG. 2 is a configuration block diagram showing an embodiment of a digital circuit testing device using the present invention. In the figure, 2 is P
OD, 6 is the circuit board to be tested (user board), P
The OD2 is connected to the test device main body (not shown) and the circuit board to be tested 6 via cables 3.5, and signals are exchanged.

21 is a processor, 22 is an interrupt control switch that outputs a masking signal for each interrupt level of the processor 21, and 22' is a signal direction control switch for controlling the signal direction of a specific interrupt terminal. For example, a push button switch or a dip switch is used as the interrupt control switch 22 and the signal direction control switch 22'. The switch 22 is designed to mask the interrupt signal when the contact is turned on. As the processor 21, one equipped with a plurality of interrupt terminals is used. As such a processor, for example, the above-mentioned iΔPX186 is used.

23 is an interrupt control signal set by the interrupt control switch 22 and a control signal from the inspection device main body]
■] This is an interrupt control circuit that receives `` and INTE and controls the masking of interrupt signals for each interrupt terminal and the input/output direction of a specific interrupt terminal of the processor 21, and is the core part of the present invention. be.

FIG. 3 is a diagram showing the flow of signals in the interrupt control circuit 23. INTφ to INT3 are sent from the circuit board 6 to be tested via the cable 5. Interrupt request signal, CASCAD
E is a signal direction control signal that controls the input/output direction of a specific interrupt terminal of the processor 21, rNTMφ~INT
M3 is an interrupt mask signal for masking the interrupt terminals of the processor 21 for each terminal, and these signals are generated by the interrupt control switch 22 and the signal direction control switch 22', respectively. TNTφ to INT3 are interrupt request signals input to the interrupt control circuit, and are generated by the circuit board 6 to be tested, for example. ACT is a signal indicating that the test equipment main body is in the acceleration operation, INTE is an interrupt permission signal output from the test equipment main body, and rNTφ' to INT3' are interrupts newly created by the interrupt control circuit. These signals enter the processor 21 with request signals.

FIG. 1 is a diagram showing a specific configuration of an interrupt control circuit according to the present invention. In the figure, SWl is a switch that generates the signal direction control signal CASCADE, SW2 is a switch that generates an interrupt mask signal INTMO, SWs is a switch that generates an interrupt mask signal INTM1, and SW4 is a switch that generates an interrupt mask signal IN King M2. switch, SW
s is a switch that generates the interrupt mask signal INTM3. These switches SW1 to SWs correspond to the signal direction control switch 22' and the interrupt control switch 22 shown in FIG. Of these signals, interrupt mask signals INTMO to INTM3 are input to multi-input AND gates G1 to G4, respectively, and cascade signal CASCADE is input to AND gates G3 and G4. These switches SW + ~ SW
In order to maintain a reliable 111 IT level state when s is off, its signal line is connected to 5V with a pull-up resistor shown in the figure.

These AND gates G1 to G4 are also connected to an active operation signal ACT output from the inspection apparatus body after the interrupt enable signal INco000 outputted from the inspection apparatus body is inverted by an inverter G5. The interrupt request signals rNTφ to ■NT3 generated by the circuit board under test 6 (see FIG. 2) are input to each gate G as they are.
They are included individually in 1 to G4. ANDGATE G1. G2
, new interrupt request signals INTφ' and lNT1' are output, and new interrupt request signals INT2' and INT3' are output from the outputs of AND gates G3 and G4 via tristate buffers Gs and G7, respectively. . On the other hand, interrupt confirmation signals INIAφ and INIA outputted from the processor 21 (see FIG. 2) are input to the lines of new interrupt request signals rNT2' and TNT3' via tristate buffers G++ and Gs, respectively. The interrupt signal I enters the input side NT2°rNT3 line and is sent to the circuit board 6 to be tested. Among the turnout gates G6 to G9, G6 and G7 are controlled by receiving the output of the inverter G1o that receives the signal direction control signal as its control input, and the control input of G8 and G9 receives the signal direction control signal CASCADE. It just goes in and the output state is controlled. The operation of the circuit configured as described above will be explained as follows.

First, the interrupt mode is selected by the signal direction control signal CASCADE set by the operator (user). When the switch S W t is turned on, the signal direction control signal CASCADE becomes φ''. This signal turns on the tristate buffers Ga and Go, and G6 and G7 are inverted by the inverter Gso and turned off. In this state Now, the circuit shown in the figure is the new interrupt signal TNT2.
', INT3' line is an interrupt wF-'l='+N M I N from the processor 21 (see Figure 2).
I A Q , I N I A 1 will be received. Conversely, if the switch SW1 is turned off, the signal direction control signal CASCA'σ becomes 1''.This signal turns off the tri-state buffers Ga and Gs.
G6 and 07 are inverted by inverter G1o and turned on. Therefore, in this state, the interrupt signals TNTφ' to INT
All lines 3' become input lines to the processor 21.

Now, consider a case where the contact switch S W t is off and the signal direction control signal CASCADE is in the 111 TT mode. Interrupt request signals INTφ-INT3 are input to AND gates G1-G4, respectively.

If all other input signals to these AND gates G1-G4 are "1", interrupt request signals lNTφ-TN
T3 passes through these gates 01 to G4 as is and is transmitted to the processor 21.

There are two types of signals that control the opening and closing of the AND gates G1 to G4: one that is commonly applied to all the gates, and one that is applied to each gate individually. First, if the module specific to the processor used in the circuit board to be tested in the test equipment main body is in the active process, the active signal ACT output from the test equipment main body is 0'', and this signal ACT is Since it is input to all gates G1-G4, it masks all interrupt request signals.Therefore, in this case, the interrupt request signals INTφ~lN generated in the circuit board under test
Since T1 does not reach the processor 21, the inspection apparatus main body can continue active processing.

In addition, by turning on the switch provided on the front panel (not shown) of the inspection device main body, the interrupt enable signal ■N
TE becomes "φ". This signal is inverted by inverter G5 and enters each AND gate G1 to G4. Therefore, when the INTE signal becomes "φ", each interrupt request signal I
It becomes possible to accept NTφ to rNT3. Conversely, when the interrupt enable signal I NTE becomes "1", the output of the inverter G5 becomes φ", masking all levels of interrupt requests.

Next, the operator individually selects the interrupt control switch 2.
2 (see FIG. 2), each interrupt signal can be masked. That is, switch SW 2
By turning on only the necessary switches among ~S W s, interrupt requests are masked for that line. Conversely, if you turn it off, you will be in an interrupt accepting state. These switches SW
2 to S W s are valid only when the interrupt enable signal INTE is "φ°", and if the inspection apparatus main body is in the active process, the active signal ACT becomes "φ°", so the switch SW 2 ~Interrupt requests are masked regardless of S W s.

In the above description, 1APX is used as the processor.
Although the case where a 186 is used is taken as an example, the processor used need not be limited to this, and any microprocessor can be used as long as it is capable of multi-level interrupts. For example, it may be iAPX188.

(Effects of the Invention) As described in detail above, according to the present invention, there is a switch on the POD that masks the interrupt request from the circuit board under test for each level, and a switch that masks the signal input from a specific interrupt terminal. By providing a switch that controls the output direction, interrupt requests during interrupt mode can be masked for each interrupt terminal by the operator's switch operation, and the input/output direction of the signal for a specific interrupt terminal can be controlled. can do. Therefore, according to the present invention, the disadvantage that the gate output and the processor output are short-circuited does not occur, and moreover, appropriate interrupt control can be performed.

[Brief explanation of the drawing]

FIG. 1 is an electric circuit diagram showing a specific configuration of the present invention, FIG. 2 is a block diagram showing an embodiment of a digital circuit testing device using the present invention, and FIG. 3 is a block diagram of a signal of an interrupt control circuit. FIG. 4 is a diagram showing the basic concept of the digital circuit testing device, and FIG. 5 is an explanatory diagram of the interrupt mode. 1... Inspection device body 2... POD3.5...
Cable 4...Probe 6...Test circuit board
11.21...Processors 12-14...Programmable interrupt controller 15...Cascade address decoder 22...Interrupt control switch 22'...Signal direction control switch 23...
Interrupt control circuit 24...Socket SW 1 to SW
s...Switches G1 to G4...And gate Gs, Gto...Inverter

Claims (1)

[Claims] When inspecting a circuit board under test using a POD equipped with a microprocessor that can handle multiple levels of interrupts, an interrupt control is provided that masks interrupt requests from the circuit board under test on the POD for each level. and a signal direction control switch for bidirectionally controlling the direction of signals only at specific interrupt terminals, and a predetermined one of the interrupt request signals from the circuit board under test is controlled by the interrupt control switch. A tri-state mode in which the signal from the switch is gated and output as is, and the remaining interrupt request signals are gated by the signal from the interrupt control switch and the signal direction is controlled by the signal direction control switch. An interrupt control circuit for a digital circuit testing device, characterized in that the interrupt control circuit is configured to output via a buffer.