JPH0232445A - Trouble condition detecting system for common bus interface - Google Patents

Abstract

PURPOSE:To instantaneously discriminate a troubled signal line, and to shorten a restoring time by providing a means, which automatically detects the trouble condition of a module common bus interface by means of a system control part, at an information processing system. CONSTITUTION:Diagnostic data from a diagnostic data sending means 1b in a system control part 1 are stored into a register 9, a register 12 becomes significant, and the data are returned from the register 9 through a selector 1, a driver 10 and a common bus 6 to the system control part 1. The system control part 1 receives them, and a diagnosing means 1c checks the correctness of the data. Thus, all modules to be checked successively sample the diagnostic data, return them to the system control part 1, the diagnosing means 1c in the system control part 1 compares and checks the diagnostic data and the returned data, discriminates the troubled line, and thus, the restoring time of the system can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention provides a common bus interface fault state detection method;
More specifically, the present invention relates to a method for inspecting a failure state of a common bus interface section of each module in a system in which a plurality of modules transfer data between modules via a common bus.

(Prior Art) In an information processing system in which multiple modules transfer data between modules via a common bus, when a failure occurs in the common bus interface section of a certain module, conventionally, maintenance personnel have created a program to reproduce the failure phenomenon. Inspections were performed by creating a module and measuring the waveform using an oscilloscope or logic analyzer to analyze which signal line of which module was faulty.

As far as the present inventors know, conventionally, there has been no known method for self-diagnosing the failure state of the common bus interface unit.

(Problem to be solved by the invention) However, the conventional inspection methods described above require troublesome preliminary preparations such as setting up measurement equipment such as an oscilloscope and logic analyzer, and creating programs to reproduce the phenomenon. is necessary. Another problem is that it is necessary to analyze which signal line of which module is faulty after measurement, and it takes a considerable amount of effort and time to identify the faulty module or line.

The present invention solves the above-mentioned problems of the conventional method, and allows the system to automatically self-diagnose the failure state of the common bus interface section of the modules that make up the system without labor, thereby reducing system repair time. The purpose of the present invention is to provide a common bus interface failure state detection method that can improve system maintainability by requiring only a short time.

(Means for Solving the Problems) The present invention provides an information processing system that includes a common bus, a plurality of modules that mutually transfer data via this common bus, and a system control unit that controls this system. A system common bus interface failure state detection method, comprising means (diagnostic data sending means) for sending diagnostic data for testing a common bus interface section of the module to the system control section onto the common bus; means (inspection instruction means) for instructing each of the modules to perform a test; each common bus interface section is provided with received data return means for returning the diagnostic data to the system control section after receiving the diagnostic data; This common bus interface failure state detection method is characterized in that the control unit is provided with a diagnostic means for determining the validity of the returned received data.

(Operation) The system control unit of the common bus interface failure state detection method of the present invention (hereinafter sometimes referred to as the method of the present invention) accepts common bus use requests from each module via individual bus use request lines. In addition to the normal control operation of controlling the setting of the bus usage right and granting the usage right of the common bus to a unique module via an individual bus usage permission line, it also detects a failure state of the common bus interface unit. control.

Further, when a failure occurs in the system, the system is set from normal mode to inspection mode. Next, the test instructing means sequentially grants each module the right to use the common bus, and at the same time sends diagnostic data for testing onto the common bus from the diagnostic data sending means. The module to be inspected samples the diagnostic data and returns the received data to the system control unit via the received data return means. The diagnostic means of the system control unit includes:
A fault condition is detected by comparing the transmitted diagnostic data and the returned received data.

As described above, in the method of the present invention, a faulty module and a faulty signal line are detected by performing simulated data transfer between the system control section and each module using diagnostic data.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of the configuration of an information processing system to which the present invention is applied. In the figure, 1 is a system control unit;
2. (i=1-n, same below) is a module, 31 is an individual bus use request line, 4° is an individual bus use permission line, 5
is a reset signal line, and 6 is a common bus. The system control unit 1 is provided with an examination instruction means 1a, a diagnostic data sending means 1b, and a diagnostic means IC. Further, each module 21 includes a module main body 2a and a common bus interface section 2b+, and the common bus interface section 2bI is further provided with received data return means 2c+.

The information processing system shown in FIG. 1 has two types of operation modes: (1) a normal mode in which normal data transfer is performed, and (2) a test mode in which a failure state of the common bus interface section is checked. The inspection mode is specified when the reset signal line 5 becomes significant, that is, when the system is started up or by an operator instruction on an operation panel (not shown). The operations (1) and (2) are transmitted from the system control unit 1 to all modules of the information processing system via the reset signal line 5 for initializing all modules. When switching to the inspection mode, the received data return means 2c+ is enabled. Below, (1), (2)
We will explain how this information processing system operates in this mode.

(1) Normal mode The system control unit 1 monitors the bus use request line 31, determines the priority of which signal is significant, and selects the common bus 6 for the only module. Grant usage rights. Modules that have been given the right to use the bus use the common bus 6 to transfer data.

(2) Inspection mode The system control unit 1 makes the reset signal line 5 valid, instructs all modules to initialize, and notifies them that they are in inspection mode. Furthermore, the system control unit 1 sends diagnostic data onto the common bus 6 from the diagnostic data sending means 1b, and also sends a significant signal from the inspection instruction means 1a to the corresponding module on the bus use permission line 4I.

When each module 2I learns from the reset signal line 5 that the information processing system has entered the test mode, data transfer between the modules is not performed, and the module 2I monitors the bus use permission line assigned to the own module. Then, the module whose assigned bus permission line becomes significant receives a sample of the diagnostic data sent out at the same time, and sends the same data back to the system control unit 1 by the received data return means 2c+. On the other hand, the system control unit 1 samples the returned received data on the common bus 6 in its diagnostic means IC, and compares the transmitted diagnostic data with the returned received data. in this way,
A faulty module and a faulty signal line are detected by causing the module to be tested to perform a simulated data transfer with the system control unit 1 and determining the validity of the data.

As a method for transmitting diagnostic data from the diagnostic data transmitting means 1b onto the common bus 6, for example, the signal line (m
How to select all patterns (2'''patterns); 1 out of m signal lines to be diagnosed
A method of assigning logic "1" to all signal lines in a pattern where only the book is set to logic "1" and all others are set to logic "O°" (
(m patterns); representative patterns include "all logic 1", "all logic O", and "0101...01".

There is a method of selecting four patterns such as "1010...10", but which method is selected is arbitrary.

Furthermore, since the information on the faulty module and fault signal line in this inspection is managed by the system control unit 1, it can be easily retrieved as needed.

FIG. 2 shows a simplified circuit diagram showing an example of the common bus interface section 2bl of the module under test 21. As shown in FIG.

In the figure, 4□, 5+, and 6+ are a bus use permission line, a mode signal line, and a common bus, as in FIG. Also, 7
is a receiver for the common bus 6; 8 is a timing flip-flop; 9 is a register for reception during data transfer and for receiving and transmitting diagnostic data during inspection mode; 10 is a common bus 6
driver, 11 is for normal mode (B side) and inspection mode (
A selector that is switched when switching to each side (A side), 1
2 is a register that holds that diagnostic data has been received in the inspection mode; 13 is a register that holds that the received data has been received in normal mode; and 14 is an internal circuit of the module main body 2a+. The received data return means 2c+ includes a register 9, a selector 1
1 and a register 12.

Next, the circuit operation shown in FIG. 2 will be explained separately for the normal mode and the test mode.

<1) Normal mode received data passes through the common bus 6, receiver 7, and flip-flop 8 and is stored in the register 9. At this time, since the register 13 becomes significant, the internal circuit 14 knows that data has been received in the normal mode, and transfers the data to the internal circuit 14.
Take in within 4.

Further, data is sent from the internal circuit 14 to the common bus 6 through the selector 11 and driver 10 connected to the B side.

(2) Inspection mode Diagnostic data from the diagnostic data sending means 1b of the system control unit 1 is stored in the register 9 as in the normal mode. At this time, since the register 12 becomes significant, the diagnostic data is sent back to the system control unit 1 from the register 9 through the selector 11 connected to the A side, the driver 10, and the common bus 6. The system control unit 1 receives the returned data and checks the validity of the received data in the diagnostic means 1c.

This test will be explained with reference to FIG. 3, which shows a time chart of the circuit of FIG. 2 in test mode. Third
In the figure, (a) is a clock signal, (b) is a bus use permission signal for the module under test 21, (C) is diagnostic data sent from the system control unit 1, and (d) is the module under test 2.
(e) is the reset signal. As can be seen from this time chart, the diagnostic data sending means 1b of the system control unit 1 transmits the bus use permission signal line 4I to the module 21 at time A on the clock signal (a).
is made significant, and diagnostic data is sent onto the common bus 6 at the same time. The module to be tested 21 stores the above diagnostic data at time B.
, and at the same time sends it back to the system control unit 1. The diagnostic means 1c of the system control unit 1 samples the data returned by the module to be inspected 21 at time C, and compares the transmitted diagnostic data with the returned data.
inspect. In the process of sequentially performing such a test on all modules, information regarding the faulty module and fault signal line can be obtained from the discrepancy between the diagnostic data and the returned data.

(Effects of the Invention) As described above, according to the present invention, since the information processing system is provided with means for the system control unit to automatically detect the failure state of the module common bus interface unit,
It is possible to instantly identify faulty modules and faulty signal lines in the system, and is expected to improve system maintainability by shortening system repair time.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram of an information processing system to which the present invention is applied, and FIG. 2 is a common bus interface section 2.
FIG. 3 is a time chart of the circuit shown in FIG. 2. 1... System control unit, 1a... Inspection instruction means, 1
b...Diagnostic data sending means, IC...Diagnostic means, 2
, (i=1-n)...Module, 2a+...Module body, 2br...Common bus interface section, 2c,...
... Received data return means, 31... Bus use request line, 41... Bus use permission line, 5... Reset signal line, 6... Common bus. Patent applicant Oki Electric Industry Co., Ltd. Time ABC ↓ ↓ ↓ (Logic 0: normal data transfer mode) Time chart in inspection mode of the circuit shown in Fig. 2 Fig. 3

Claims (1)

[Claims] A common bus interface failure state of an information processing system that includes a common bus, a system that includes a plurality of modules that mutually transfer data via the common bus, and a system control unit that controls this system. The detection method includes means for transmitting diagnostic data for testing a common bus interface section of the module onto the common bus, and means for instructing each module to perform the test, to the system control unit. and each common bus interface section is provided with received data return means for returning the diagnostic data to the system control section after receiving it, and the system control section is provided with a received data return means for determining the validity of the returned received data. 1. A common bus interface failure state detection method, characterized in that a diagnostic means is provided.