KR100208284B1 - Appatatus for testing i/o test brs interface board of subscriber in switching system - Google Patents

Abstract

The present invention relates to a test apparatus capable of checking whether a loop formed on an input / output test bus matching board is normally checked in order to actually measure a tip terminal or a ring terminal of an input / output test bus in an exchanger. To this end, the device comprises first and second in or out test relays; A first test relay; A second test relay; In the tip terminal test, supply power is supplied to the second test relay, the signal transmitted through the first test relay is received, in the ring terminal test, the supply power is supplied to the first test relay, and the second test relay is supplied. A relay unit driven to receive a signal transmitted through the unit; A latch for latching data received at the relay unit; And forming the respective loops during the tip terminal test and the ring terminal test by using the first and second in or out test relays and the first and second test relays, and controlling the operation of the relay unit and the latch. And a processor for analyzing the signal transmitted from the latch and determining whether the loop formed on the input / output test bus matching board is normal.

Description

Tester for subscriber I / O test bus matching board in exchange

The present invention relates to an input / output test bus interface board of a subscriber in an exchange, and more particularly to a test apparatus for checking an abnormality of a path formed on an input / output test bus matching board. It is about.

In the exchange, the subscriber's I / O test bus is a bus connected to the in-test relay and the out-test relay provided between the subscriber registration board and the subscriber line. When testing, it is connected to the in-test relay and out-test relay described above to provide a loop for testing the corresponding subscriber line in the actual measuring device.

In order to provide such a test loop, an I / O test bus (hereinafter referred to as an I / O test bus) matching board is provided between the I / O test bus and the actual measuring device.

FIG. 1 is a block diagram illustrating a relationship between a conventional I / O test bus matching board and a real measurement device, and includes an in-test relay (not shown) or an out test relay (not shown) located between a subscriber line and a subscriber matching board (not shown). This is the case where the Nth tip terminal (TIP N) and the ring terminal of the I / O test bus connected to the I / O test bus are connected.

That is, in the actual measurement of the Nth tip terminal, the I / O test bus registration board 100 is first and second in or out test relays 101 and 102 and the second test relay (by the processor 105). 104 to form a loop between the tip terminal of the test bus and the actual measurement device 110. Accordingly, the real measurement device 110 performs a real measurement on the tip terminal TIP N using a loop formed on the I / O test bus matching board 100.

In addition, in actual measurement of the N-th ring terminal, the I / O test bus matching board 100 is first and second in or out test relays 101 and 102 and the first test relay 104 by the processor 105. ) To form a loop between the ring terminal (RING N) of the corresponding test bus and the actual measurement device (110). Accordingly, the actual measuring device 110 performs a real measurement on the corresponding ring terminal RING N using a loop formed on the I / O test bus matching board 100.

However, when such a real measurement, the loop formed on the I / O test bus matching board 100 without checking whether the loop formed on the normal is abnormal, there was a problem that the actual measurement results are not accurate.

The present invention has been made to improve the above-described drawbacks, and is a test that can check whether the loop formed on the input / output test bus matching board to check the tip terminal or ring terminal of the input / output test bus in the exchanger. The purpose is to provide a device.

In order to achieve the above object, a test apparatus according to the present invention includes an input / output test for matching between a real measurement device for performing a real measurement on a tip terminal and a ring terminal of an input / output test bus provided in an exchanger. A bus matching board, comprising: a first and second in or out test relays each having a matrix structure and connected to a tip terminal and a ring terminal, respectively; A first test relay for forming a first in or out test relay and a pass connected to the tip terminal and the ring terminal, respectively, and a first test relay for forming a second in or out test relay and a pass during the ring terminal test; A second test relay for forming a pass with a second in or out test relay during a tip terminal test, and a second test relay for forming a pass with a first in or out test relay for a ring terminal test; In the tip terminal test, supply power is supplied to the second test relay, the signal transmitted through the first test relay is received, in the ring terminal test, the supply power is supplied to the first test relay, and the second test relay is supplied. A relay unit driven to receive a signal transmitted through the unit; A latch for latching data received at the relay unit; And forming the respective loops during the tip terminal test and the ring terminal test by using the first and second in or out test relays and the first and second test relays, and controlling the operation of the relay unit and the latch. And a processor for analyzing the signal transmitted from the latch and determining whether the loop formed on the input / output test bus matching board is normal.

1 is a block diagram showing a relationship between a conventional input / output test bus matching board and a real measurement device.

2 is a functional block diagram of an exchange having a test apparatus for an I / O test bus matching board according to the present invention.

* Explanation of symbols for main parts of the drawings

200: I / O test bus matching board 201: First in or out test relay

202: second in or out test relay

203: relay for first test 204: relay for second test

205: Processor (PP) 206: Relay

207: latch

The above and other objects and various advantages of the present invention will become apparent from the following description of the preferred embodiment.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a functional block diagram of an exchanger having a test apparatus for a subscriber's input / output test bus matching board according to the present invention, wherein the input / output test bus matching board 200 and the actual measurement apparatus provided with the test apparatus according to the present invention are shown in FIG. It consists of 110.

The input / output test bus matching board 200 includes the first and second in or out test relays 101 and 102 and the first and second test relays 103 and 104 as shown in FIG. 1 and the first test relay. In the relay section 201 and the relay section 201, which are composed of relays K0 and K1 connected to the ring test point connected to the 103 and the tip test point connected to the second test relay 103, respectively. The latch 202 connecting the input terminals I1 and I2 to the relays K0 and K1 provided, the first and second in-out test relays described above as shown in FIG. 1 according to the terminal to be tested. When the data is transmitted from the latch 202 by controlling the operations of the 101 and 102 and the first and second test relays 103 and 104, and also controlling the operations of the relay unit 201 and the latch 202 described above. By analyzing this, a processor for determining the presence or absence of abnormalities on the loops formed on the I / O test bus matching board 200 ( 203).

As can be seen from such a configuration, the test apparatus according to the present invention comprises the above-described relay unit 201, latch 202, and the processor 203 provided on the input / output test bus matching board 200, The above-described relay unit 201 and the latch 202 may be provided outside the input / output test bus matching board 200.

The operation of the input / output test bus matching board 200 having the test apparatus configured as described above is as follows.

That is, when testing the tip terminal of the input / output test bus at the request of the operator, the processor 203, as shown in FIG. 1, the first in or out test relay 101, the second in or out test relay ( 102 and the state of the relay of the second test relay 104 is controlled to form a loop for the tip terminal described above. At this time, the first and second in or out test relays 101 and 102 and the first and second test relays 103 and 104 have a matrix structure.

The processor 203 controls the relay unit 201 so that the relay K0 is connected to the a1 contact and the relay K1 is connected to the b2 contact. Accordingly, the input / output test bus matching board 200 has a relay K0 → a second test relay 104 → a second in or out test relay 102 → a first in or out centering on a tip terminal TIP N. A loop for transmitting a signal in the direction of the test relay 101 → the first test relay 103 → the relay K1 is formed.

Through the loop formed as described above, the relay K0 transmits a power of + 5V to the second test relay 104, and the relay K1 transmits a signal transmitted from the first test relay 103 to the latch 202. Transmit to I2 input terminal.

The latch 202 latches data applied to the I2 input terminal and then transmits the latched data to the processor 203 by being controlled by the processor 203. At this time, the data latched in the latch 202 becomes a voltage value.

The processor 203 determines that the currently formed loop is normal when the data transmitted from the latch 202 is + 5V. However, if the transmitted data is not + 5V, it is determined that the currently formed loop is abnormal.

On the other hand, when testing the ring terminal of the input / output test bus at the request of the operator, the processor 203 is the relay state of the first and second in or out test relays (101, 102) and the first test relay (103) Control to form a loop for the above-described ring terminal.

The processor 203 controls the relay unit 201 so that the relay K0 is connected to the a2 contact and the relay K1 is connected to the b1 contact. Accordingly, the input / output test bus matching board 200 includes a relay K1 → a first test relay 103 → a second in or out test relay 102 → a first in or out test relay 101 → a second. A test relay 104 forms a loop that transmits a signal in the direction of relay K0.

Through the loop formed as described above, the relay K1 transmits a + 5V power supply to the first test relay 103, and the relay K0 receives a signal transmitted from the second test relay 104 by the latch 202. Transmit to I1 input terminal.

The latch 202 latches data applied to the I1 input terminal and then transmits the latched data to the processor 203 by being controlled by the processor 203.

The processor 203 determines that the currently formed loop is normal when the data transmitted from the latch 202 is + 5V. However, if the transmitted data is not + 5V, it is determined that the currently formed loop is abnormal.

As described above, the present invention is caused by abnormally forming a loop formed on the I / O test bus matching board by testing whether the loop is formed on the I / O test bus matching board provided in the exchanger. There is an advantage that the operator can recognize the actual error.

Although the present invention has been described as the above-described embodiment, those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (2)

In the real measurement device 110 for real measurement of the tip terminal and the ring terminal of the input and output test bus provided in the exchanger and the input and output test bus matching board for matching between the input and output test bus, a matrix structure First and second in or out test relays 101 and 102 connected to the tip terminal and the ring terminal, respectively; In the tip terminal test, a pass is formed with the first in or out test relay 101, and in the ring terminal test, the first test for forming a pass with the second in or out test relay 102 is performed. Relay 103; A second test for forming a pass with the second in or out test relay 102 when the tip terminal test, the second test for forming a pass with the first in or out test relay 101 at the ring terminal test Relay 104; Supplying power to the second test relay 104 to the tip terminal tester, receiving a signal transmitted through the first test relay 103, and during the ring terminal test, the first test relay 103 A relay unit 201 driven to provide the power supply to the power supply) and to receive a signal transmitted through the second test relay 104; A latch 202 for latching data received by the relay unit 201; And loops according to the tip terminal test and the ring terminal test using the first and second in or out test relays 101 and 102 and the first and second test relays 103 and 104. And control the operation of the relay unit 201 and the latch 202 to analyze the signal transmitted from the latch 202, and the loop formed on the input / output test bus matching board 200. Tester for the input and output test bus matching board of the subscriber, characterized in that consisting of a processor 230 for determining whether or not normal. The method of claim 1, wherein the relay unit 201 transmits the power supply to the tip terminal tester to the second test relay 104, and is transmitted from the second test relay 104 during the ring terminal test. A first relay K0 for receiving a signal and transmitting the signal to one input terminal of the latch 202, and transmitting the supply power to the first test relay 103 during the ring terminal test, and during the tip terminal test, A test apparatus for an input / output test bus matching board of a subscriber, characterized in that it comprises a second relay (K1) for receiving a signal transmitted from the first test relay (103) and transmitting it to the other input terminal of the latch (202). .