KR19990000005A - Tester for subscriber I / O test bus matching board in exchange - Google Patents

Abstract

The present invention relates to a test apparatus capable of checking whether a loop formed on an input / output test bus matching board is normally checked in order to actually measure a tip terminal or a ring terminal of an input / output test bus in an exchanger. To this end, the device comprises first and second in or out test relays; A first test relay; A second test relay; In the tip terminal test, supply power is supplied to the second test relay, the signal transmitted through the first test relay is received, in the ring terminal test, the supply power is supplied to the first test relay, and the second test relay is supplied. A relay unit driven to receive a signal transmitted through the unit; A latch for latching data received at the relay unit; And forming the respective loops during the tip terminal test and the ring terminal test by using the first and second in or out test relays and the first and second test relays, and controlling the operation of the relay unit and the latch. And a processor for analyzing the signal transmitted from the latch and determining whether the loop formed on the input / output test bus matching board is normal.

Description

Tester for subscriber I / O test bus matching board in exchange

The present invention relates to an input / output test bus interface board of a subscriber in an exchange, and more particularly, to a test apparatus for checking an abnormality of a path formed on an input / output test bus matching board. It is about.

At the exchange, the subscriber's I / O test bus is a bus connected to the in-test relay and the out test relay provided between the subscriber registration board and the subscriber line. When testing, it is connected with the in-test relay and out-test relay described above to provide a loop for testing the corresponding subscriber line in the actual measuring device.

In order to provide such a test loop, an I / O test bus (hereinafter referred to as an I / O test bus) matching bus is provided between the I / O test bus and the actual measuring device.

1 is a block diagram illustrating a relationship between a conventional I / O test bus matching board and an actual measuring device, and includes an in-test relay (not shown) or an out test relay (not shown) located between a subscriber line and a subscriber matching board (not shown). This is the case where the Nth tip terminal (TIP N) and the ring (RING) terminal of the I / O test bus connected to the I / O test bus are connected.

That is, the actual measurement value for the Nth tip terminal, the I / O test bus matching board 100 is the first and second in or out test relays 101 and 102 and the second test relay 104 by the processor 105. Control to form a loop between the tip terminal of the test bus and the actual measurement device (110). Accordingly, the actual measuring device 110 performs a real measurement on the tip terminal TIP N using a loop formed on the I / O test bus matching board 100.

In addition, during actual measurement on the N-th ring terminal, the I / O test bus matching board 100 uses the processor 105 to check the first and second in or out test relays 101 and 102 and the first test relay 104. The control unit forms one loop between the ring terminal RING N of the corresponding test bus and the actual measurement device 110. Accordingly, the actual measuring device 110 performs a real measurement on the corresponding ring terminal RING N using a loop formed on the I / O test bus matching board 100.

However, when such a real measurement, the loop formed on the I / O test bus matching board 100 is made without the check for the normal ruler is formed, the actual measurement result was not accurate.

The present invention has been made to improve the above-described drawbacks, and is a test that can check whether the loop formed on the input / output test bus matching board to check the tip terminal or ring terminal of the input / output test bus in the exchanger. The purpose is to provide a device.

In order to achieve the above object, a test apparatus according to the present invention includes an input / output test for matching between a real measurement device for performing a real measurement on a tip terminal and a ring terminal of an input / output test bus provided in an exchanger. A bus matching board, comprising: a first and second in or out test relays each having a matrix structure and connected to a tip terminal and a ring terminal, respectively; A first test relay for forming a pass with the first in or out test relay during the tip terminal test, and a first test relay for forming a pass with the second in or out test relay for the ring terminal test; A second test relay for forming a pass with a second in or out test relay during a tip terminal test, and a second test relay for forming a pass with a first in or out test relay for a ring terminal test; In the tip terminal test, supply power is supplied to the second test relay, the signal transmitted through the first test relay is received, in the ring terminal test, the supply power is supplied to the first test relay, and the second test relay is supplied. A relay unit driven to receive a signal transmitted through the unit; A latch for latching data received at the relay unit; And using the first and second in or out test relays and the first and second test relays to form loops according to the tip terminal test and the ring terminal test, and to control the operation of the relay unit and the latch. And a processor for analyzing the signal transmitted from the latch and determining whether the loop formed on the input / output test bus matching board is normal.

1 is a block diagram illustrating a relationship between a conventional input / output test bus matching board and an actual measuring device.

2 is a functional block diagram of an exchanger having a test apparatus for an I / O test bus matching board according to the present invention.

* Description of the symbols for the main parts of the drawings *

200: I / O test bus registration board 201: Relay for first in or out test

202: relay for the second in or out test

203: first test relay 204: second test relay

205: Processor (PP) 206: Relay

207: Latch

The above and other objects and various advantages of the present invention will become apparent from the following description of the preferred embodiments.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a functional block diagram of an exchanger having a test apparatus for an I / O test bus matching board of a subscriber according to the present invention, and an input / output test bus matching board 200 having a test apparatus according to the present invention and an actual measurement apparatus. It consists of 110.

The input / output test bus matching board 200 includes the first and second in or out test relays 101 and 102 and the first and second test relays 103 and 104 as shown in FIG. 1, and the first test relay 103 is connected to the first test relay 103. Relays provided in the relay unit 201 and the relay unit 201, which are composed of relays R0 and K1 connected to the ring test point connected and the tip test point connected to the second test relay 103, respectively. Latches 202 connecting the input terminals I1 and I2 to the fields K0 and K1, the first and second in-out test relays 101 and 102 and the first and second in-out test relays as shown in FIG. It controls the operation of the first and second test relays 103 and 104, and also controls the operation of the relay unit 201 and the latch 202 described above, and analyzes the data when the data is transmitted from the latch 202 and analyzes the input / output test bus matching board ( To the processor 203 for determining whether there is an abnormality with respect to the loop shaped on the It is sex.

As can be seen from such a configuration, the test apparatus according to the present invention comprises the above-described relay unit 201, latch 202, and the processor 203 provided on the input / output test bus matching board 200, The above-described relay unit 201 and the latch 202 may be provided outside the input / output test bus matching board 200.

The operation of the input / output test bus matching board 200 having the test apparatus configured as described above is as follows.

That is, at the request of the operator, the tester for the tip terminal of the input / output test bus, the processor 203, the first in or out test relay 101, the second in or out test relay 102 as shown in FIG. And control the relay state of the second test relay 104 to form a loop for the above-described tip terminal. At this time, the first and second in or out test relays 101 and 102 and the first and second test relays 103 and 104 have a matrix structure.

The processor 203 controls the relay unit 201 so that the relay K0 is connected to the a1 contact and the relay K1 is connected to the b2 contact. Accordingly, the input / output test bus matching board 200 has a relay K0 → a second test relay 104 → a second in or out test relay 102 → a first easy or out centering on a tip terminal TIP N. A loop is formed to transmit a signal in a direction from the test relay 101 to the first test relay 103 to the lily K1.

Through the loop formed as described above, the relay K0 transmits a power of + 5V to the second test relay 104, and the relay K1 transmits a signal transmitted from the first test relay 103 to the latch 202. 12 It is transmitted to the input terminal.

The latch 202 latches data applied to the 12 input terminals and then transmits the latched data to the processor 203 by being controlled by the processor 203. At this time, the data latched in the latch 203 becomes a voltage value.

The processor 203 determines that the currently formed loop is normal when the data transmitted from the latch 202 is + 5V. However, if the transmitted data is not + 5V, it is determined that the currently formed loop is abnormal.

Meanwhile, at the request of the operator, when testing the ring terminal of the input / output test bus, the processor 203 controls the relay states of the first and second in or out test relays 101 and 102 and the first test relay 103. A loop for the above-described ring terminal is formed.

The processor 203 controls the relay unit 201 so that the relay K0 is connected to the a2 contact and the relay K1 is connected to the b1 contact. Accordingly, the input / output test bus matching board 200 is a relay (K1) → the first test relay (103) → the second in or out test relay (102) → the first in or out test relay (101) → first 2 A loop is formed to transmit a signal in the direction of the test relay 104 to the relay K0.

Through the loop formed as described above, the relay K1 transmits a + 5V power supply to the first test relay 103, and the relay K0 receives a signal transmitted from the second test relay 104 by the latch 202. Transmit to I1 input.

The latch 202 latches data applied to the I1 input terminal and then transmits the latched data to the processor 203 by being controlled by the processor 203.

The processor 203 determines that the currently formed loop is normal when the data transmitted from the latch 202 is + 5V. However, if the transmitted data is not + 5V, it is determined that the currently formed loop is abnormal.

As described above, the present invention is a real measurement caused by abnormally formed loop formed on the input / output test bus matching board by testing whether the loop formed on the input / output test bus matching board provided in the exchanger is abnormal. The error value has the advantage that the operator can recognize.

Although the present invention has been described as the above-described embodiment, those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (2)

An input / output test bus matching board for matching between an actual measuring device (110) for performing actual measurement on a tip terminal and a ring terminal of an input / output test bus provided in an exchanger; A first and second in or out test relays 102 and 102 having a matrix structure and connected to the tip terminal and the ring terminal, respectively; The first test relay to form a pass with the first in or out test relay 101 during the test of the tip terminal, and the first test relay to form a pass with the second in or out test relay 102 during the ring terminal test. (103); A second test for forming a pass with the second in or out test relay 102 when the tip terminal test, and a pass with the first in or out test relay 101 for the ring terminal test. Relay 104; Supplying power to the second test relay 104 at the tip terminal test, receiving a signal transmitted through the first test relay 103, and at the ring terminal test, the first test relay ( A relay unit 201 configured to provide the supply power to 103 and receive a signal transmitted through the second test relay 104; A latch 202 for latching data received by the relay unit 201; And The first and second in or out test relays 101 and 102 and the first and second test relays 103 and 104 are controlled to form loops for the tip terminal test and the ring terminal test. Controlling the operation of the relay unit 201 and the latch 202 to analyze the signal transmitted from the latch 202, and determine whether the loop formed on the input / output test bus matching board 200 is normal. Tester for the input and output test bus matching board of the subscriber, characterized in that the processor 230 for. The method of claim 1, The relay unit 201 transmits the supply power to the second test relay 104 during the tip terminal test, and receives the signal transmitted from the second test relay 104 during the ring terminal test to receive the latch. A first relay K0 for transmitting to the input / output input terminal of 202; The power supply is transmitted to the first test relay 103 during the ring terminal test, and the other terminal of the latch 202 is received by receiving a signal transmitted from the first test relay 103 during the tip terminal test. Tester for the input and output test bus matching board of the subscriber, characterized in that consisting of a second relay (K1) for transmitting to.