GB2144228A - Digital pin electronics module for computerized automatic diagnostic testing systems - Google Patents

Abstract

A Digital Pin Electronics Module (DPEM) (16) which includes a digital word generator 118) and a controller (17) minimizes the role of a host computer (11) of an automatic diagnostic testing system in the testing of complex digital circuits (10). The module is capable of communicating with the host computer (11) through a high level language, and performing the entire GO/NO GO testing of UUTs (10) in response to general commands received from the host. The module can place a UUT in a known state prior to its actual testing, and mask out irrelevant response data from a UUT to simplify the host's task of analyzing the failure of a unit. The module can also detect faults in its driver/receiver circuits down to the board level. <IMAGE>

Description

SPECIFICATION Digital pin electronics module for computerized automatic diagnostic testing systems Background of the invention The present invention relates to the field of computerized automatic diagnostic testing systems for the testing of electrical circuits, and more particularly, to an improved microcomputer controlled digital word generator for use in such systems having several important advantages over digital word generators previously in use.

Computerized automatic diagnostic testing systems are used to test many types of electrical circuits. Generally, such systems operate by automatically connecting the circuits to one or more electric- al stimulus and measurement devices used in the testing process. In the test mode stimulus and response signals are conducted to and received from the terminals of a unit under test (UUT) under program control of a host computer. Thereafter, the response of the UUT is compared to a predicted response on a GO/NO GO basis. If the unit's output or response matches the predicted response, it is passed. Similarly, if the predicted response is not obtained, the unit is failed and the system's host computer may proceed to effect a different operation to isolate the particular fault in the unit. In this way the electrical circuits are tested for defects.

Automatic testing systems generally use a variety of stimulus and measurement devices to test a variety of UUTs. One type of device used to test digital circuits is a digital word generator, a device capable of what is known to those skilled in the art as parallel testing, i.e., the simultaneous transmission of a number of electrical pulses or bits (i.e., a digital word) to certain pins of a UUT and the generally simultaneous measurement and logic analysis of the response emitted from other pins of the UUT. In operation, such devices usually generate the control and data signals necessary to test a specific UUT in direct response to detailed commands from a host computer.Testing typically consists of stimulating certain pins of the UUT with a series of binary test patterns, collecting corresponding binary response patterns from other pins of the UUT; and comparing the response patterns with predicted binary response patterns on a GO/NO GO basis. if the comparison fails, an analysis of the result is usually done by the host computer to isolate any faults in the unit.

Often, the testing of a UUT will require that it first be placed in a known state. Similarly, there may be instances where a portion of the UUT output or response need not be considered in determining whether or not the unit is defective. In this latter instance, the "don't care" portion of the comparison result is masked out so that it is not analyzed. Prior to the present invention, these functions were typically carried out by the host computer under software control. However, it has now been recognized that they could be performed more quickly and efficiently if they were performed by the digital word generator itself.

The effectiveness of any diagnostic testing system is measured by the thoroughness with which a given unit is tested. To ensure that every type of UUT is thoroughly tested so that an acceptable fault detection rate (between 75 and 95%) is achieved test systems invariably require tailored test procedures using a variety of test patterns for each type of UUT.

Where a digital word generator performs its functions in direct response to detailed commands from a host computer, a large amount of valuable host computer time must be used for proper testing to be done. It has now been recognized that this time could be reduced to allow the host computer to be used for other tasks if the digital word generator could carry out testing procedures with less supervision from the host computer.

For a user to be relatively confident that a circuit has been properly tested, the automatic diagnostic testing system, and more particularly the digital word generator itself, should be capable of being tested. Prior to this invention, a digital word generator was often tested through the host computer as a unit. Since this type of testing requires the use of valuable host computertime, and since a digital word generator can cease to function due to a fault on any one of a number of driver/receiver boards used to stimulate a UUT and measure its response, it has now been recognized that it is desirable for a digital word generator be able to self-diagnose faults in its driver/receiver circuits to the board level.

It is therefore, a general object of the present invention, to overcome the cited limitations present in devices of this type by providing an improved digital word generator having all of the desirable abilities noted above.

In addition, a particular object of the present invention is to provide an improved digital word generator capable of masking out "don't care" response signals so that the masking function need not be carried out by a host computer.

It is also a particular object of the present invention to provide an improved digital word generator that is capable of placing a UUT in a known state prior to the testing thereof.

Another object of the present invention is to provide an improved digital word generator having a self-test capability that allows it to diagnose drive/ receiver circuit faults to the board level.

A further object of the present invention is to provide a digital word generator capable of communicating on a higher level with a high level host computer so that the testing of UUTs is performed more independently of the host computer.

Summary of the invention According to the present invention there is a provided an improved digital word generator, referred to as a Digital Pin Electronics Module (DPEM), which minimizes the role of a host computer of an automatic diagnostic testing system in the testing of complex digital circuits. The module is capable of communicating with the host computer through a high level language, and performing the entire GO/NO GO testing of UUTs in response to general commands received from the host. The module can place a UUT in a known state prior to its actual testing, and mask out irrelevant response data from a UUT to simplify the host's task of analyzing the failure of a unit. The module can also detect faults in its driver/receiver circuits down to the board level.

The Digital Pin Electronics Module ofthe present invention is comprised of three major subassemblies: a microprocessor-based controller, a digital word generator module, and a power supply module.

The controller serves as a communications link between the host computer and the digital word generator. The host computer is used to develop individual test programs for each type of UUT. When a a particular program is executed, it is translated into CIIL (Control Interface Intermediate Language) commands and binary test data, and transmitted in ASCII code to the controller. The controller accepts and decodes the ClIL commands and data, and converts them into detailed functional and data commands that are used to control the performance of the digital word generator module. The functional and data commands define the detailed operations to be performed by the digital word generator module to insure that it thoroughly tests a selected UUT.Such operations include programming certain digital word generator channels as drivers, and others as receivers, and performing test sequences that include stimulating a UUT with a series of test patterns, comparing the UUT response with expected data patterns, masking out irrelevant data and transmitting comparison results to the host computer for further analysis. The controller's ability to interpret the CIIL commands and data and generate the functional and data commands for UUT testing relieves the host computer of this burden, the host to dedicate its time to more important tasks.

In the test mode the digital word generator module typically transmits test data or patterns to a UUT, collects the output or response patterns of the UUT and compares them with a pre-generated expected data pattern stored in a RAM memory located within the generator module. Where the UUT is to be initially placed in a known state priorto testing, the RAM memory is programmed with a specific response pattern corresponding to the known state. The UUT is then massaged with stimulus data, and its output monitored until it matches the stored pattern, indicating that the unit is in the known state.

Where a UUT produces an incorrect response requiring further analysis by the host computer, and a masking function is to be used, a mask pattern is stored in the RAM memory. The mask is used to mask out "don't care" portions of the error data to be transmitted to the host by AND'ing the mask pattern with the error data prior to such data being sent to the host computer.

Locating the above functions within the Digital Pin Electronics Module relieves the host computer of the burden of carrying them out under program control.

Besides allowing the host to perform more important tasks, having these functions performed within the DPEM reduces the time necessary to perform this aspect of the testing process.

The ability to test the driverareceiver boards of the digital word generator module resides in the firmware of the microprocessor-based controller and the hardware of the generator module. This test checks all driver/receiver boards within the generator module and provides status outputs to the host computer. If any of the boards are defective, the controller performs the necessary diagnostics to pinpoint any failures to the circuit board level.

Description of the drawing Figure 1 shows a block diagram of a MATE computerized automatic diagnostic test system incorporating the DPEM.

Figure 2 shows a block diagram of the digital word generator module of the DPEM.

Figures 3a and 3b show a block diagram of the controller of the DPEM.

Figure 4 shows a flow chart of a program used by the controller to carry out IEEE 488 bus communication functions.

Figure 5 shows a block diagram of a circuit used to carry out the masking and stop-on-match functions.

Figure 6 shows a flow chart of the DWG Test Failure Analysis routine.

Detailed description of the preferred embodiments Figure 1 shows a MATE (ModularAutomaticTest Equipment) System, a computerized automatic diagnostic test system of the type disclosed in U.S.

Patent No. 3,854,125, which may be used to test a variety of electrical circuits.

In the MATE System shown in Figure 1, overall testing of a circuit or unit under test (UUT) 10 is controlled by a high level host computer 11. Depend- ing on the type of UUT and the type of testing to be done, the host computer selects one or more of the sti m u I ilm easu rem ent instruments 12 to stimulate the UUT and measure its response. The stimuli measurement instruments are linked to the host computerthrough a standard IEEE 488 bus 13, and to the UTT through a mux interface assembly 14 of the type disclosed in U.S. Patent No. 3,922,537. The UUT is connected to this assembly through a connector referred to as an interface test adaptor 15.

The Digital Pin Electronics Module of the present invention, which is shown in Figure 1 as stimulil measurement instrument 16, is an improved digital word generator of the type disclosed in U.S. Patent Nos. 3,832,535 and 4,102,491. Like these devices its function is to provide the means by which a host computer such as computer 11 can test, analyze and evaluate complex digital circuits.

The three major sub-modules of the DPEM include a microprocessor-based controller 17, a digital word generator (DWG) module 18 and a power supply module (not shown). The digital word generator module is that part of the DPEM that actually stimulates a unit under test, measures its response and determines whether or not the unit is defective on a GO/NO GO basis. The controller serves as a communications link between the host computer and the digital word generator. Under normal opera tion the controller sends data to the DWG over an interface bus 19, along with commands telling the DWG what to do with the data. The DWG then conducts the data to UUT 10 by means of interface assembly 14 and interface test adapter 15, and waits a programmed amount of time beforerit measures the response of the UUT.DWG 18 then compares the UUT's response with pre-generated predicted data and sends the result to the controller for analysis over interface bus 19.

The digital word generator module is shown in greater detail in Figure 2. As can be seen therein, the preferred embodiment of the DWG includes a maximum of twenty essentially identical data driver boards 21, each of which contains 12 channels or pins 22 which are programmed to be either a high speed digital driver or a high speed digital receiver.

Since each of the data driver boards and the channels contained thereon are identical, only the details of board number 1 and pin number 1 are shown.

The controller is shown in greater detail in Figures 3A and 3B. The heart of the controller is the 80136 microcomputer board 23 shown in Figure 3A. This microcomputer is manufactured by Intel Corporation. Its central processing unit is an intel 80/86-2 microprocessor 24.

Figure 3B is a block diagram of typical logic circuits used by the controller to perform such functions as generating and distributing clock signals for conducting data to and receiving data from a UUT, channeling commands and data to the various data driver boards and receiving data therefrom.

For each type of electrical circuit tested by the system shown in Figure ia a separate test program is developed. This insures that the system will thoroughly exercise each UUT so as to achieve a desirable fault detection rate. The test program is developed on host computer 11 using a standard MATE language called ATLAS, which will be recognized by those skilled in the art as being a high level language commonly used in computerized automatic diagnostic testing systems for this purpose.

During the execution of a compiled test program, the program is converted into CIIL commands and binary test data by a bus controller/translator 25 (Figure 1) which transmits the commands and test data in ASCII format to the DPEM 16 over bus 13. The CIIL language is a high level language which will also be recognized by those skilled in the art as a language commonly used in computerized automatic diagnostic testing systems of the MATE type.

Controller 17 accepts and decodes the CIIL commands and binary test information transmitted from the host computer and converts this information into detailed functional and data commands to control the operation of digital word generator module 18.

The controller also receives error data over bus 19 from the DWG and transmits this data over bus 13 to the host computer for further analysis.

The IEEE 488 bus interface functions are implemented in the DPEM in both hardware and firmware. As seen in Figure 3A, the hardware includes a general purpose interface bus multimodule board 26 and IEEE address logic 27. Multimodule board 26 and IEEE address logic 27 are standard circuits that provide the necessary talker/ listener and sourcelacceptor handshake capabilities required to make controller 17 compatible with IEEE/488 bus 13. This hardware handshake logic implements the 488 source and acceptor handshake function, generates interrupts from 488 status and decodes 488 functions received on bus 13. The hardware also decodes commands received from the firmware.

The 488 firmware is stored in a ROM circuit 28 located on microcomputer board 23. This circuit includes I/O buffers seen by the firmware as memory ports which allow the firmware to monitor, and set and reset 488 control lines, read and write data, and respond to request from a user. A flow chart representing the program stored in the firmware is shown in Figure 4. It represents a software driver program which includes a total of seven software modules (routines) for carrying out various 488 functions.

INITIAL module 30 performs an initialization routine to initialize 488 bus status and allow a new status to occur under interrupt control. Once initiaiization is complete, ERROR module 31 reviews the configuration of the DPEM to ensure that it is configured as a talkerilistener in a non-extended address mode. If an invalid configuration exists an error flag is set. If the configuration is correct the routine falls through to the unsolicited interrupt (UNSOL) module 32.

UNSOL routine 32 checks for unsolicited interrupts. If it finds that an unanticipated bit has been set, the program reads 488 bus status and branches back to the beginning of the driver program, otherwise the routine proceeds to a command error (CMD ERR) routine 33.

CMD ERR 33 reviews CIIL commands received from host computer 11. If a received command is invalid the routine sets the interrupt status to denote that an unidentified command has been received, reads the corresponding 488 response and branches back to the beginning of the driver program. If a valid command is received the program proceeds to UNKNOWN module 34.

Routine 34 checks for an unknown operation, identification or interrupt. If one of these three conditions exists, or an I/O (command) buffer is in the execution state, the program stores the command and branches back to the beginning of the driver program. If none of the above conditions exists, the program proceeds to IDLE routine 35.

IDLE routine 35 checks for an Unlisten or Untalk condition, looping in idle state until a change in operation status occurs. The routine holds back further execution until operation status is ready for execution. During execution the routine branches to a send/receive I/O command buffer (SEND/REC IOCB) routine 36 which controls data inputs and outputs through the I/O command buffer. This data includes CIIL commands and data from host compu ter 11.

The CllL commands and data are passed to microprocessor 24 over a general purpose interface bus (not shown) located on multi-module board 26 and over an on-board local bus 39 of microcomputer 23 (Figure 3a). The GPIB is an extension of local bus 39. Once microprocessor 24 receives the CIVIL commands and binary test data from host computer 11, it converts a portion of these commands and data into information which is distributed to the clock generator, the references voltage and channeling and decoding logic circuits shown in Figure 3b. These circuits provide the signals necessary to control the operation of DWG module 18.

As indicated previously, these signals are in the form of functional and data commands which cause the DWG to carry out specific operations such as inputting stimulus patterns to a unit under test, comparing the response of the unit under test with expected patterns, masking out irrelevant data and transmitting the results to controller 17. The actual functional and data commands necessary to carry out these operations can be voluminous. For exampie, 213 microprocessor I/O instructions are required for microprocessor 24 to carry out these operations alone.Thus, the configuration of the present invention is an improvement over the prior art because these functional and data commands, which were originally generated by a host computer utilizing large amounts of valuable computer time, are now generated by the DPEM, allowing host computer, more time to perform other, more important tasks. in addition, this portion of the testing process is now performed at a faster rate.

The test data patterns, expected data patterns and comparison results used and obtained in the digital testing are temporarily stored in the DWG. Each data driver board of the DWG has a data RAM 40 and an error RAM 41 for this purpose for each of its 12 pins or channels. Each RAM is 4,096 bits deep, and each is separately addressed. Data RAM 40 is accessed through a driver memory address control 42, while error RAM 41 is accessed through a receiver memory address control 43. This allows separately controlled timing of the output and input functions.

Where a pin, such as pin 1, for example, is programmed as a high speed driver, its data memory 40 is first loaded with test data which is used to stimulate UUT 10. This data is sent to data RAM 40 by controller 17 over a Read/Write Data portion 44 of an 110 interface bus 45 interconnecting controller 17 and generator module 18. It is sequenced into RAM 40 under the control of a driver clock signal 46, which sequences driver memory address control 42. Clock signal 46 is generated by Dual Channel Clock/Delay Generator 91 board 47, and may derive either from a Driver Clock 41 signal 48 or a Driver Clock a2 signal 49, depending on whether the particular pin is part of a lower group of sixty pins or an upper group of sixty flus.

During the actual stimultion of UUT 10, the stored test data is sequenced out of RAM 40 at a maximum rate of 10MHz underthe control of driver clock signal 46, which again sequences driver memory address control 42. The data is then passed through a buffer latch 50, also controlled by clock signal 46, to a driver 51. From driver 51 the test data is driven through a driver select relay 52, a channel isolation relay 53 and pin number 1 to UUT 10.

Where a pin, such as pin 1, is programmed as a high speed receiver, data RAM 40 is loaded with expected data predicted to match the response of the UUT, rather than test data. Once the UUT 10 has been stimulated with test data from other pins programmed as driver pins, its response or output data is channeled through the various receiver pins, including (in this example) pin 1, where a receiver 54 receives and passes the data to an error comparator 55. Comparator 55 accepts the data under the control of a receiver clock signal 56 generated by Dual channel Clock/Delay Generator #2 board 57, and compares it bit by bit against the expected data stored in data RAM 40. If the comparison disagrees a pattern of exceptions, called the error data, is generated and clocked into receiver error memory 41 by receiver clock signal 56 for storage.Like clock signal 46, receiver clock signal 56 may derive from either a Receiver Clock #1 signal 58 or a Receiver Clock #2 signal 59, depending on whether the particular pin is part of a lower group of sixty pins or an upper group of sixty pins.

The generation of any error data causes an error flag to be raised in error flag circuit 60. If further analysis is to be done, the error data is read out of memory 41 and sent to controller 17 over Read/Write Data portion 44 of I/O interface bus 45. Subsequently, this data is transmitted over bus 13 by controller 17 to host computer 11 for further analysis and isolation of any faults that may exist in the UUT.

Often, a portion of the error data need not be considered by the host computer in its fault analysis.

The DPEM masks out this "don't care" portion of the error data by using a mask pattern stored in the upper half of the data RAM 40 of each pin programmed as a receiver. Controller 17 generates an appropriate functional command to perform a "read masked error", causing the most significant bit of the address lines from address control 42 to data RAM 40 to be overridden so that the masked data can be written into and read from the upper half thereof. Thus, a total of 2,048 bits of memory are available for each pin to store the masked data patterns used in the masking function.

Referring now to Figure 5, during the execution of the masking function the contents of data RAM 40 and error RAM 41 are sequenced out simultaneously, bit by bit, to a one-of-four data MUX 65 and a one-of-four error MUX 66, respectively. Each channel has two one-of-four MUX'es corresponding to MUX'es 65 and 66, which can be totally disabled, or selected to pass data to controller 17. The data and error MUX outputs from the twelve channels of each data driver board 21 are AND'ed together through AND gates 67 and 68, respectively and buffered with open collector drivers 69 and 70, respectively. The outputs of these drivers are connected to MUX DATA and MUX ERROR lines 71 and 72, respectively, which pass over 110 interface bus 45. The MUX DATA line is a wire OR'ed line which allows data from the various data RAMs to be transmitted to the DWG controller, while the MUX ERROR line is a wire OR'ed line which allows data from the error RAMs to be transmitted to the DWG controller. MUX DATA line 71 and MUX ERROR line 72 are then AND'ed together in controller 17 by an AND gate 73 which performs the actual masking of the error data. A masked error data signal 74 is then passed by controller 17 to host computer 11 for further fault analysis.

Through this arrangement the masking function is performed more quickly and efficiently because the host need only consider that portion of the error data that is useful for fault analysis. Thus, the burden of the host computer is reduced, allowing it more time to perform other functions.

Where it is desirable or necessary to first place a UUT in a known state prior to testing, the DPEM performs a stop-on-match operation. In this mode of operation each of the data RAMS 40 corresponding to those pins programmed as receivers are program med to store a portion of a specific expected data pattern corresponding to the output of the UUT when it is in the known state. The UUT is then massaged using test data from those pins program med as drivers until a match between the output of the UUT and the specific expected data pattern is attained. Referring to pin 1 by way of example, output data is received through pin 1 and isolation relay 53, and passed to receiver 54.This output data is then presented by the output of receiver 54 to comparator 55 which accepts and compares this data under the control of receiver clock signal 56 bit by bit with the expected data stored in memory 40.

The expected data stored in memory 40 is presented to comparator 55 under the control of driver clock signal 46. The resulting error data is stored in error RAM 41 and sequenced under control of receiver clock signal 56 to ERROR MUX 66 which is enabled to pass this data. The output of ERROR MUX 66 is AND'ed with the outputs of the selected ERROR MUX'es of pins 2 through 12 of the driver board 1 by AND gate 68 and buffered through open collector driver 70 to MUX ERROR line 72. The MUX ERROR signal passing over this line is then routed over I/O interface bus 45 to driver clock and receiver clock boards 47 and 57 in controller 17.Because MUX ERROR line 72 is wire OR'ed with the MUX ERROR lines of the other cards of the DWG, and the corresponding drivers 70 use active high logic, only when the output data of the UUT measured by the receiver pins matches the expected data stored in the corresponding data RAMS for such pins can the MUX ERROR line go high. When this change of state occurs, the driver and receiver clocks thereon are reset, and therefore, stopped. The UUT is then held in a known state, readyfortesting.

To ensure the reliability of testing results, the Digital Pin Electronics Module is capable of testing the operation of its data driver boards 21 to deter nline which, if any, are not functioning. Under this mode of operation, each channel 22 of each board 21 is tested to ensure that it is operational.

Referring to pin 1 by way of example, controller 17 instructs digital word generator module 16 to open channel isolation relay 53 to isolate the channel under test from other components in the automatic testing system. Module 16 is also instructed to close relays 52 and 54 to connect the output of driver 51 to the input of receiver 54. A test pattern is then loaded into a portion of data RAM 40 by means of Read/ Write Data bus 44. Also loaded into data RAM 40 is an expected data pattern which matches the test pattern previously stored.

During operation of the self-test function, the test data pattern is read out of data RAM 40 under the control of driver clock signal 46 to buffer latch 50 and driver 51. Once the signal is output by driver 51 relay 52 routes the signal to the input of receiver 54. The signal is then passed to error comparator 55 where it is compared on a bit-by-bit basis under the control of receiver clock signal 56 with the expected data pattern previously stored in data RAM 40.

If the channel under test is operating properly, no exceptions to this comparison should occur, and the channel is deemed to be operating properly. In contrast, if there are exceptions to this comparison, error data is generated which is stored in error RAM 41. An error flag is then raised by error flag circuit 60, indicating that the channel under test is not functioning properly. This procedure is carried out for all channels under test.

Where controller 17 detects one or more data driver board failures, a DWG failure analysis routine stored in ROM 28 of microcomputer board 23 is then executed by microprocessor 24 to analyze which channels under test, ifany, have failed. A flow chart of this failure analysis routine is shown in Figure 6.

Since there are a number of reasons why one or more data driver boards 22 would fail, the DWG failure analysis routine tests for six different types of failures. The first condition tested at step 80 is whether or not all pins have failed. If all the pins have failed, then the routine branches to step 81, theIST DACB (internal self-test digital to analog converters and controller) test, to determine whether or not any of the DACS, which provide the threshold voltages for the DWG drivers and receivers, are responsible for the failures. If the DACS boards are responsible, the microcomputer will indicate that they have failed, and stop the internal self test.

If all the pins have not failed, then the routine checks to determine whether the failed pins are in certain groupings. For example, in steps 82 and 83 the routine checks to see if all the failed pins are within the same group of sub-group, respectively, to determine if there is a problem in the DWG pin addressing circuitry. If either condition proves to be true, then microprocessor 24 indicates that the pin addressing circuitry located on the Data Distribution Burst Counter Logic board 84 (Figure 3b) has failed.

If neither of these conditions proves to be true, the routine then checks at step 85 whether pins 1-48 have failed and whether pins 49-120 have passed. If so, microprocessor 24 declares that there is a failure on the DACS board and stops the internal self-test because the DAC driver voltage levels are provided only for pins 1-48 (step 86).

Assuming that this condition is not true, the program then tests at steps 87 and 88, respectively, whether pins 1-60 have failed and pins 61-120 have passed, or vice versa. Since pins 1-60 use clock #1, if one set of these pins fail and one set passes, then the clock board controlling the set of pins determined to have failed is declared bad (steps 89 or 90).

At step 91 the program checks whether all pins on a single DWG board have failed. If so, microproces sor 24 indicates which particular DWG has failed (step 92).

Finally, at step 93, the program checks whether pins on less than four DWG cards have failed. If so, then microprocessor 24 declares the DWG cards on which the pins have failed as being bad at step 94.

Otherwise the microprocessor declares the DACS boards to be faulty, (step 95), at which point the internal self-test is stopped.

The above-described embodiment of the invention is illustrative, and modifications thereof may occur to those skilled in the art. The invention is not limited to the embodiment disclosed herein, but is to be limited only as defined in by the appended claims.

Claims (20)

1. An improved digital word generator comprising means for receiving and for applying to a plurality of input terminals of a unit under test binary test data from a host computer, means for receiving and for comparing with binary expected data received from the host computer binary response data from a plurality of output terminals of the unit under test and means for sending comparison results to the host computer, wherein the improvement comprises memory means for storing binary masked data and means for using said binary masked data to mask out portions of the comparison results prior to the comparison results being sent to the host computer.

2. An improved digital word generator as recited in Claim 1 wherein the improvement further comprises means for routing output signals from the applying means to the receiving means so that output signals from the receiving means when compared by the comparing means with binary self-test data input to the applying means matches said self-test data when the applying means and the receiving means are properly operating, and means for identifying the location of faults in the applying and receiving means to the board level when errors occur in said comparison.

3. An improved digital word generator as recited in Claim 2 wherein the improvement further comprises memory means for storing a predetermined binary expected data pattern corresponding to a known state of the unit under test and means for stopping the application binary test data to the unit under test when a binary response data pattern of the unit under test matches said pre-determined binary expected data pattern.

4. An improved digital word generator comprising means for receiving and for applying to a plurality of input terminals of a unit under test binary test data from a host computer, means for receiving and for comparing with binary expected data received from the host computer binary response data from a plurality of output terminals of the unit under test and means for sending comparison results to the host computer, wherein the improvement comprises means for routing output signals from the applying means to the receiving means so that output signals from the receiving means when compared by the comparing means with binary self-test data input to the applying means matches said self-test data when the applying means and the receiving means are properly operating, and means for identifying the location of faults in the applying and receiving means to the board level when errors occur in said comparison.

5. An improved digital word generator as recited in Claim 4 wherein the improvement further comprises memory means for storing binary masked data and means for using said binary masked data to mask out portions of the comparison results prior to the comparison results being sent to the host computer.

6. An improved digital word generator as recited in Claim 5 wherein the improvement further comprises memory means for storing a pre-determined binary expected data pattern corresponding to a known state of the unit under test and means for stopping the application of binary test data to the unit under test and means for stopping the application of binary test data to the unit under test when a binary response data pattern of the unit under test matches said pre-determined binary expected data pattern.

7. An improved digital word generator comprising means for receiving and for applying to a plurality of input terminals of a unit under test binary test data from a host computer, means for receiving and for comparing with binary expected data received from the host computer binary response data from a plurality of output terminals of the unit under test and means for sending comparison results to the host computer, wherein the improvement comprises memory means for storing a pre-determined binary expected data pattern corresponding to a known state of the unit under test and means for stopping the application of binary test data to the unit under test when a binary response data pattern of the unit under test matches said pre-determined binary expected data pattern.

8. An improved digital word generator as recited in Claim 7 wherein the improvement further comprises memory means for storing binary masked data and means for using said binary masked data to mask out portions of the comparison results prior to the comparison results being sent to the host computer.

9. An improved digital word generator as recited in Claim 8 wherein the improvement further comprises means for routing output signals from the applying means to the receiving means so that output signals from the receiving means when compared by the comparing means with binary self-test data input to the applying means matches said self-test data when the applying means and the receiving means are properly operating, and means for identifying the location of faults in the applying and receiving means to the board level when errors occur in said comparison.

10. An improved digital word generator as recited in Claims 3,6 or 9 wherein the improvement further comprises means for receiving and interpreting high level language commands from the host computer to control the operation of the digital word generator and said masking, routing and stopping means.

11. An improved digital word generator as recited in Claim 10 wherein said memory means for storing binary masked data is random access memory and wherein said means for using said binary masked data to mask out portions of the comparison results is an AND logic circuit connected to said memory means and to said means for sending comparison results to the host computer.

12. An improved digital word generator as recited in Claim 11 wherein said stopping means is a reset circuit for stopping the operation of clock circuits controlling the operation of the applying means, comparing means and receiving means.

13. An improved digital word generator as recited in Claim 12 wherein said routing means is a relay connected between each output of the applying means and each input of the receiving means.

14. An improved digital word generator as recited in Claim 13 wherein said fault identifying means and said means for receiving and interpreting commands from the host computer is a microcomputer.

15. An improved digital word generator comprising means for receiving and for applying to a plurality of input terminals of a unit under test binary test data from a host computer, means for receiving and for comparing with binary expected data received from the host computer binary response data from a plurality of output terminals of the unit under test and means for sending comparison results to the host computer, wherein the improvement comprises means for masking out portions of the comparison result prior to the comparison results being sent to the host computer, means for testing the operation of the applying means and receiving means and for identifying the location of faults therein to the board level, means for stopping the application of binary test data to the unit under test when the unit under test is in a known state and means for receiving and interpreting high level language commands from the host computer and for controlling the operation of the digital word generator and said masking means, testing means and stopping means in response to said commands.

16. An improved digital word generator as recited in Claim 15 wherein said masking means comprises a plurality of memory circuits for storing binary masked data and an AND logic circuit connected to said memory circuits and said means for sending comparison results to the host computer, said AND logic circuit using said binary masked data to mask out portions of the comparison results.

17. An improved digital word generator as recited in Claim 15 wherein said means fortesting the operation of the applying means and the receiving means comprises means for routing output signals from the applying means to the receiving means so that output signals from the receiving means when compared by the comparing means with binary self-test data input to the applying means matches said self-test data when the applying means and the receiving means are properly operating.

18. An improved digital word generator as recited in Claim 17 wherein said routing means is a relay connected between each output of the applying means and each input of the receiving means.

19. An improved digital word generator as recited in Claim 15 wherein said stopping means is a reset circuit for stopping the operation of clock circuits controlling the operation of the applying and receiving means.

20. An improved digital word generator as recited in Claim 15 wherein said means for identifying the location of faults in the applying and receiving means and said means for receiving and interpreting high level language commands from the host computer is a microcomputer.