WO1984002412A1 - High speed testing of complex circuits - Google Patents

Abstract

Improved apparatus and process for testing a variety of electronic components, such as printed circuit boards (101, figure 3), which have a large number of potential circuit paths. The apparatus of the invention is characterized by a versatile searching sequence which achieves a surprising combination of search speed and efficiency and hardware economy. Advantages embodiments of the invention enable multiple test stations (32, 34, 36, figure 1) to be connected in parallel to one set of switch cards through special "matrix boards" (90, figure 3). Multiplexing of the switch cards is accomplished by only bringing one circuit board into contact with test probes at one time. The sytem has a microprogrammed sequencer wherein signals representative of pin and board designations of switch boards are utilized in conjuction with a PROM which normally contains the next address to the currently-addressed pin and board designation.

Description

High Speed Testing of Complex Circuits

BACKGROUND OF THE INVENTION

This invention relates to a high-speed testing apparatus for complex printed circuit boards.

Although there has been much apparatus developed for use in testing printed circuit boards, most such apparatus has been severely limited in its capability to perform actual certification of error free circuits. This problem has become even more acute as the number of connections and components on circuit boards has increased.

Therefore it has remained a problem to provide a circuit-board testing apparatus that could, using a commercially-acceptable amount of hardware, provide a hign-speed means to certify circuit boards.

There is a large amount of switching circuitry necessary to perform such testing. It has not been possible in the past for multiple test stations to share this switching circuitry.

In understanding the achievement to be described below, it should be understood that both manufacturers and purchasers of circuit boards are often faced with testing hundreds or even thousands of a board of a single configuration and then proceeding to test another board, whoily different in design, yet with, typically, up to

10,000 or more electrical connections. Errors in testing can have very serious commercial consequences. Therefore, it has become necessary to undertake extraordinarily expensive testing procedures or settle upon statistical tasting techniques that will not provide error-free certification capability.

One of the major objectives of the system is to test and report faults in an entire pattern of opens and continuities as quickly as possible. The key features of the machine that allow such a rapid test rate are:

1. The data stored for the test sequence is in a raw form which is easily accessible, can be used quickly, and interrogated by the system to determine if there is a difference between what the machine has learned about a circuit to be tested and what the machine is actually measuring on that circuit.

2. The electrical sense circuitry is localized on each individual switch card and the amplifying circuit associated with switch cards provide one single strong signal transmitted from switch card to the point interface card and main CPU 200 indicates whether or not any of the cards has sensed a continuity.

3. The main CPU (central processing unit - data processor) programs the sequencer and controls which test station is to be used at the time, and which stored (learned) program is to be run at any given moment.

Another object is to report results to the operator of the testing apparatus in a useful form. This involves botn removing fault information which is redundant, for example multiple detected shorts which are the result of the same physical imperfection in the circuit board under test, as well as translating the fault information from the raw form used in test sequencing to a form more directly usable by a technician in repairing a faulty board.

It is further an object to be able to service multiple test stations from one set of switch cards and sequencing control circuitry. In order for this sharing of apparatus to be effective, the speed of the testing procedure must be especially fast. In addition to the speed requirement, it is necessary that multiple test stations be interconnected to the switch cards in a way that is both compact and does not require the additional costly circuitry.

A further object is to reduce the cost of switch cards. As a tester capable of testing 10,000 points uses 80 switch cards, switch cards contribute substantially to the cost of such test apparatus. Reduction in the complexity or the circuitry on each of these cards is advantageous.

SUMMARY OF THE INVENTION

The basic purpose of a machine built according to the present invention is to compare continuity/opens pattern of a circuit under test with that of a known complex circuit, particularly a printed circuit board, and to quickly and reliably report circuit faults.

The present circuit board tester provides for multiple test stations to share one set of switch cards and contol circuitry. Physically this is accomplisned by connecting the test probes at each test station in parallel with the test probes at the other test stations. Means is further provided for controlling the lowering of boards to be tested onto the test probes so that only one board is in contact with test probes at one time.

switch cards for a 10,000 point tester provide pins to connect to 10,000 points in a compact space. Yet in order for three test stations to share one set of switch cards, it is necessary for three times as many connections to be made to that set of switch card connectors. This parallel connection of the test stations is accomplished by the use of printed circuit matrix cards of unique design. These matrix cards provides a practical mechanism for cabling from three test stations to converge on and be connected to one set of switch cards.

In order to be able to test with sufficient speed to service multiple test stations from one set of control and switch circuitry, tasks are distributed among different pieces of hardware.

A main processor provides overall control. This processor determines which test station will, test at any time as well as providing the overall control of the test procedure. The main processor issues "stimulate and scan" commands to a sequencer; the sequencer sends the commands to the switch cards commanding the closing of specific switches.

A sequencer is microprogrammed to control the basic scanning sequence with high speed. Given a stimulus point and a point from which sensing should begin, the sequencer can control the opening and closing of switches to determine the "first hit", the lowest logically numbered point in the scan which has continuity with the stimulus point. The sequencer also provides the source voltage which is to be applied to the stimulus test point. Via a hit signal, all switch cards route sensed current back to the sequencer so that presence of a continuity can be rapidly determined.

switch cards are simple in design, yet operate with a test procedure that can test multiple points at one time. Control signals are provided by the sequencer to the switch cards through a control bus on the switch card backplane. Each switch card can determine its position from connections wired to the switch card backplane. switch cards need only be able to turn on one switch at a time, and need only be able to respond to two types of commands: turn on the designated switch if your number is greater than the indicated card number; turn on the designated switch if you number is equal to the indicated card number .

In the test procedure used, test points are sequentially used as source points; for each souce point, other test points are scanned in search of continuity. This search for the firs continuity is done in the same order as the points are used as source points. These resulting first continuities are then stored in a test table. This testing sequence results in a test table in which continuities are linked together. This facilitates the removal of redundancies when faults are detected.

In the test procedure used, the search for continuity involves testing groups of test points at once. The test points in these groups are on separate switch cards. This makes it possible to test groups of points at once (providing great speed advantage) while still maintaining a simple design for the switch cards (providing economy and reliability). BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 illustrates a perspective of a compact 3-test station embodiment of the invention, wherein each station comprises a test fixture and each operator has ready visual access to a single CRT display apparatus.

Figs. 2 and 3 together form a diagram illustrating the overall testing apparatus.

Fig. 4 depicts a matrix card useful in connecting 3 test stations to one set of switch cards. Fig. 5A is a test table that records the continuity pattern depicted in Fig. 56.

Fig. 6A is a test table that records the continuity pattern depicted in Fig. 6B.

Fig. 7A is a test table that records the continuity pattern depicted in Fig. 7B. Fig. 7C shows the same continuity pattern with the addition of a short.

Fig. 8A is a test table that records the continuity pattern depicted in Fig. 83. Fig. 8C snows the same continuity pattern with the addition of an open. Fig. 9A is a schematic of circuitry of the point interface card (PIC) which connects to a portion of the control bus of the switch card backplane.

Fig. 9B is a schematic of circuitry on the PIC used to generate a source voltage and to sense the presence of resulting current.

Fig. 9C is a schematic of a portion of the circuitry on the PIC.

Fig. 9D is a schematic of circuitry on the PIC used to indicate the number of switch cards installed the tester.

Fig. 10A is a schematic of decoding logic on the PIC.

Fig. 10B is a schematic of sequencer control circuitry on the PIC. Figs. 10C and 10D are schematics of the sequencers of the PIC.

Fig. 11 schematically depicts pins on switch cards; the pins that correspond to the continuity pattern of Figs. 6B, 76, and 88 are specially indicated.

Fig. 12 schematically depicts pins on switch cards; the pins that correspond to the continuity pattern of Fig. 7C are specially indicated.

Fig. 13 schematically depicts pins on switch cards; also indicated is the scanning sequence that is used once a hit has been detected on level 2.

DETAILED DESCRIPTION

Terminology

The present invention is used in the testing of the electrical continuity of circuit boards. The testing involves measuring the continuity pattern among a set of test points on the circuit board to be tested and comparing this pattern with a rererence continuity pattern. There are two types of faults: shorts and opens. The objective of the test is to detect these faults, in other words, to determine whether the circuit board under test has the desired continuities (i.e. does not have opens) and whether the board has continuities which are not desired (i.e. shorts).

Test points are locations on the circuit board from which it is desired to test continuity. The term "test points" is also often used to refer to the probes of the testing apparatus which contact the test points on the circuit board. The slight difference between these two meanings is rarely significant, and the intended meaning can generally be inferred from the context. A testing machine utilizing the present invention is capable of testing up to 10,000 or more test points.

Continuity testing is accomplished by the well know approach of applying an electrical potential across a possible circuit path and measuring the resulting current flow. In other words, one measures the impedance between pairs of test points: if the impedance is less than a threshold value, then there is continuity; if the impedance is greater, then there is no continuity between those test points.

When a pattern of metallic conductors is being tested (bare board testing), it is not necessary to determine the precise impedance of the path; essentially, it is only necessary to differentiate between current flow and lack of current flow. Altnough the invention will be discussed in the context of bare board testing, the present invention is applicable to other forms of testing. For example, the tester may be modified to provide for 4-wire testing. A tester with 4-wire capability can more precisely measure impedance of a circuit patn. This modification is particularly useful for loaded board testing, as is discussed below.

Testing for continuity between two test points is accomplisned by connecting a source (or stimulus) circuit to one of the test points and connecting a sense circuit to the other test point. The sense circuit also provides the source return (i.e. the ground side of the source voltage). Two switches are associated with each test point: one to connect the test point to the souce circuit (in which case the point is called a "source point"), and the other to connect the test point to the sense circuit (in which case the point is called a "sense point"). In the testing procedure described below, although only one source switch is closed at any given time, it is often advantageous (speeding the testing process by reducing the number of successive switch closures necessary to fully characterize a circuit board) to close a number of sense switches simultaneously.

These switches must have very low noise characteristics because of the speed of the switching operations contemplated. Typically, solid state switches are used. CMOS type switches are generally satisfactory. Other types may be used as, for example, when high voltage is used in the testing procedure.

These switches are arranged on circuit boards referred to as switch cards. A typical switch card will include enough switches to connect to 128 test points, i.e. 256 switches.

These switches are mounted on switch cards which themselves are held in switch card cages mounted on the frame of the apparatus.

The switch cards are installed in card cages and by being plugged into connectors in a backplane in the card cages. Each switch card cage holds 20 switch cards. A 10,000 point tester would thus include 4 card cages and a total of 80 switch cards. The connectors provide a pin for each test point to which a switch card can connect, i.e. 128 pins per card. There are additional connector pins for signals connecting to the point interface card (PIC) , which will be described in more detail below. There are also connector pins that uniquely identify each position in each of these card cages; thus, although the switch cards may be identical, once plugged into the card cages, each pair of switches on each switch card is uniquely associated with one test point. In other words, the assignment of test points is carried out by direct wiring of different slot positions within the switch card cages.

If for each card one numbers these pins from 1 to 128, then all pins numbered 1 (and all associated test points) can be referred to as a "level". Thus, altnough test points can be at arbitrary physical locations on a circuit board, it is often helpful to ignore the arrangement on the circuit board and conceptualize the test points as being arranged in a rectangular grid pattern, each card being a column of test points, each level being a row of test points; with this viewpoint, each test point can be referenced by its card number and level number.

Another useful way to conceptually arrange the test points is in one line. When discussed below, this numbering system will be referred to a "logical numbering", and, unless otherwise indicated, "test point number" will refer to the "logical number" described here. As will be described in great detail below, the testing procedure involves connecting, in sequence, each test point (except for the last test point) as a source point. If the points are numbered in the order in which they are chosen to be used as test points, then one can refer to higher numbered test points as being "above". Also, in this conceptual arrangement, the "first hit" refers to the lowest numbered point for which continuity with the selected source point is detected; "first" refers to the numerical order, not necessarily to time.

Since the test procedure need not use a source points any of the test points on those cards which (although installed in the tester) are not wired. to the currently installed fixture, the logical numbering changes from one test fixture to another . The logical numbering depends on how many switch cards are used in the test procedure. When a new fixture is installed at a test station of the tester, the operator, by use of the video terminal, indicates how many test ponts are wired in the fixture. The tester can then divide this number by the number of points per switch card (and round up) to determine how many cards are actually used by that test fixture.

"Physical numbering" refers to numbering the pins in the order they are wired to a fixture. When wiring, all pins on one switch card are used before one uses pins on the next card. Thus, physical numbering runs 1-128 on the first switch card, 129-256 on the second switch card, and so forth. With 20 switch cards per cage, the first card cage would have switches for test points 1-2560; the second card cage would contain switches for points 2561-5120; etc. The switches "know" with which test point number they are associated as a result of their position on the switch card and the above-mentioned wiring of the switch card backplanes in each card cage.

Alenough physical numbering is used in numbering test points when test fixtures are wired, it is not of much help in understanding the testing procedure of the present invention. As will be discussed below, there are advantages to choosing an order for source points (e.g. logical numbering) that does not correspond to the physical numbering of test points.

The logical and physical numbers associated with any pin on any switch card may be computed as follows: Logical Test Point =

[(Total Cards used in the Test)* (Pin # - 1)] + Card #

Pnysical Test Point = [(Card # - 1)*(Pins/Card)] + Pin #.

In the test process, data is manipulated in terms of logical test point numbers. But logical numbers are different from the test point numbers that are reported to the operator, nerein called a physical test point.

Before performing a continuity test on a circuit board, it is necessary to determine a reference continuity pattern against which the measured pattern of tested boards will be compared. Further, this pattern must be communicated to the test apparatus. The reference pattern can be provided in the form of a known correct circuit board; the communication of this pattern to the test apparatus can be accomplished by a process called learning a board. The learn mode in which the tester can operate is similar to, out distinct from, the test mode. Learning involves loading a correct board onto the test apparatus (in the same fasnion ooards to be tested will be loaded) and running a test procedure called a learning sequence, by which the test apparatus determines the continuity pattern. This pattern is then stored in the apparatus for use in the determination of faults on boards to be tested. This reference continuity pattern is stored in wnat is called a test table.

Because one does not generally have access to a known good board until the tester has tested some boards, usually 2 to 6 boards of uncertain accuracy are used to completely "learn" a circuit pattern. This is accomplished by "learning" a number of boards and comparing the results, taking tnose aspects of the continuity pattern that are most common among these boards as a presumption of what the correct pattern should be.

There is one register of memory reserved in the test table for each test point. This register can be 2 bytes long and is maintained in the random access memory. Two bytes are used for each test table entry in a system with 10,000 test points. Thus, to fully describe a pattern of opens and shorts for 10,000 test points requires about 20K bytes of random access memory (RAM) .

The machine stores test information in this test table in raw form which is obtained by a test procedure conducive to the speed of operation. However, this form of raw intormation is not very useful to the operator of the tester. Test point designations in this raw form are according to logical numbering. The operator of the tester relates positions of test points in the fixture to physical numbering. Also, multiple continuity discrepancies can result from a single physical fault, i.e. this raw information contains redundancies. Thus, the machine must decide what information is useful to the operator (i.e. remove redundancies) and translate this from raw form to a form more useful to the operator.

Overall Operation

In order for a particular type of PC Board to be tested it may have a customized test head (alternatively, a universal grid fixture may be used, as described below under "Variations"). The test head or test fixture is a device that mechanically interfaces the machine to the board that is to be learned and tested. In a typical situation, an operator may have to test several hundred of a particular board type. The board may be being shipped from a board manufacture or it may be component-loaded. In order for a board to be tested on the machine , it must be locked in place at one of the test stations of the machine. A test station is comprised of an operator control panel including a receiver assembly whereby the test head mechanically lnterfaces to the machine.

The board is placed on the test head. The operator must then load a learned or other test program into tn main CPU's memory from a floppy disk on which the program has been stored in a RAM of the CPU. This is conveniently done at the CRT unit. Each test station has memory space reserved, in which it can maintain the test table for the board to be tested on that station.

Tna operator then presses start at his test station. The main CPU then controls the sequencer through a point interface card which controls the switch closures on the switch cards.

The signals are routed from the switch card to the test stations through the matrix card(s) and cables. The measurement signals pass from the test station to the test head, through the test probes to the printed circuit board. An interlock mechanism assures that only one test station is allowed to engage a test head to a board at a time.

The results of the test for a given test station are communicated through an I/O board ( in the main CPU card cage) to the operator control panel. The operator control panel then removes redundant information and translates from logical test points to physical test points, and prints the appropriate faults on the ticket printer using the physicl test point data. A test is completed, the board under test is released from the test head on which it is mounted, and the main CPU goes on to service a next request from another test station on the CRT.

Rererring to Figure 1, a multi-station testing apparatus comprises a frame 30 which includes three test stations 32, 34, 36. Each test station carries a fixture 38 into which a printed circuit board may be "loaded" for testing. A cathode ray tube terminal is mounted on turntable 40 for viewing from each of the test stations. In normal practice the test results can be displayed on the CRT or can be printed at the individual test stations.

Figures 2 and 3 are a block diagram of electrical circuitry of the test apparatus. The apparatus shown is one wherein three distinct testing operations are carried out by three different test operators. Each test operator is operating a test station which has the capability of testing printed circuit boards with 10,000 test points.

Witnin frame 30 (Fig. 1) are four switch card cages each having 20 slots for receivng switch cards 100

(Fig.3). These switch cards are connected in parallel to all 3 of the test stations by use of matrix cards, which will be described in greater detail below. In a 10,000 point tester, cables bearing 10,000 conductors from each of the test stations all converge on and are connected to the switch cards. This massive interconnection is efficiently and compactly accomplisned by use of the matrix cards. Other control equipment including the controller processing units can also be compactly carried within frame 30.

Previous testers have provided only one test station for each set of switch cards. The present tester can be expanded to multiple test stations and still use only one set of switch cards. The preferred way to expand to three test stations is to mecnanically multiplex the boards, all three test stations using the same switches, and their use being mechanically, or electrically, segregated. This shared use of the switches represents a substantial economy, since a station capable of testing 10,000 test points requires 30 switch cards, each card having 256 switches.

This sharing is made possible by the combination of two aspects of this tester: (1) the tester operates fast enough that three stations can be serviced with one set of switch cards; and (2) the tester provides an arrangement by which the enormous number of conductors could all be physically connected to one set of switch cards. The first aspect (speed) is made possible by use of a particularly efficient testing procedure and by the the efficient division of tasks among several separate processors. The second aspect (physical connection) is made practical by the use of matrix cards and the mechanical multiplexing at the test fixtures of the circuit boards to be tested.

A testing station comprises a circuit board to be tested 101 under a test head 102 which is conveniently customized for each kind of printed circuit board to be tested. The test head (or test fixture) 102 will comprise wiring that will communicate directly through test point connections in the test well 104 (Fig. 3) to the matrix board 90 shown in Fig. 5. Various customized test heads can be installed into each of the test well. The matrix boards are an extremely compact and efficient means for routing signals between the switch cards 100 and the test neads when there are multiple test stations.

Each testing station also includes, conveniently, an operator control panel 110 and a printer. Most importantly, however, the test station comprises printer/operator control microprocessor 112, suitably basad on a Motorola 6809 microprocessor hnip, control circuits 116 for interfering with the control panel and printer control means 113. In addition, each operator station has its own bank of RAM 114. In general, 128K bytes of memory is used when testing a 10,000 test-point circuit.

The tasks of microprocessor 112 include: responding to the position of operator controlled switches, receiving test information (raw data from the testing of a circuit board) from the main CPU 200, removing redundant information, translating the remaining information from "logical test-point" form to a physical test-point form (a form more useful to the operator), and controlling a printer (a printer is located at each test station) which is used to provide a record of test results.

In addition, there may also be sufficient memory in the operator control panel processor to perform further translation to "user language". User language is that used to associate information describing a position on the board in terms other than test point numbers; it is a description more directly usable by a technician involved in tracking down and correcting the physical imperfections in the circuit boards that resulted in the shorts and opens reported by the tester. For example, "pin 6 of chip U15" instead of "test point 1295".

It is important to note that the processors at each of the three stations can each be operating on these redundancy-removing and translating functions while the main central processing unit 200 is servicing a test sequencing operations on one of the boards under test 101. Thus the main CPU 200 need ot take time after each test sequence to process rne raw data resulting from the test sequence. Instead, this. data is passed to the processor at the individual test station, preventing the redundancy removal and translation operations from delaying the overall operation of the tester. This is one of the features which makes multiwell sharing of one set of switch cards possible.

The main CPU 200 (Figure 2) is a microprocessor control system. Memory 206 contains the program for controlling the testing procedure (which is used for testing at all test stations) as well as memory to contain information relating to each of the three test stations. An important characteristic of the CPU 200 is that is comprises enough memory, two bytes or more (per point), to define the condition of each of the points which are to be tested on each of the three test fixtures. Typically, 64K of random access memory 206 will be reserved and availaole for each (typically three) of the test stations.

The primary job of the main CPU 200 is to operate the testing sequence for each of the boards under test, in a manner that will be more fully described below. Each test point may be considered a single wire. When only a single testing operation is associated with the apparatus the wire may go directly to the test fixture. When a plurality of testing operations are associated with the apparatus the single test point conductor is routed to the matrix board for further routing to the test fixture and to the circuit board to be tested.

A "point interface card" (PIC) controls all switch cards. It interfaces between cards and the main computer controller unit (CPU). The point interface card functions to determine what test points and the condition of test points and sequence of testing as they affect the switch cards. One point interface card will control all 80 slot positions in the switch card cages.

The point interfaces card controls the pattern in which switches are opened and closed in response to the main CPU. (In practice, it is usually desirable to have a new control program for each circuit board configuration to be subject to test. The control program is readily "self-learned" by a program in the CPU's readonly-memory (ROM) device and RAM 206. As a general rule, about 2 to 10 boards can "teach" the ROM through PIC card 129. This general procedure is already well-known.

The test pattern, or sequence, in which the card is tested is establisnad by D.C. excitation of a measurement circuit from sequencing through a single point interface card 129 which is described in Figs. 9 and 10.

A testing procedure, taken together with the signal-distriouting and signal-processing apparatus described above, provides not only what is believed to be an optimun balance between short test time and equipment cost out to achieve such a balance while providing the versatility to accept a large number of special problems associated with circuit board testing.

Matrix Cards

In order to accommodate the great number of potential connections and handle them in a reasonable amount of space, a matrix printed circuit board is snown in Figure 5. The switch card backplane has sockets on one side for the switch cards and has sockets on the other side for one edge of each of the matrix cards. There is one matrix card per switch card, i.e. for a 10,000 point tester, there are 80 matrix cards.

In the matrix board of Figure 5, there are two groups or conductors 94 and 92 but only one of each is shown in full, the other of each being indicated in fragmentary form.

Each side of an illustrated board 90 has 128 terminals, 80 which are associated directly with a set of parallel conductors 92 or 94. Conductor set 92 is insulated from conductor set 94 by insulator layer commonly used in printed circuit board manufacture. However, preselected connections are made between the conductor sets using the conductor-lined barrels (plated- tnrougn holes) 96 (according to the established techniques of printed circuit board technology) .

Figure 5 indicates the position of the connections in the insulator layer 95. It is to be noted that there are sets of terminals 80 at top and bottom of the board. A second set of plated-tnrough holes (arranged along a diagonal perpendicular to the first diagonal of platedtnrough holes) may also be used. This second set of connections enables the connectors on opposite sides of the matrix card to be in the same orientation with respect to the matrix card. In other words, each of the three connectors (connecting to the three test stations) would have pin 1 on the left (from the point of view of the connector). This arrangement of connector pins enables cables to be routed from each of the three test stations with a minimum of twists in the cabling. This is significant because an enormous bundle of cabling converges on these matrix cards from each of the stations.

In practice, this means that three distinct circuit board testing operations may be serviced from three perimeters while data is fed to and from a master controller serviced from the fourtn side of the board.

Each pin of the matrix board is associated with two switches. A source switch forms a connection with a source signal. A sense switch forms a connection to a sense signal. Each pin of the matrix board also connects to test probes in each of three test fixtures.

Use or matrix cards enables a system to be designed whicn can be initially operated with a single test station and later easily upgraded by the addition of other stations. The same switch card cage arrangement as is used for a single station system can be used with a multiwell system.

With a single test station, the cables connecting to the test fixture can connect directly to the switch cards. Where matrix cards are used, a Teradyne backplane is used between the switch cards and the matrix cards. A Teradyne backplane has back-to-back wired edge connectors, i.e. the edges of switch cards plug into one side and the edges of matrix cards plug into the other side.

Multiplexing

A feature of the present tester is that multiple test stations share one set of switch cards and one set of control circuitry. This is accomplished without the addition of circuitry. The test. fixtures (one of these customized fixtures is installed in the test well at each test station) are all connected in parallel to the switch cards.

Also provided at each test station is means for keeping the circuit board to be tested from contacting the test probes until it is that station's turn to test. Special spring-loaded locating pins are used to hold the circuit board above the test probes. Locating pins are commonly used to accurately position circuit boards. These are holes in, for example, two opposite corners of the circuit board; printed circuitry and holes for component leads are precisely positioned relative to these locating holes. The locating pins of the present tester are actually compound pins: a thin portion of the pin is located on the top of a portion which is of greater diameter; the thin part of the pin is sized to penetrate a locating hole, while the board rests against the greater diameter portion of the pin. This entire compound locating pin is spring mounted so that the circuit will be supported above the test probes (without contacting the probes) , but when downward force is applied to the circuit board, the pins give, allowing the board to lower into contact with the test probes. The downward force on the circuit board is applied by a door over the test fixture. When the test of a board is completed, the force on the circuit board is released, the springs push the board back up off the test probes, releasing electrical contact and freeing the switch cards to be used with one of the other test stations.

Data Representation and Scanning Test Points

The overall test procedure involves sequentially using each test point (except for the last test point) as a source point, and for each source point "scanning" the points above the source point to identify a "hit". A "hit" is the detection of a continuity between the currently selected source point and at least one sense point; the "first hit" is the identification of the lowest numbered point in the scan which exhibits continuity with the source point. "Scanning" is the process of selectively closing sense switches. Numerous scanning procedures are possible. The following scanning procedure offers particular advantages:

(1) a relatively small number of separate test steps (due to sensing from groups of points at a time);

(2) a simple design for the switch cards

(for example, switch cards need not be designed to close any arbitrary combination of switches, in fact, each card need only close one sense switch at a time) ,

(3) redundancies can easily be readily removed from the data which results from this procedure because the resulting list of continuities is "linked".

The tester has botn "test" and "learn" modes. The test mode is that which is used to detect continuity faults in circuit boards. The learn mode is used to build the test table from a know correct circuit board.

The basic scanning procedure (successively using each point as a source point and scanning to determine the first hit for that point) is the same for both test and learn modes. However, when testing, additional scanning procedures will be used when the determined first hit does not agree with that indicated in the test table.

First, the basic scanning procedure will be described in the context of "learning" a board. Then, the modifications of this basic procedure will be described in the context of detecting faults

The reference pattern of continuities is represented in what is called a test table. This is a list of first nits, one first hit for each test point (except for the last) . The "first hit for test point X" is the logical number of the lowest numbered point above x that has continuity with point X; if there is no such point, then the value of the first hit is set to zero, or some other special value that does not correspond to the number of any test point. The test table is stored in a sequence of memory registers: the address of the register corresponds to the number of the source point; the contents of the register is the number of first hit for that point. For example, if when point 25 is used as a source point (on a correct board) the first hit is point 87, then of the memory registers used to hold the test table, the 25th memory register will contain the number 87.

Even if for any source point there would be hits after the first hit, the list of first hits still fully describes the continuity pattern of the circuit board. This will be explained by the following example. Assume that when point 25 is used as a source point, there would be a hit at point 107 as well as at point 87. In this case the number 87 is recorded as the first hit for point 25; the continuity between points 25 and 107 is not directly recorded. However, when point 87 is used as a source point, the first hit recorded for it will be point 107. Thus the list shows that point 25 is connected to point 87, and that point 87 is connected to point 107; because each pair of points is considered to be either connected or not connected (degrees of impedance are not at issue) , one can conclude from examination of the list that point 25 is connected to point 107.

In carrying out a test on the illustrative system, it will be assumed that the test program for a single board calls for the testing of 2,560 connections: In practice, of course, different testing points may be selected when a particular circuit board to be tested "teaches" the machine (or is otherwise known) to not require that the testing include certain terminals on the circuit board.

In the following discussion of the testing procedure, it will be assumed that there are 64 points per switch card, rather than the 128 points mentioned in the discussion above. The matrix of test points can be looked at as a number of switch cards assembled in a row, left to right, each card having its test point connections along ordinates extending upwardly. This arrangement of test points is schematically illustrated in Figs. 11-13. Using such a model as the basis for discussion, it is pointed out that the general testing process is preferably one wherein the stimuli (i.e. source) points are selected, one by one, along each abscissa, left to rignt with the stimuli being moved upwardly to a new line of test points and back to the leftmost card when one abscissa finished. This sequence corresponds to the logical numbering described above.

For each stimuli point, the pattern in which test points are sampled (i.e. sensed) to see if they receive the stimuli is also along the abscissa and from bottom to top.

However, all points being "sensed" along an abscissa are tested at once (until the sensing of a hit or open may require some other procedure). Also, it snould be noted that all points which have already been utilized in the procedure as stimuli points are not utilized as sensing points. Thus for each source point, the only points which are scanned in the search for a hit are those points above (i.e. with higher logical numbers than) that source point.

Basic Scanning Sequence:

In describing this sequence, reference will be made to a relatively small matrix of cards and pins, i.e., one having 40 cards each card having 64 pins on test points. The first pin on the first card will be called C₁P₁, the first pin on the second card will be called C₂P₁. The

C₁P₁ source switch is closed, i.e. C₁P₁ is our first "stimulus point". Thus C₁P₁ is logical test point number 1. In the following discussion logical numbers are in pa heses following CP numbers. All sense switches of the same pin vaiue on all cards greater than the stimulus card are closed. Thus, all the sense switches corresponding to C₂P₁ tnrougn C₄₀P₁ are closed. If a continuity existed between the source point and any of the points wnose sense switches were closed (in this case, any other points on the first level), a hit signal would be channeled to the sequencer (the PIC) and the detection of the hit sent on by the PIC to the main CPU 200. In the case of all opens, there will be no such hit signal, ϊne next step, assuming no hit, is to turn off the sense switches at the first level and go to the next level (the next highest pin number P₂); all sense switches at the next level are turned on (as opposed to the case of the level on which the source point was located, in which case only those points on higher numbered cards than that of the source point are turned on) . If a hit signal is again not generated, switch off all sense switches, and then turn on the sense switches on the next highest pin level. Continue this procedure of successively turning on rows of sense switches until either a hit is detected or until all pins of ail cards beyond the source pin have been tried. If no hit is detected, "0" is stored in the register corresponding to that stimulus point.

After completing the scan for the first hit for pin

C₁P₁ ^, a scan is performed for the first hit for pin C₂P₁. This is accomplished by turning off the source switch for

C₁P₁ and turning on the source switch for C₂P₁. We then turn on all sense switches to the right of card #2 (i.e. cards 3-40) on the same pin level, C₃P₁ through C₄₀P₁ and cnhck for a hit. If there is no hit, turn off those sense switches C₃P₁ through C₄₀P₁ and turn on all sense switches of all cards of the next nignest pin level C₁P₂ through C₄₀P₂. Continue this process for each stimulus point until all points have acted as a stimulus at least once and only once. This procedure continues until all test points have been utilized as stimulus points at least once and only once. The order in which the source switch for each point is turned on is C₁P₁ , C₂P₁, . . .

C₄₀p₁, C₁P₂, C₂P₂ . . . C₄₀P₂ . . . C₁P₆₄ . . . C₄₀P₆₄. (Note that C₄₀P₆₄ need not actually be used as a stimulus point because it is known that there will be no hit: there are no points aoove it to scan as sense points.) For further illustration, when pin C₇P₂₅ is the source point the scanning sequence is as follows: all sense switches at level 25 on cards 8-40 are turned on (not sense switches on cares 1-7); if no hit, then turn those sense switches off and turn on all sense switches on the next level, e.g. pins C₁P₂₆ througn C₄₀P₂₆; if still no hit, then go to the next higner level; etc., until a hit or until all higner pins have been tried.

When a hit is detected, an additional procedure is followed in order to determine which test point was responsible for the hit. Because points on each of the switch cards are sensed simultaneously, when there is a hit, it is not immediately known which test point was responsible for the hit (or if more than one point at that pin level was responsible for the hit, what is the number of the lowest point responsible for the hit).

Thus, when a hit is detected, all of the sense switches are turned off, and the sense switches at the pin level at which the hit occurred are turned on one at a time (starting with the pin on the lowest numbered card being scanned) until a hit is again indicated, tnus determining the first card with a hit at that level.

The following example illustrates the procedure followed when a hit has been detected at pin level 6. Turn off all sense switches. Turn on the sense switch at C₁P₆. if a hit, then C₁P₆ is the first hit, otherwise turn off C₁P₆ and turn on the sense switch for C₂P₆. If a hit, then C₂P₆ is the first hit, otherwise continue trying the sense switches at that level. Note that if in tnis example the source point had been on level 6 (i.e. there was a hit in the first level tried) then C₁P₆ would not have been tried; rather, the first card tried would have been that one immediately to the right of the card on which the source point was located.

The process of learning is continued, closing the next source switch etc., until all (but the last) of the test points has been used as a source point and the test table is complete, that is, to say, until the apparatus has learned the pattern to be stored in the main CPU and Printer/Operator Control memories.

This procedure results in the determination of the first hit that corresponds to each test point. This is all that is required for the learning mode. This first hit information is all that is stored in the test table, and is all that is needed for representation of the reference pattern when boards are tested for continuity faults.

This is information is stored as a table of numbers: the position of each entry in the table corresponds to the logical number of the source point for which the content of that entry is the logical number of the point which is the first hit.

A copy of the test table for each of the test stations is stored in memory of the main CPU. A copy of the test table for each particular test station is stored in the memory 114 of the processor 112 in the Operator/Control Panel for that test station.

For tasting possibly faulty circuity boards this basic procedure is used. However, whenever the first hit detected does not correspond to the first hit as recorded in the learned test table, a fault exists and additional procedures are used.

A Specific Example of Learning a Board:

As an example we assume that three test points connected when the circuit is on a test head are C₄P₁, C₄₀P₂, and C₁P₃. These correspond to logical test point numbers 4, 80, and 81 respectively and correspond to physical test point numbers 193, 2498, and 3 respectively. In this example Fig. 6B shows a physical realization of the continuity pattern. Fig. 11 indicates which pins on switch cards are connected in the continuity pattern, and Fig. 6A shows the test table representing this continuity pattern. In this example, logical test point numbers are shown in parentheses after the corresponding card and pin numbers.

The general test sequence is the same as described above. C₁P₁ (1) stimulus switch is closed, and pin 1 of all cards have the sense switch closed. A continuity is not detected from pin 1 to any of the sense points, all sense switches are opened. Then, all sense switches for pin 2 of all cards are closed. No hit is detected. Thus a zero is placed in the first location in the test table. This process is repeated for all pin levels above the pin level of the source signal. A zero is stored in register 1. Next, C₂P₁ (2) source switch is closed. All pin 1 sense switch switches on all cards from C₃P₁ (3) through C₄₀P₁ (40) are closed. The process previously described for C₁P₁ (1) is repeated until either a hit is detected or all nigher numbered sense switches have been tried. In this case no hit is detected and a thus zero is placed in register 2 in the test table. The same process is repeated for C₃P₁ (3) and a zero is stored in register 3.

The same process is then repeated for C₄P₁ (4). However, when pin 2 of all cards is turned on a continuity is detected and a hit signal is generated. We have determined that C₄P₁ (4) is connected to a pin 2 of some as yet unknown switch card. We want to determine the lowest card number that generated the hit signal. (Several cards could have generated a hit signal.)

To determine the lowest card number, we open all sense switches ano close the sense switches for C₁P₂ (41). There will be no hit there in this example, thus we continue by turning off the sense switch at C₁P₂ (41) and closing the sense switch at C₂P₂ (42). Again there will be no hit. We continue this polling of the individual switch cards until a hit signal is generated.

A hit signal will be generated when the sense switch for

C₄₀P₂ ( 80 ) is closed. At this point an 80 is stored in location 4 in the test table.

This process is continued. No hit will be detected until C₄₀P₂ (80) is used as a source point. With C₄₀P₂ (80) as a source point there will be a hit detected when the sense switches for pin level 3 are closed. These switches will then be opened and the switch for C₁P₃ (81) will be closed. There will be a hit at C₁P₃ (81), so polling of the individual cards ends and 81 is stored in location 30 in the test table.

This process is continued until the test table of Fig. 6A is completed There will be no further hits; all remaining entries in the test table will tnus be filled with zeros.

Testing — Fault Identification

In the test mode the pattern recorded in the table of opens and continuities is compared to the results of the actual measurements made on the circuits being tested. When the two agree, no information is reported to the Printer Operator Control processor 112 and memory 114. When there is a discrepancy between what has been measured and what is recorded in the table, the raw information is reported. Raw information is supplied to the microprocessor at the operator control panel. At the operator control panel this raw information is culled of redundnt information and translated sucn that only useful information is reported to the operator.

The manner in which the test points are actually switched during testing in which measurments are made is not dependent on the general test pattern that is resident in the CPU's RAM, or the pattern learned at the time. These points are switched according to the same general method during each test, which follows the basic sequencing pattern described above. It is only once a discrepancy between the measured and learned continuity patterns has been identified that the test sequence differs from that used in learning (and described above).

The test apparatus is capable of reporting multiple faults such as the following: more than one short to one test point; a test point that snows an open as well as one or more shorts.

In test mode, any additional scanning that might be required (beyond that of the basic scanning procedure) and the reporting of faults depends on comparison between the number of the first hit actually measured and the number that the first hit should be as recorded in the test table. (Note that this "reporting" of faults is not reporting to the operator; rather, this raw fault information is passed to the Operator/Control processor which will further process it and remove redundancies before reporting it to the operator of the tester.)

If the measured number is equal to the expected number (as indicated in the test table), then there is no fault to report from this hit, and no further scanning with the existing source point is required. The test procedure then moves on to the next point to be used as a source point.

If the measured number is less than the expected number, then a short is reported from the source point to the point responsible for the hit. in addtion, keeping the same source point, scanning is continued in search of the next hit. Depending on how the next hit number compares (equal to, less than, greater than) with the number stored in the table for the existing source point, a further fault may or may not be reported and scanning may or may not continue yet again using the same source point.

If the measured number is greater than the expected number, then it must be further determined whether the measured number is "linκed" to the expected number. It is a feature of the scanning sequence of the present invention that points which are connected together form a linked list in the test table. Thus it is easy to determine from the test table the logical numbers of all test points to which a given point should be connected. This can be seen in the test table of Fig. 6A: as indicated by location 4, point 4 is connected to point 80 ; looking in location 80, we see that point 80 is further connected to point 81; thus point 4 is also connected to point 31. This "linking" means that the contents of one register of the table can be used as a pointer or address to another address which has as its contents the number of another connected point. To determine whether the measured number is linked to the expected number, one looks at the contents of the location pointed to by the expected number. If this is equal to the measured number, then the number is linked. If it is less, then one uses that number as a pointer an compares the number in the location pointed to by it. This process continues until a number equal to the measured number is found, in which case there is a link, or a number greater than the measured number is found, in which case there is no link.

If the measured number is greater than the expected number and the measured number is linked to the expected number, then there is no fault to report from this hit, and no further scanning with the existing source point is performed. If the measured number is greater than the expected number and the measured number is not linked to the expected number, then a short is reported and scanning is continued for the next hit.

To test a circuit to see if it has the same continuity pattern as the pattern that was learned, the circuit to be tested is placed on the machine and the machine is placed in the test mode. The machine tests for a pattern in the same fashion that a pattern is learned. When a hit is detected for a given source point the number of the sense point that caused the hit is determined and compared to the contents of the register that is associated with the source point. If the numbers are equal, then there is no fault to report. If the hit point is different from the value contained in the register, it is compared to the expected value; the specific procedure followed in response to detection of a fault depends on whether the hit is less than or greater than that indicated in the table.

A Testing Example Showing Detection of a SHORT:

Although there are typically 128 pins are on a given switch card and there are 80 such switch cards in the switch array, in the description below, to simplify matters, we discuss a situation wnerein there are 64 pins per switch card and there are 40 switch cards total.

Given the continuity pattern that should exist as shown in Fig. 7B, its the learned table in Fig. 7A, we can then examine now it tests a pattern that is shown in Fig. 7C and wnere the interconnected points are indicated in Fig. 12. The test sequence starts the same as the learn mode. The source switch of pin 1 of Card one is closed, and all sense switches of cards of pin levels greater than the source pin are stepped through, no hit is detected so the resulting value is zero. This value is compared to learned value in register 1. The two values are equal. Thus, a fault is not reported to the operator control panei. The same process is repeated for C₂P₁, C₃P₁, etc. However, when the C₄P₁ source switch is closed, and when all sense switches at pin level 1 on cards greater than card four are closed, a hit signal is generated.

In order to determine which card and pin caused the hit ( short fault in this case) all sense switches are opened and C₅P₁ sense switch is closed. No hit is generated, Next C₆P₁ sense switch is closed. A hit signal is generated. The logical test point value of this point is 6. This is compared to the contents of the learned register value of logical test point 4 (see the test table in Figure 7A); register 4 contains the value of 80. Six is less than 80, thus a short from test point 4 to test point 6 is reported to the operator control panel. The main CPU directs the sequencer to continue the scan; the scan continues beginning with closing sense switches greater than the sense switch that detected the fault. There are no more hits on that pin level. At the next pin level all sense switches on all boards are closed. A hit is detected. Next, one sense switch on pin level 2 is closed one at a time, from C₁P₂ onward, until the board that caused the hit is determined. (See Figure 12) The circled X indicates the test point that caused the hit signal to be generated. Its logical value is 80 (C₄₀P₂), this value is compared to the value in the register for logical test point 4 (the source point); the two values are equal, and the test sequence associated with the source test point 4, is complete.

The test sequence continues by using test point 5 as a source point. No hit is detected. The value zero is compared to the contents of register 5 in the test table (Fig. 7A). The two values match, no fault is reported.

Test point 6 source switch is closed and sense switches at pin level 1 on all boards greater than the source board (board 6) are closed. A no hit signal is generated. All sense switches are closed on pin level 2. A hit signal is generated. To find where it is each sense switch on pin level 2 is closed one at a time until a hit is detected. A hit is detected on pin 2 of board 40. This is logical test point 80. This number is greater than the 0 stored in location 6. The 80 is not linked to the expected value, because the expected value is 0, and nothing is linked to 0. A short is reported between 6 and 30 and scanning continues. Another hit is detected on pin level 3 at point 81. This is also reported as a short. Scanning continues, but no further hits are detected while using point 6 as a source point. A zero is finally reported and this is equal to the contents of register 6; tnus no further faults are reported for test point 6.

The test process is continued for test points 7 to 79, no continuities are detected and the value in each of the registers is equal to zero. No faults are reported. Test point 80 is found to have a hit. It is determined that test point 81 has caused the hit. The contents of register 80 is equal to 81. No fault is reported. The remainder of the test points act as source points, and no continuities are detected. The contents of these registers are equal to zero so no additional faults are reported.

A Testing Example Showing Detection of an OPEN:

Given the continuity pattern that should exist as shown in Fig. 83, its the learned table in Fig. 8A, we can then examine how it tests a pattern that is snown in Fig. 8C and wnere the interconnected points are indicated in Fig. 13.

The test sequence is the same as previously outlined for the detection of a short: The first pin on Card one is stimulated, i.e., the source switch of C₁P₁, is closed and all "pin 1" sense switches on all cards greater than the source card are closed. A hit is not detected. Succeeding pin levels are also scanned, and no hit is detected. The resulting value is zero, this is compared to the contents of register 1 (see Fig. 8A) . The two values are equal, no fault is reported. The same procedure is followed for C₂P₁ and C₃P₁.

The source switch for C₄P₁ is closed. The sense switches for all pin 1's of all cards greater than the source card are closed, no hit is detected. Next, all sense switches for all cards are closed for the next highest pin level. (all P₂s) No hit is generated (because there is an open type fault at pin 80). Then, all sense switches of the next nignest pin level, (all P₃s) are closed; a hit is generated. Closing the sense switches at the P₃ level of each card, one at a time, determines that card 1 generated the hit signal, logical test point 81. The contents of register 4 are compared to the logical test point value of 81. The value in the register is 80, 81 is greater than 80. An open is reported to the operator control panel from test point 4 to test point 80. Next, the contents of register 80 (the expected value) is compared to the value of 81. If the two are equal, no additional faults are reported. However, if the two were not equal, a short would be reported if the contents of the expected value was greater than the detected value. The test sequence would continue until the detected value matched a value that was pointed to by the contents of the registers associated with test point 4, or until all sense switches were closed in the usual sequence and a no hit condition was determined. Any mismatch other than the no hit would be reported as a short to test point 4. The test sequence for card four pin 1 is complete.

The test sequence is continued for each logical test point as previously outlined. All the other points up to 79 are "no hit" tests wnose corresponding register contain zero so no fault is reported.

The source switch for test point 80 is closed and all sense switches are sequentially closed as they would for a no hit condition. At the end of the sequence a no hit condition is determined. However, the contents or register 80 is equal to 81, an open is reported from 80 to 81. No further comparison is to be done because a no hit condition exists.

The source switch and sense switch sequencing continues as previously outlined. All other test points have a no-hit condition. The contents of the corresponding registers are equal to zero, so that no additional faults are reported.

It is to be understood that other orders of testing procedures are operable. However, it is believed that when a great many points are being tested in a given circuit, other procedures would not present the testing data to the operator test station data processing apparatus in such a way as would enable such facile removal of redundant data. Thus, relatively more data processing equipment would be required.

Other basic test sequences could be used. In particular, using the matrix model described aoove for switch cards and pins, a vertical rather than norizontal sequencing system could be used; a horizontal stimuli and vertical sensing system is used; a vertical stimuli and norizontal sensing system is used.

However, such alternative testing sequence would not minimize the amount of circuitry required for each switch card in the way that scanning a level at a time does (as opposed to card at a time) . If sensing is done 1 card at a time, then it is necessary to design switch cards capaole of sensing at multiple points at one time; further, switch cards would have to be able to turn on all sense switches aoove a certain level (i.e. when the source point is on the same card) and not turn on the sense switches at and below that level. Sensing in groups where the groups are all pins on one level results in simpler decoding circuitry for the switch cards; this approacn keeps the decoding circuitry on all cards working all the time, rather than sitting idle while only one of the switch cards is working; thus each switch card need have less decoding circuitry.

Removal of Redundant Information

All detected open-type faults are reported. Shorts are checked for redundancy: if there is a short between a pair of test points, then other test points connected to one of the 2 test points will show shorts to all of the test points connected to the other of the 2 test points.

The duplicate entires pertaining to each test operation are removed at each the operator control panel by maintaining two "tables" in its memory. The first is a copy of the test table which was learned. The second is a table of all non-redundant fault information that is reported on a given test up to the current point in the test. When a fault is reported to the main CPU all other faults in the fault table are used to examine the test table. If an already reported fault is linκed (as determined oy examination of the table of reported faults and the test table) to the new fault, the newly reported fault is not printed. However, if the newly reported faults proves not to be linked to already existing faults in the fault table, sucn information is added to the fault table and the new fault is reported. The test table is retained as long as boards of the type of the "learned" board are tested. The fault table is cleared everytime a new board is presented for test. The order in wnich data is acquired in conjunction with the way in which the data is stored in memory greatly speeds the removal of redundant information.

The recording and printing of a fault is a two step process as each fault is recognized by the sequencer and main CPU. The information is sent to the appropriate printer/operator control board (POCB) via the I/O control board. The "POCB" has the same test table as the one stored in the main CPU memory. The fault data as well as the test table is used to select the information that is to be printed. This is necessary because the main CPU sequence provides complete but duplicate information.

In the above example of testing and detection of a short, it was shown that shorts would be detected between points 4 and 6, points 6 and 80, and points 6 and 81. The operator/control panel processor would print the first of these (the short between points 4 and 6). However, the other shorts would be found to be redundant. This is determined because points 6 and 80 are both either found in the table of already reported faults, or linked to points in the fault table. Likewise, points 6 and 81 are either both in the fault table or linked tnrough the test table to points in the fault table. This is determined as follows. Point 6 already exists in the fault table. There would be a entry in the fault table indicating a short between points 4 and 6. Thus the test table is examined for links to point 4. The test table (see Fig. 7A) shows that point 4 is linked to point 80, which is itself linked to point 81. Thus the otner points involved in the reported shorts, points 80 and 81, are linked to already reported faults. Since ootn 6 and 80 and both 6 and 81 are either in or linked to the fault table, these faults (6 to 80 and 6 to 81) are considered to be redundant faults, and are not printed or otherwise reported to the operator. Distribution of Tasks

The various tasks performed by the tester are distributed among various pieces of hardware. This contributes to the speed with which the tester operates.

The main CPU 200 controls the overall operation of the tester, determining which test station is actively testing at any time, controlling the scanning procedure at a high level. In directing the testing of a board, the main CPU directs the PIC, while the PIC then directs the switch cards to close specific switches.

An feature of this tester is the cooperaton of the CPU with the sequencer. The sequencer is microprogrammed to rapidly perform a switching sequence. However, when the sequencer's capaoilities are best superceded, the CPU steps in and redirects the sequencer. This redirection of sequencing activity takes place when, during the testing of a circuit board, a fault is detected.

The Operator/Control Panel accepts input from the test station operator, prints fault reports for the operator, and processes the raw fault information into a usable form.

There is also an additional processor which keeps overall statistics on tester operation. This is indicated in Fig. 2 as the "domain processor".

Switch Cards:

Each switch card nas means for channeling sensed signals to the PIC. By detecting this sensed current, the PIC can determine if there has been a "hit", i.e. if there is continuity between the present source point and the present sense point (or at least one of the present sense points if the PIC has commanded xnore than one sense switch be closed).

switch card close switches in response to commands received from the PIC on a control bus in the switch card backplane. Only one source switch is closed at one time. When a command directing the closing of a source switch is placed on this control bus, each switch card determines whether the indicated switch is on that card. More than one sense switch may be clcsed at once, altnough individual switch cards can close only one at a time. Switch card sense switches respond to three commands directing the closing of sense switches: "greater than" command, an "equal" command, and an "all" command. When the "equal" command is given, then the only sense switch closed is the sense switch on the switch card whose number equals the indicated card number (the switch on that card which is closed is the one at the pin level indicated in the command) . When the

"greater than" command is given, all cards with numbers greater than the indicated number close sense switches. The "all" command instructs all switch cards to close sense switches; each switch card closes one sense switch at the pin level indicated in the command. The "greater than" command is used in the basic scanning sequence to close groups of switches (all sense switches at the same pin level as the source switch. The "all" command is used to close groups of sense switches at levels higher than that on which the source switch is located. The

"equal" command is used after a hit has been detected to poll the switch cards to determine which is the lowest numbered card with a hit. Requiring that switch cards only be able to close one switch at a time greatly simplifies the circuitry which must be contained on each switch card as compared with a tester in which the switch cards had to be capable of closing groups of switches. Further the savings over a system in which switch cards must be able to close arbitrary sets of switches is enormous. It is a feature of this tester that it achieves both the speed that results from sensing groups of test points at a time, out also achieves the economy resulting from reduced circuitry requirements for the switch cards.

Point Interface Card (PIC):

The PIC is a state machine designed to stimulate a test point and seen a hit.

Aithough the main CPU controls the overall sequencing, the PIC controls the details. The PIC is capable of being given a source point board and pin and a point number from which scanning snould begin (generally exactly 1 greater than the source point number, except after a fault nas been detected, in which case there may be a search for additional hits) and scanning until a hit is detected. It then reports to the main CPU the board and pin number of the point with the lowest logical number in the scan for which there was a hit. The main CPU compares this information with that in the test table and directs the PIC to perform the next scan.

The sequencing apparatus (Figs. 9 & 10) has a highspeed sequencer utilizing a Mealey-Moore machine and nign-speed TTL (Transister transistor logic) buffers and latcher. bipolar programmable read-only memories (PROMs) with a propagation delay of 15 nanoseconds. Mealey- Moore machines are known in the computing art as the components used therein and the technology by which said components are assembled to achieve high-speed sequencing.

In general, the sequencer is a multiple state machine which goes from one state to another depending on what its state is at any time and what stimuli it receives. It is driven by a system clock, at say 0.5 or even a 1.0 MHz.

There are actually two similar sequencers on the PIC: a board sequencer and a pin sequencer. The board and pin sequencers are operated simultaneously. A particularly unique feature increases the speed of the system. The sequencers are set up with a starting address (decoded to board and pin) and a PROM which contains current address plus 1. This allows the sequencer to be ready to clock the next address at the very next pin latch or board latch signal. This will not occur, however, if the board latch or pin latch or hit have occurred. Either of the above conditions will cause tn clocks to stop and the microprocessor to read the address of the Board and Pin Sequencers. The sequencer are then preloaded and the process continues.

The functions performed by the PIC are the extended addressing procedure; generating pin and board limit signals by sequencers; timing functions using pin and board clock circuits which have various speed settings varying in, e.g., two microsecond steps. The board also contains status registers which are available to the microprocessor to be read. Also included on this board is the DAC, which is programmaole, which sets up the excitation voltage used for stimulating the board under test. This circuitry also contains the super hit sensor circuitry. The functions that are defined above are described below.

The extended addressing is used to generate board select which in turn is decoded into the various control states used by the remainder of the logic.

The pin and board sequencer are loaded with starting address from 1 to 128. The sequencer then runs until it hits a pin or board limit or until it sees a hit signal. A hit is defined as a connection between the points enaoled by the board and pin sequencers.

The pin and board sequencer essentially work in suostantially similar ways. Looking at U23 and U24 in Fig. 10D, the current pin address is generated at the output side or U23 (these are TTL levels) and is translated into CMOS levels. The 75365s convert the TTL 5-volt input into a 12-volt output. U24 is a PROM which is programmed always to contain the next address so that the current address is fed into its input side (AO thru A7 ) , and it translates the input address into the next output address and it outputs the D-D7 which are connected to the inputs of the latch U23. The latch is controlled by the pin clock or board clock in the case of the board operations U39 and U41. The clock signal is generated from the buffered E-Clock which is snown at U26. U26 need not actually be used (it would provide a divide by two) out the alternate system, the jumper shown as a megahertz is installed and U26 is left out.

U29 and U30 form a down counter which when the count of zero is reached, automatically reload the starting count and continue the clock sequence. Asssuming that the pin sequencer is running, then a pin start common will have been issued to U39 pin 1 which takes U41 out of the present condition and allows it to repsond to the clock pulses at its input derived from U40 pin 3. These clock pulses are inverted in U42, 9 and 10 and gated with pin limit at U42 pin 13. Assuming that the pin sequencer clock is running clock pulses at the rate specified by the speed command at pin latch, U29 pin 3 and also U23 pin 11 causing the LS374 latch to set up the next address previously establisned at the output of U24. This next address is then sent out to the input points 0-7 through the 75365 buffers and go to the input of U24 so that the next address is being estaolisned. The next address is simply set up by programming U24 with the desired address sequences.

When pin limit is reached, (this happens when all 8 outputs from U24 go high) , the output of U49 pin 8 will go low, signifying pin limit. The condition of pin limit causes the pin latch pulses to stop, this is done via U42, 13.

The microprocessor is also signaled that pin limit nas occurred via U23. The system then simply waits for the microprocessor to set up a new set of pin and/or board addresses, making use of the pin set and board set commands.

Any time that a hit occurs U50 pin 8 will go high causing the two clock counters, U29 nd U30, to cease counting so that the current pin and board addresses are frozen. The hit command also is sent out to the microprocessor at U23 to signal it that a short has been found and that the appropriate board and pin addresses should be read to establish whether the point is legal. The analog system excitation level is established by the digital-to-analog converter (DAC) U15 (Fig. 9B) , this is a voltage output DAC. Its output is buffered by U2 and used to drive excitation high to the analog voltage specified as stimulus on the menu. The DAC is an eight bit DAC so the range of stimulus (the excitation-high signal) can be set over 0 to 225 steps and covers a voltage range from 0 to 10 volts. (The steps are conveniently aoout 40 millivolts per number input to the DAC) .

The excitation high signal from the DAC ( the stimulus signal to the test point cards) includes "super hit". The function of super hit is to detect those errors that might be missed due to bus type problems where a multitude of shorts could appear causing loss of normal excitation voltage. Super hit works oy monitoring the current in the excitation high signal. Any time that the current exceeds the amount of current that would flow from approximately 10 Ohm hits a comparator U1 (which is tied in parallel with the hit line) pulis the signal to the hit line low whether or not any of the switch cards senses a hit.

The microprocessor does not distinguish between a hit caused by super hit or one caused oy one of the switch cards. When a hit occurs the pin and board sequencer clocks stop, the microprocessor is notified and it searches out the location of the hit as it would for any hit. Two separate hit levels are provided for, one in a two-wire case and one in a four-wire case. The necessary switching of signals is done in U14. Sw1 informs the microprocessor of the number of boards that are currently active in the system via U9, which is read as the Sw1 memory locaton. When the microprocessor reads this address, it is given a binary representation of the number of switch cards in the system.

The output board and pin addresses are set up in U21 and U22. which appear to the microprocessor simply as memory addresses. When written to, they establish the two eight bit addresses for the output board and output pin. The system operating modes which are two-wire, four-wire, and ALL, Equals, or Greater Tnan mode are establisned through the board control command via U20. The appropriate memory word is simply written to the board control address and U20 latches the values.

The initial pin and board addresses are set up through the pin set and board set command respectively. A pin set is used at U27 pin 13, the pin set is an active low signal and when it goes low U29 pin 3 goes low causing the pin latch at U23 to go low. However, this latch is active on the positive edge of clock so nothing happens at this point. When the pin set goes low the pin write enable signal goes active causing U36 to pass the data buss data into the inputs to the latch. The prom

U24 will have been disaoled by the pin prom enable signal at U24 pin 15. At this point pin set returns high causing pin latch to go high which in turn causes U23 to latch the input data derived from the data bus as opposed to the normal route of data which it gets from 024. This sets up the initial pin addresss, a similar operation sets up the board address at 021 and 022. Once these addresses have been set, a pin start at 039 pin 1 or board start 039 pin 13 causing either the pin or the board sequencer to function. Variations

Software Masking and Universal Matrix Fixtures:

A test apparatus built according to the present invention will in general have a greater number of test probes than there will be test points on any particular circuit board. The test time can be reduced if test probes in the test apparatus which do not connect to test points on the circuit under test can be eliminated from the test sequence, i.e. there is no point in using these as source points. This elimination of certain possible test points from the test sequence is called software masking.

In the currently most common arrangement of this type of test apparatus, a test fixture is wired especially for each type of circuit board to be tested. Such a custom fixture is provided with test probes corresponding to the locations of test points on the circuit board. These test probes are wired to as to be connected to switch cards, filling one switch card, filling the next, and so forth. With these custom fixtures one need only indicate to the tester the number of switch cards wired to the particular test fixture in use, and the tester will then know which switches are connected to test points (except for some on the last card used).

An approacn different from this custom fixturing approach is the use of a unversal matrix fixture. The universal test matrix is a type of fixture which has test probes positioned in a square grid pattern with a spacing of, for example, 0.01 inch. Circuit boards that are designed so that all test points are positioned on such a grid can then use the same test fixture; for these boards the substantial cost of wiring a custom fixture can be eliminated. However, unlike custom wired fixtures, the test points actully used on any given circuit board will not correspond to a limited group of switch cards.

Without software masking, ali test probes in the matrix would need to be used as source points.

The problem with using software masking in conjunction with a universal matrix fixture is communicating to the software the identifications of the test probes actually used for each type of circuit board to be tested. This problem can όe solved by the use of a shorting plate.

4-Wire Testing:

4-wire capability is more important with the testing of loaded boards, rather than bare boards. Bare boards contain metallic circuit connections, but do not yet contain any electronic components. Loaded boards have components installed on them. Distinguishing between current flow due to shorts and current flow due only to the installed components requires more precise impedance measurement than is needed for the testing of bare boards. 4-wire testing eliminates innaccuracy in sensing due to the impedance of the semiconductor switches that are used to connect test points to source and sensing circuitry, witn "4-wire" capability, single wires still run to each of the test points, but there are four switches for each test point, rather than two: source voltage; source voltage return; sense; sense return. In a 2-wire system, source and sense circuits share the same switches. Addition of a Priority Chain to the Switch Cards:

Some logic can oe added to each of the switch cards and the switch card backplane can be modified so as to allow automatic identification of the first card with a hit on a given level. The modification to the switch cards and the backplane results in the formation of a priority chain for the switch cards. Thus if a card detects a hit, that card can, by use of the priority chain, determine whether it is the lowest numbered card with a hit. With this modification, once the level is determined during a scan, the lowest numbered switch card with a hit can identify itself to the PIC; this eliminates the need for polling the individual cards.

AutoLearn :

Another feature that can oe used in conjunction with the above-described tester is an ability to automatically determine the maximum sequencing speed at which a particular type of board can be tested. Due to capacitance of the board to be tested and the tester itself, there is a settling time required between sensing from a new set of sense switches. To perform the autolearn function, a circuit board of the type to be tested is installed in the test fixture and a series of learn-type procedures are run on that board. These procedures are performed at various sequencing rates. The test tables resulting from tests performed at low rates will be identical. However, at rates above which the board can reliably be tested, the test tables give erratic results. By performing test runs at various rates and examining the resulting test tables, the optimum test rate can be determined . Augmented PIC Capabilities:

The PIC might be microcoded to make it able to perform the entire test sequence, rather than just a single scan. This can reduce the time for an overall test sequence. Additionally this shifts some processing load from the control CPU to the PIC, freeing the control CPU to spend more processing time on other tasks. Further, the PIC might be microcoded to be capable of adjusting test parameters for each individual source point; for example, some source points may have to be tested at lower rates than others.

In Conclusion

From the above it will be seen that we have described a circuit board tester with several advantageous features. In addition to the advantages obtained from the individual features, these features combine to make "multiwell" testing possible. A multiwell tester provides the capacity of several testers at a fraction of the cost.

Matrix cards and mechanical multiplexing provide the means for economically meeting the physical and electrical constraints imposed on the designer of a multiwell tester. Matrix cards provide parallel connection of test probes from several test stations to one set of switch cards. This enables several test stations to share a single set of test circuitry in such a way that one board can be tested at one test station while other boards are loaded and unloaded at other test stations. This parallel connection is accomplished despite the enormous bulk of cabling that must converge on and be connected to the switch cards if such parallel connection is to be achieved. In addition, means is provided for mechanically multiplexing the circuit boards to be tested so that a board at only one test station at a time is electrically connected to the common set of switch cards. This method of electrically isolating the several test stations of the tester makes multiwell testing economical; the achievement of parallel connection through the use of matrix cards makes it physically practical to connect more than one test station to a tester.

The tester also utilizes particularly efficient testing procedures. The choice of testing procedures enables the tester to perform tests with sufficient speed to make practical the sharing of one set of switch cards among several test stations. In order for a multiwell tester to be useful, test speed must be sufficient that the tester is available for testing a board at each test station as soon as the board has been loaded in place of the previous board.

The tester also utilizes particularly economical switch cards. Each switch card need have only a minimum amount of decoding circuitry. This is made possible by the advantageous choice of certain aspects of the testing procedure. The testing procedure also provides data in a form which is particularly well adapted for further processing. The combination of storing first hits in conjunction with the scanning of only those test points above the source point results in a linked list of electrical continuity data.

What we claim is:

Claims

1. A tester for testing selected test points on printed circuit boards, comprising: means for applying electrical test signals to selected test points on a circuit board and measuring the electrical response thereto, means for ordering the test points in a defined sequence, means for sequencing the application of test signals to successive test points, and means for sequencing the sensing of a signal at test points subsequent to the point at which a signal is applied until a first response signal is found.

2. A tester as claimed in claim 1 wherein said sense sequencing means is operative to sense simultaneously at groups of test points, said ordering means comprises a series of switch cards, a set of test points being associated with each switch card, and wherein each of said groups includes no more than one test point from each of said switch cards.

3. A tester as claimed in claim 1 wherein the ordering means orders test points in a matrix form, said matrix having rows and columns, and wherein one switch card is associated with each column of the matrix.

4. A tester as claimed in claim 3 wherein at most one switch on each switch card is closed at any time.

5. A tester as claimed in claim 3 wherein the sense sequencing means is operative to sense simultaneously those tests points in the same row as the stimulus point which are above the stimulus point, and to sense simultaneously all test points in a row for those rows above the row with the stimulus point.

6. Apparatus for testing circuit boards at a plurality of test points, said testing apparatus comprising: a set of switches, at least 2 sets of test probes means for electrically connecting in parallel corresponding ones of the test probes from one set of test probes with corresponding ones of the test probes from another set of test probes, and further connecting these parallel connected test probes to corresponding switches of the set of switches, a contact control means associated with each set of test probes, each of said contact control means being adapted to control the relative position of a circuit board to be tested and the set of test probes, so as to control electrical contact between the circuit board and the test probes, and thereby be capable of electrically isolating one of the sets of test probes from circuit boards to be tested at another set of test probes.

7. Apparatus as in claim 6 wherein said contact control means comprises: means for mounting a board for testing while maintaining said board out of contact with said probes, and means for selectively bringing said board into contact with said probes for testing.

8. Apparatus as in claim 7 wherein said means for electrically connecting in parallel comprises a set of matrix cards, each of said matrix cards comprising a printed circuit card having a set of connections at one edge connected to the set of switches, and sets of connections on at least 2 other edges, each connected to a set of test probes.

9. Apparatus as in claim 8 wherein said matrix cards have conductors on one face of the cards connecting to switches, conductors on the other face of the cards connecting to test probes, and wherein these two sets of conductors are interconnected by plated-though holes.

10. Apparatus as in claim 9 wherein the connections from the sets of test probes to the matrix cards comprise cables terminating in connectors which attach to edges of the matrix cards, and wherein said plated-through holes are arranged along two lines which run diagonally across said conductors, whereby the resulting orientation of the connectors minimizes twists in the cables.