JPH02293678A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To easily evaluate and analyze at a speed limit area in a short time by providing a test terminal, a multiplexer circuit which inputs a logic signal and plural clock signals, and input/output terminals. CONSTITUTION:When the test terminal T is at a high potential, a test state is entered, and the data of a data bus 22 is inputted to the decoder circuit 1 of the multiplexer 20, so that an output selected by the circuit 1 is 'H' and the other output is 'L'. If the output (a) of the circuit 1 is 'H' and the other output is 'L', the output of a NAND gate 101 which is the output of the logic signal of a critical path circuit 2 is received by an inverter gate 6 and outputted from an input/output terminal A through Nch transfer gates 55 and 62. Similarly, the gate signal of a clocked inverter gate 107 which conflicts with the logic signal of the circuit 2 is received again by an inverter 7 and outputted from an input/output terminal B through Nch transfer gates 56 and 64 and the signal of the terminals A and B are measured to evaluate the circuit 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a measurement test circuit for a critical bus section existing therein.

[Conventional technology]

Conventionally, it has not been possible to directly measure the critical path portion of this type of semiconductor integrated circuit (hereinafter referred to as IC).
Connect the IC to a dedicated test equipment, apply data to the input terminal of the IC to operate it, inspect the signal output from the output terminal of this IC, change the power supply voltage, operating speed, etc.
The operating limits of the IC itself were measured.

[Problem to be solved by the invention]

The conventional measurement method described above is difficult to overcome due to factors such as increased capacitance and resistance inside the chip due to the large size of current IC chips, increased operating speed, and deterioration of speed characteristics due to assembly of plastic packages, etc. It takes time to analyze the limits of the operating speed of the completed IC.

For this reason, it has the disadvantage that it is extremely difficult to develop high-speed ICs in a short period of time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit in which the above-mentioned drawbacks can be solved and evaluation and resolution can be easily and quickly carried out.

[Means to solve the problem]

The configuration of the semiconductor integrated circuit of the present invention includes a test terminal to which a test signal is input, a multiplexer circuit to which a logic signal of a critical bus section and a plurality of clock signals competing with the logic signal are input, and a designation made by the multiplexer circuit. The device is characterized by having an input/output terminal that outputs a pair of logic signals and a clock signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a part of a semiconductor integrated circuit according to an embodiment of the invention, and FIG. 2 is a block diagram showing other parts of a semiconductor integrated circuit according to an embodiment of the invention. Arrow 30 in Figure 1
35 are respectively connected to arrows 30 to 35 in FIG. 2, and FIG. 1 and FIG. 2 together form a block diagram of a semiconductor integrated circuit according to an embodiment of the present invention. 1 and 2K, the semiconductor integrated circuit of this embodiment includes an input signal terminal T, a control circuit 21 to which a data bus 22 is input, a decoder circuit 1, and critical path circuits 2, 3. 4 and
It is configured to include a multiplexer 20, transfer gates 55 to 63, and inverter gates 6, 7 to 11. Here, the input terminal T is a test terminal, the data bus 22 is a data bus within the IC, the circuit 21 is a control circuit for inputting data on the data bus 22 to the multiplexer 20, and the multiplexer 20 is a decoder. The critical bus circuits 2, 3 are composed of circuit 1 and Nch} lance 7 agates 55 to 60. 4
A plurality of input/output terminals A and B exist in each part of the IC, and input/output terminals A and B are terminals for outputting a logic signal that is information on the critical path specified by the data bus 22 and a clock signal that competes with the logic signal.

Now, when the test terminal T is at a low potential (hereinafter referred to as @L''), the Nch} transfer gates 62 and 64 are non-conductive,
Nch} lance 7 agate 61.63 is conductive, so terminals A and B are used as normal IC output buffers. Further, the Nch transfer 1 gates 65 to 67 of the control circuit 21 are also in an OFF state, and the data bus 22 is not input to the multiplexer 20. When the test terminal T is at a high potential (hereinafter referred to as @H''), it is not in the test state.
The Nch transfer gates 62 and 64 become conductive. Further, since the Nch transfer gate of the control circuit 21 is turned on, data on the data bus 22 is input to the multiplexer 20. Data on the data bus 22 is input to the decoder circuit 1. In this decoder circuit 1, the selected output is ``H'' and the other outputs are 1L''. Suppose that the output a of the decoder circuit 1 is ``H'' and the other outputs are 1L''K. , critical path circuit 2
The output of the NAND gate 101, which is the output of the logic signal, is received again by the inverter gate 6, passes through the Nch transfer gates 55 and 62, and is outputted to the input/output terminal A. Similarly, the gate signal of the clocked inverter gate 107 that competes with the logic signal of the critical path circuit 2 is received again by the inverter 7, passes through the Nch transfer gate 56, 64, and is sent to the input/output terminal B.
Output. By measuring the signals at terminals A and B, the critical path circuit 2 can be evaluated. Similarly, by changing the data on the data bus 22, the critical bus circuits 3 and 4 can be evaluated.

In this embodiment, by outputting the information of the critical bus section directly from the terminal, the speed limit section can be easily evaluated and analyzed using a dedicated test device in a short time.

〔Effect of the invention〕

As explained above, the present invention has the advantage that it is possible to output information on critical bus sections of various parts within an IC chip from the terminals during a test state, and therefore evaluation and analysis of speed bottlenecks can be performed easily and in a short period of time. There is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a semiconductor integrated circuit according to an embodiment of the invention, and FIG. 2 is a block diagram of other parts of the semiconductor integrated circuit according to an embodiment of the invention. 1... Decoder circuit, 2, 3, 4...
...Critical path circuit, 5, to 11...
...Inverter game}, 55, to 67...N
ch}Transfergate, 101. ~106...
...NAND gate, 107...Clocked inverter gate, T...Test terminal, 22...
...Data bus, 21...Control circuit for switching input data of multi-flexor, 20...Multiplexer, A...Critical path section logic signal output terminal, B. ...Critical path section clock signal output terminals, 30, to 35...Arrows. Agent: Patent Attorney Susumu Uchihara

Claims (1)

[Claims] a test terminal for inputting a test signal for controlling whether to enter a test state or an operating state; a multiplexer circuit receiving a logic signal and a plurality of clock signals each competing with the logic signal; A semiconductor integrated circuit comprising a specified pair of logic signals and a terminal that outputs a clock signal.