JP2001267501A - Semiconductor integrated circuit and testing method for input characteristics using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which enables a test of its input characteristics in contact by only a small number of specific pins. SOLUTION: This semiconductor integrated circuit has a transfer gate 13 placed between an input pin a PIN1 and an input buffer 11, a transfer gate 14 placed between an input pin PIN2 and an input buffer 12, and a transfer gate 15 placed between the input PIN1 and the input buffer 12. An inverter circuit 16 is connected to a control pin PINy, one control terminal of each transfer gate 13-15 is connected to the input of an inverter circuit 16, and the other terminal of each transfer gate 13-15 is connected to the output of the inverter circuit 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and an input characteristic testing method used therewith, and more particularly to a semiconductor integrated circuit mounted on a computer device or other electronic device, which can be easily tested by an LSI (large-scale integrated circuit) inspection device. Circuit.

[0002]

2. Description of the Related Art Conventionally, in order to inspect a characteristic test of a semiconductor integrated circuit by an inspection apparatus, signals input from input pins PIN1, PIN2,..., PINN are input to an input buffer as shown in FIGS. Propagated to flip-flops (hereinafter, referred to as F / F) 63 and 64 via 61 and 62, the input pins PIN1, PIN2,.
A signal must be input every time.

[0003] An inspection method of this kind is disclosed in JP-A-6-5 / 1994.
There is a technique disclosed in JP-A-8994. In the technology described in this publication, an output circuit test method for an LSI is implemented with a circuit configuration as shown in FIG. The circuit configuration in this case is a CMOS (Complementary Me
tal Oxide Semiconductor) circuit is used.

The LSI chip 7 has an input terminal 71 for testing.
-1 to 71-n, a control circuit 72 connected to the control circuit 72, a switch decoder circuit 73, a scan circuit 74, and output terminals 77-1 to 7-1 of the LSI chip 7.
Switch circuits 76-1 to 76-n connected to 77-n
And output level sense terminals 78 connected to the output terminals 77-1 to 77-n via the switch circuits 76-1 to 76-n.

Hereinafter, the operation of the LSI chip 7 will be described. The control circuit 72 has input terminals 71-1 to 71-
In response to the input from n, the selection control signals D1 to Dn are output to the switch decoder circuit 73, and the output logic control signal SC is output to the scan circuit 74.

The switch decoder circuit 73 includes a control circuit 72
, Sn2,..., Sn2,..., S1 ′, S2, S2 ′,.
Output n '.

The LSI chip 7 includes a switch circuit 76-1.
To 76-n are the switch selection signals S given to the control terminals.
1, S1 ', S2, S2',..., Sn, and Sn 'are turned on and off depending on the logic level, so that one of the plurality of switch circuits 76-1 to 76-n is turned on. , The corresponding output terminal 77-1 to 77-n
Is output to the output level sense terminal 78, and by observing this, the output terminals 77-1 to 77-
n output potentials can be tested.

The truth value of the switch decoder circuit 73 is shown in FIG.
As shown in FIG. From this, the output terminal 77-1
For the measurement of the voltage levels of ~ 77-n, a non-contact electrical investigation is performed except for some control inputs.

However, this test method corresponds to only the output circuit test of the LSI, and cannot be used for the test on the input side. The switch selection signals S1 ', S
“′” Of 2 ′ and Sn ′ are switch selection signals S
1, S2, and Sn are shown in FIG.
Reference numerals 75-1 to 75-n indicate output circuits.

[0010]

In recent years, with the increase in the scale of gates, the number of pins of the LSI has been increasing, and the demand for increasing the number of pins has been increasing.
In order to bring out the performance of SI, TAB (Tape Au
Applications such as a tomated bonding technique and a bare chip mounting technique are being implemented.

In testing the input characteristics of such a multi-pin LSI, since the number of pins to be probed is large, an LSI inspection apparatus required for this is expensive, and the pins are arranged at the center of the chip. However, there is a problem that it may not be possible to probe all pins because of the appearance of an LSI.

Accordingly, an object of the present invention is to solve the above-mentioned problems and to provide a semiconductor integrated circuit capable of performing an input characteristic test by contacting only a specified few pins and an input characteristic test method used therefor. It is in.

[0013]

A semiconductor integrated circuit according to the present invention has first and second input pins and the first and second input pins.
And a first and a second input buffer for transmitting a signal from the first input pin, wherein the first and second input buffers are provided between the first input pin and the first input buffer. A transfer gate, a second transfer gate disposed between the second input pin and the second input buffer, and a second transfer gate disposed between the first input pin and the second input buffer. A third transfer gate, and the third transfer gate is configured to be in a conductive / non-conductive state exclusively with respect to the first and second transfer gates.

According to a method for testing the input characteristics of a semiconductor integrated circuit according to the present invention, first and second input pins and first and second input buffers for transmitting signals from the first and second input pins are provided. A method for testing input characteristics of a semiconductor integrated circuit, comprising: disposing a first transfer gate between the first input pin and the first input buffer;
A second transfer gate is provided between the input pin and the second input buffer, and a third transfer gate is provided between the first input pin and the second input buffer. The third transfer gate is made conductive / non-conductive exclusively to the first and second transfer gates.

That is, the semiconductor integrated circuit of the present invention has at least two or more input pins, and each of a P-channel transistor and an N-channel transistor is provided between the first input pin and the first input buffer. A first transfer gate having a drain input, a source output, and a gate as a control terminal is inserted, and a second transfer gate is inserted between the other second input pin and the input of the second input buffer. Inserting, connecting a third transfer gate between the first input pin and the input of the second input buffer, the third transfer gate being exclusively conductive to the first and second transfer gates, It has a circuit connection configuration that is in a non-conductive state.

In the semiconductor integrated circuit of the present invention, the first to third transfer gates are switched on and off by the control pins. In the case of normal use, the first and second transfer gates are turned on, and the third transfer gate is turned off.
F, the signal from the first input pin is propagated to the first input buffer via the first transfer gate, and the signal from the second input pin is transmitted to the second input buffer via the second transfer gate. To the input buffer.

At the time of inspection of the LSI, the first and second transfer gates are turned off by the control pin, the third transfer gate is turned on, and the signal from the first input pin is passed to the third transfer gate via the third transfer gate. 2 input buffer.

Thus, it is possible to inspect the characteristics of the first and second input buffers by measuring the voltage or current of the signal without contacting the second input pin. That is, a test of input characteristics, which was conventionally realized only by a contact test for all pins and all terminals, can be performed by contacting only a very small number of specific pins.

[0019]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention.
In FIG. 1, a semiconductor integrated circuit 1 includes input pins PIN1 and PIN1.
, A control pin PINy, input buffers 11 and 12, transfer gates 13 to 15, an inverter 16, and flip-flops (hereinafter referred to as F / F) 17 and 18.

In the semiconductor integrated circuit 1, the signal from the input pin PIN1 is transmitted to the input buffer 1 by the control pin PINy.
The input is switched to 1,12. Specifically, in the semiconductor integrated circuit 1, a transfer gate 13 is disposed between the input pin PIN1 and the input buffer 11, and the input pin PIN
Transfer gate 14 between input buffer 12 and input buffer 12
And a transfer gate 15 is provided between the input pin PIN1 and the input buffer 12, so that the transfer gate 15 is exclusively connected to the transfer gates 13 and 14 in a conductive / non-conductive state. I have.

The semiconductor integrated circuit 1 switches ON and OFF of the transfer gates 13 to 15 by the control pin PINy. When the semiconductor integrated circuit 1 is normally used, the transfer gates 13 and 14 are turned on and the transfer gate 15 is turned off, so that the input pin PI
The signal from N1 is propagated to the input buffer 11 via the transfer gate 13, and the signal from the input pin PIN2 is transmitted to the input buffer 1 via the transfer gate 14.
2 is propagated.

When testing the semiconductor integrated circuit 1, the transfer gates 13 and 14 are turned off by the control pin PINy.
F, the transfer gate 15 is turned on, and the signal from the input pin PIN1 is transmitted to the input buffer 12 via the transfer gate 15. by this,
By measuring the voltage or current of the signal without touching the input pin PIN2, the characteristics of the input buffers 11 and 12 can be inspected.

FIG. 2 is a diagram showing the operation of the semiconductor integrated circuit according to one embodiment of the present invention during normal use. FIG. 2 shows an MO as a semiconductor integrated circuit 4 according to an embodiment of the present invention.
S (metal oxide semiconductor)
5 shows an example in which an (or) type transistor is used.

The semiconductor integrated circuit 4 inputs the respective drains of the P-channel MOS transistor and the N-channel MOS transistor connected to the input pin PIN1, outputs a source, and outputs a source. A buffer 41 and a transfer gate 46 to which the drains of the P-channel MOS transistor and the N-channel MOS transistor are input, the source is output, and the gate is a control terminal
And a P-channel MOS connected to the input pin PIN2
Each of the transistors and the N-channel MOS transistor has its drain input, its source output and a transfer gate 45 having a gate as a control terminal, an input buffer 42, inputs PIN3 to PINn, and a control pin PI
The inverter circuit 47 includes Ny, a P-channel MOS transistor and an N-channel MOS transistor, and F / Fs 50 to 52.

In the semiconductor integrated circuit 4, the input pin PIN1 is connected to the input of the transfer gate 44, the output of the transfer gate 44 is connected to the input of the input buffer 41, and the input pin PIN2 is connected to the input of the transfer gate 45. , The output of the transfer gate 45 is connected to the input of the input buffer 42, the input of the transfer gate 44 is connected to the input of the transfer gate 46, the output of the transfer gate 45 is connected to the output of the transfer gate 46, and the control PINy and The input of the inverter circuit 47 and the control terminals 44A, 4A of the transfer gates 44, 45
5A is connected to the control terminal 46B of the transfer gate 46, and the output of the inverter circuit 47 is connected to the control terminals 44B, 45B, 46A of the transfer gates 44 to 46.

The semiconductor integrated circuit 4 has transfer gates 44 to 46 when testing an input buffer connected to two input signals. Further, even when the semiconductor integrated circuit 4 has many input pins, as shown in FIG. 2, a transfer gate 48 is provided between the input pin PINn and the input buffer 43, and the transfer gate 46 is added to the transfer gate 46. This can be dealt with by disposing a transfer gate 49 between the transfer gate and the transfer gate.

FIG. 3 is a diagram showing an outline of measurement of a semiconductor integrated circuit by an inspection apparatus according to one embodiment of the present invention, and FIG. 4 is a diagram showing an operation at the time of inspection of a semiconductor integrated circuit according to one embodiment of the present invention. is there. The operation of the embodiment of the present invention will be described with reference to FIGS.

In a case where the semiconductor integrated circuit 4 is normally used (a signal is input to each input pin and propagated to an input buffer) such that the semiconductor integrated circuit 4 is mounted on a computer device (not shown), FIG.
As shown in the figure, the logic level “1” is output from the control pin PINy.
Is input, the output of the inverter circuit 47 becomes a logical level “0”, the transfer gates 44 and 45 are turned on, and the transfer gate 46 is turned off.

For this reason, the signal of the logic level "0" or "1" entered from the input pin PIN1 is propagated from the transfer gate 44 to the input buffer 41, and the logic level "0" or "1" entered from the input pin PIN2. 1 "
From the transfer gate 45 to the input buffer 42
To the F / F 50,
The signal is propagated to each of 51.

The characteristic test of the semiconductor integrated circuit 4 is performed by the inspection device 3
3, the measurement pins 3a and 3b of the inspection device 3 are brought into contact with the signal pins 2a and 2b of the LSI 2 in a one-to-one relationship, and a voltage or a current is applied from the inspection device 3 side. The LSI 2 is inspected by measuring the voltage or the current of the signal pins 2a and 2b of the LSI 2.

However, the measuring pin 3 of the inspection device 3
If the number of the signal pins 2a and 2b of the LSI 2 is larger than the number of the signal pins 2a and 3b, they cannot be brought into a one-to-one relationship. Therefore, as shown in FIG. ”, The output of the inverter circuit 47 becomes logic level“ 0 ”, and the transfer gate 4
4 turns ON, and the transfer gate 46 turns OFF. As a result, the voltage or current of the signal of the logic level “0” or “1” input from the input pin PIN1 is transmitted from the transfer gate 44 to the input buffer 41, and the input characteristics of the input buffer 41 can be inspected.

When a logic level "0" is input from the control pin PINy, the transfer gates 44 and 45 are turned off and the transfer gate 46 is turned on.
As a result, the logic level "0" that has entered from the input pin PIN1 has not been brought into contact with the input pin PIN2.
Alternatively, the voltage or current of the signal of “1” is transmitted from the transfer gate 46 to the input buffer 42, and the input characteristics of the input buffer 42 can be inspected. Thus, the signal from the input pin PIN1 is input to the input buffer 41,
42 and can be propagated.

Further, when testing without contacting many input pins, as shown in FIG. 4, when a logic level "0" is input from the control pin PINy, the transfer gate 4
4, 45 and 48 are turned off and transfer gate 4
6, 49 are turned on.

As a result, the voltage or current of the signal of logic level "0" or "1" entered from input pin PIN1 is propagated from transfer gates 46 and 49 to input buffer 43 without contacting input pin PINn. , The input characteristics of the input buffer 43 can be inspected. With the above operation, the input characteristics of the plurality of input buffers 41 to 43 can be inspected from the input pin PIN1 by using the input signal switching circuit as described above.

FIG. 5 is a diagram showing the relationship between the logic level of the control pin and the voltage and current in one embodiment of the present invention.
FIG. 6 is a diagram showing the relationship between the voltage of the control pin and the voltage of the control terminal of the transfer gate according to one embodiment of the present invention. FIG. 7 is a diagram illustrating the state of the control pin voltage and the transfer gate according to one embodiment of the present invention. FIG. The operation of the semiconductor integrated circuit 4 according to one embodiment of the present invention will be specifically described with reference to FIGS.

In the semiconductor integrated circuit 4, the input pin P
A transfer gate 44 having the drains of the P-channel MOS transistor and the N-channel MOS transistor connected to IN1 as inputs, the respective sources as outputs, and the respective gates as control terminals 44A and 44B; Is connected to the input of the input buffer 41.

In the semiconductor integrated circuit 4, the drains of the P-channel MOS transistor and the N-channel MOS transistor connected to the input pin PIN1 are input, and the sources are output.
A transfer gate 46 having respective gates as control terminals 46A and 46B, and an output of the transfer gate 46 is connected to an input of the input buffer 42.

Further, in the semiconductor integrated circuit 4, the respective drains of the P-channel MOS transistor and the N-channel MOS transistor connected to the input pin PIN2 are input, the respective sources are output, and the respective gates are control terminals. Transfer gates 45A and 45B;
And the input of the input buffer 42 are connected.

Further, in the semiconductor integrated circuit 4, an inverter circuit 47 composed of a P-channel MOS transistor and an N-channel MOS transistor is used.
Is input to the control terminals 44 of the transfer gates 44 to 46.
A, 45A, 46B and control pin PINy, and outputs the output of inverter circuit 47 to transfer gates 44-4.
6 control terminals 44B, 45B, 46A.

The semiconductor integrated circuit 4 has transfer gates 44 to 46 when testing an input buffer connected to two input signals. Also, when the semiconductor integrated circuit 4 has many input pins, as shown in FIG. 2, a transfer gate 48 is provided between an arbitrary input pin PINn and an input of the input buffer 43, and the input of the transfer gate 48 Is connected to PINn, the output is connected to the input of the input buffer 43, and the control terminal 48A of the transfer gate 48 is connected to the inverter circuit 4.
7 and the control terminal 48B of the transfer gate 48 is connected to the output of the inverter circuit 47.

Further, the semiconductor integrated circuit 4 has a transfer gate 49, an input of the transfer gate 49 is connected to an output of the transfer gate 46, and an output of the transfer gate 49 is connected to an input of the input buffer 43. The control terminal 49A of the transfer gate 49 is connected to the output of the inverter circuit 47.
Is connected to the input of the inverter circuit 47.

The above-described semiconductor integrated circuit 4 is mounted on a computer device or electronic equipment (not shown), and a voltage or current is input to each input pin of the semiconductor integrated circuit 4 as shown in a voltage or current value table for a logical value. When the signal is propagated to the input buffer in the semiconductor integrated circuit 4, as shown in FIG.
When a voltage of 5 V or a current of 1 mA is input, the output of the inverter circuit 47 becomes 0 V, and this voltage turns on the transfer gates 44 and 45 and turns off the transfer gate 46 (see FIGS. 5 to 7). ).

Therefore, a voltage of 0 V or 2.5 V input from the input pin PIN1, or 0 mA or 1
An input signal such as a current of mA is transmitted to the input of the input buffer 41 via the transfer gate 44, and the input pin P
An input signal such as a voltage of 0 V or 2.5 V or a current of 0 mA or 1 mA coming from IN2 is transmitted to the input of the input buffer 42 via the transfer gate 45.

Thus, the output voltage or output current of the input buffer 41 is determined, and this voltage or current is
Propagated to the data input terminal of F50. Similarly, the output voltage or output current of the input buffer 42 is determined, and this voltage or current is transmitted to the data input terminal of the F / F 51.

The characteristic test of the semiconductor integrated circuit 4 is performed by the inspection device 3
3, the measurement pins 3a and 3b of the inspection device 3 are brought into contact with the signal pins 2a and 2b of the LSI 2 in a one-to-one relationship, and a voltage or a current is applied from the inspection device 3 side. The LSI 2 is inspected by measuring the voltage or current of the signal pins 2a and 2b of the LSI 2.

However, the measuring pin 3 of the inspection device 3
If the number of the signal pins 2a and 2b of the LSI 2 is larger than the number of the signal pins 2a and 3b, the contact cannot be made in a one-to-one relationship. Therefore, as shown in FIG.
Is input or the current of 1 mA is input, the output of the inverter circuit 47 becomes 0 V, and this voltage turns on the transfer gate 44 and turns off the transfer gate 46.

Therefore, a voltage of 0 V or 2.5 V input from the input pin PIN1, or 0 mA or 1
A signal such as a current of mA is transmitted to the input of the input buffer 41 via the transfer gate 44,
One input characteristic can be tested.

On the other hand, when a voltage of 0 V or a current of 0 mA is input from the control pin PINy, the output of the inverter circuit 47 becomes 2.5 V, and the transfer gates 44 and 45 are turned off by this voltage, and the transfer gate 46 is turned off. It becomes conductive. Therefore, the input pin PIN
2, a signal such as a voltage of 0 V or 2.5 V or a current of 0 mA or 1 mA input from the input pin PIN1 is transmitted to the input of the input buffer 42 via the transfer gate 46, and 42 input characteristics can be tested.

As described above, the signal from the input pin PIN1 can be switched to the input buffers 41 and 42.
In the case of inspecting the semiconductor integrated circuit 4 without contacting many input pins, as shown in FIG.
When a voltage of 0 V or a current of 0 mA is input from INy, the output of the inverter circuit 47 becomes 2.5 V, and the transfer gates 44, 45, and 48 become non-conductive,
The transfer gates 46 and 49 become conductive.

Therefore, the input pin PINn is not brought into contact with the input pin PINn.
A signal such as a voltage of V or a current of 0 mA or 1 mA is transmitted to the input of the input buffer 43 via the transfer gates 46 and 49, and the input characteristics of the input buffer 43 can be inspected. With the above operation, the input characteristics of the plurality of input buffers 41 to 43 can be inspected from the input pin PIN1 by using the input signal switching circuit.

As described above, the inspection of the semiconductor integrated circuit 4 can be performed by contacting only a few signal pins 2a and 2b of the LSI 2, so that the signal pins 2a and 2b of the LSI 2 can be inspected.
An inexpensive inspection device 3 having fewer measurement pins 3a and 3b can be used, and a multi-pin LSI that is not caught by a pin neck can be developed.

[0052]

As described above, according to the present invention, a first transfer gate is provided between a first input pin and a first input buffer, and a second input pin and a second input buffer are provided. And a second transfer gate is arranged between
A third transfer gate is provided between the first input pin and the second input buffer, and the third transfer gate is in an exclusive conductive / non-conductive state with respect to the first and second transfer gates. By configuring so that
There is an effect that the input characteristic test can be performed by contacting only a very small number of specific pins.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing an operation of the semiconductor integrated circuit according to one embodiment of the present invention during normal use.

FIG. 3 is a diagram showing an outline of measurement of a semiconductor integrated circuit by an inspection apparatus according to one embodiment of the present invention.

FIG. 4 is a diagram showing an operation at the time of inspection of a semiconductor integrated circuit according to one embodiment of the present invention.

FIG. 5 is a diagram showing a relationship between a logic level of a control pin and a voltage and a current in one embodiment of the present invention.

FIG. 6 is a diagram showing a relationship between a voltage of a control pin and a voltage of a control terminal of a transfer gate in one embodiment of the present invention.

FIG. 7 is a diagram showing a relationship between a voltage of a control pin and a state of a transfer gate according to one embodiment of the present invention.

FIG. 8 is a diagram showing a circuit configuration of a semiconductor integrated circuit according to a conventional technique.

FIG. 9 is a diagram showing an operation of a semiconductor integrated circuit according to the related art.

FIG. 10 is a diagram showing another circuit configuration of a semiconductor integrated circuit according to the related art.

FIG. 11 is a diagram showing truth values of the switch decoder circuit of FIG. 10;

[Explanation of symbols]

1, 4 Semiconductor integrated circuit 2 LSI 2a, 2b 3 Inspection device 3a, 3b 11, 12, 41 to 43 Input buffer 13 to 15, 44 to 49 Transfer gate 16, 47 Inverter circuit 17, 18, 50 to 52 Flip-flop 44A , 44B, 45A, 45B, 46A, 46B, 4
8A, 48B, 49A, 49B Transfer gate control terminals PIN1, PIN2,..., PINn input pin PINy control pin

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G003 AA07 AH04 2G032 AA01 AD01 AK11 AK14 AL05 5F038 BE01 DF17 DT02 DT05 DT08 EZ20 5J056 AA01 BB53 BB60 CC00 CC14 DD13 DD28 EE03 FF10 HH04 KK03 HKK KK03 9A001 BB03

Claims (10)

[Claims] 1. A semiconductor integrated circuit comprising: first and second input pins; and first and second input buffers for transmitting signals from the first and second input pins, wherein A first transfer gate disposed between the input pin and the first input buffer; and a second transfer gate disposed between the second input pin and the second input buffer. , A third transfer gate disposed between the first input pin and the second input buffer, wherein the third transfer gate is provided with respect to the first and second transfer gates. A semiconductor integrated circuit configured to be exclusively in a conductive / non-conductive state. 2. The semiconductor device according to claim 1, wherein said third transfer gate is exclusively turned on / off with respect to said first and second transfer gates in response to a control signal inputted from outside. 2. The semiconductor integrated circuit according to claim 1, wherein: 3. The first transfer gate inputs the drains of a P-channel MOS transistor and an N-channel MOS transistor connected to the first input pin, outputs a source, and controls a gate as a control terminal. Wherein the second transfer gate inputs the respective drains of a P-channel MOS transistor and an N-channel MOS transistor connected to the second input pin, outputs a source, sets a gate as a control terminal, The third transfer gate is a P-channel type MO
3. The semiconductor integrated circuit according to claim 1, wherein a drain of each of the S transistor and the N-channel MOS transistor is input, a source is output, and a gate is used as a control terminal. 4. In normal use, the first and second transfer gates are turned on by an external control signal, the third transfer gate is turned off, and a signal from the first input pin is turned on. To the first input buffer via the first transfer gate, and to propagate the signal from the second input pin to the second input buffer via the second transfer gate. 4. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit is configured as described above. 5. During inspection, the first and second transfer gates are turned off by an external control signal, the third transfer gate is turned on, and a signal from the first input pin is turned on. 5. The semiconductor integrated circuit according to claim 2, wherein the signal is propagated to the second input buffer via the third transfer gate. 6. 6. An input characteristic test method for a semiconductor integrated circuit including first and second input pins, and first and second input buffers for transmitting signals from the first and second input pins. A first transfer gate is provided between the first input pin and the first input buffer, and a second transfer gate is provided between the second input pin and the second input buffer.
And a third transfer gate is provided between the first input pin and the second input buffer, and the third transfer gate is provided with the first and second transfer gates. An input characteristic test method characterized in that a conduction / non-conduction state is exclusively established with respect to. 7. The method according to claim 7, wherein said third transfer gate is exclusively turned on / off with respect to said first and second transfer gates in response to a control signal inputted from outside. 7. The input characteristic test method according to claim 6, wherein: 8. The first transfer gate inputs the respective drains of a P-channel MOS transistor and an N-channel MOS transistor connected to the first input pin, outputs a source, and controls a gate as a control terminal. Wherein the second transfer gate inputs the respective drains of a P-channel MOS transistor and an N-channel MOS transistor connected to the second input pin, outputs a source, sets a gate as a control terminal, The third transfer gate is a P-channel type MO
8. The input characteristic test method according to claim 6, wherein a drain of each of the S transistor and the N-channel MOS transistor is input, a source is output, and a gate is used as a control terminal. 9. During normal use, the first and second transfer gates are turned on by an external control signal, the third transfer gate is turned off, and a signal from the first input pin is turned on. To the first input buffer via the first transfer gate, and to propagate the signal from the second input pin to the second input buffer via the second transfer gate. 9. The input characteristic test method according to claim 7, wherein the input characteristic test is performed. 10. During inspection, the first and second transfer gates are turned off and the third transfer gate is turned on by an external control signal,
The input according to any one of claims 7 to 9, wherein a signal from the first input pin is propagated to the second input buffer via the third transfer gate. Characteristic test method.