JPS6113349A - Microprocessor analyzer - Google Patents

Abstract

PURPOSE:To prevent wrong recognization of the executed result of an 8087CPU when an active program is run, by storing active requests (NMI) arrived while a BUSY signal is ''H'' by means of the 8087CPU until the BUSY signal becomes ''L'' and giving the NMI to the 80186CPU after the BUSY signal becomes inactive. CONSTITUTION:An 80186 and 8087 CPUs on a target 10 can be removed from sockets 11 and 12 and connectors 21 and 22 at a POD side are respectively mounted on each socket. The connectors 21 and 22 are respectively connected with an 80186 and 8087 chips mounted on a POD20 through cables 23 and 24 and the target is actuated by means of the POD20 side 80186 and 8087 chips. An active request control circuit 27 has a function which temporarily stores an active request given from the main body side while the 8087CPU executes an instruction and gives the request to the 80186CPU at a permissible time.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical field to which the invention pertains) The present invention relates to a microprocessor analyzer, and more specifically, in a microprocessor that uses two microprocessors in pairs, one microprocessor (
The reception of active requests for rice while the co-processor (co-p, called rocea@Or) is in operation is related to control.

(Prior Art) So-called microprocessor analyzers, which test microprocessor-applied equipment using in-circuit emission techniques, are well known. Such a microprocessor analyzer is connected to a target microprocessor application device (hereinafter referred to as a target) via a probe.

This probe (usually called POD) includes Yuichige,
It is equipped with the same type of microprocessor as the one built into the target, and a removable socket is used to remove the microprocessor from the target during testing.The connector from the POD is connected to it. However, the microprocessor on the POD operates the target on its behalf.

By the way, there are various types of microprocessors that can be incorporated into the target depending on the purpose.

For example, Intel's 16-bit microprocessor 1APX 186 is one of them. This microprocessor functions as a central processing unit (hereinafter referred to as CPU).
186 chip and 8087 chip used in conjunction with this,
It is sometimes used in combination with Pugo.

Figure 2 shows the 80186 chip and 8087 chip on the POD.
8087 CPU 2
2 is the 80186 CPU while monitoring the Qsl'' and sO (key status signal) of the 80186 CPU 21.
A similar instruction briefetch is performed following the PU. In this case, the 8087 CPU executes the escape (ESC) instruction only when it is decoded, and does not read or execute any other instruction codes. Here, the busy (BUSY) terminal of the 80B7 CPU, which is connected to the test terminal (five liver terminals) of the 80186CPH, is at the 'H' level only while the 8087 is executing an instruction, and gives a monitor signal to the 80186. .

In this case, there are the following problems. If an active request (NMI) is input while the 8087 is executing an instruction, that is, when the BUSY signal is "H", the instruction of the 8087 is interrupted because the NMI is accepted. After NMI reception, the active program will run! The active program is constantly prefetched and imported into the 1180186 and 8087, and when the 80186 returns from NMI, the ESC command that was inside the 8087 is not left behind, and the 8087 is It is possible to forget the ESC command that was interrupted. This leads to a misunderstanding of the calculation result of the 8087 after returning to the active state, resulting in an extremely inconvenient problem.

(Object of the Invention) The object of the present invention is to solve such problems, and to
NMI requests that arrive while the signal is at ++H++ level are stored until BUSY reaches IILIIK,
80186 CP after BUSY becomes inactive
The present invention provides an icroprocessor and analyzer designed to control active requests to provide UK NMI.

(Summary of the Invention) In order to achieve the above object, the present invention utilizes a coprocessor (data processing using a microprocessor).
In contrast to K, P, which is equipped with the same type of microbucks,
In a microprocessor analyzer that is equipped with an OD and tests the operation of a target using an in-circuit electronic system, when an active request arrives, the coprocessor performs a coprocessor, but if an instruction is not currently being executed, the active request is directly accepted. an active request control circuit for controlling the active request so that it is stored until the first execution is completed while the coprocessor is executing an instruction, and the active request is accepted and processed at the time when the execution of the first instruction is completed. It is characterized by the following:

(Example) The present invention will be described in detail below using the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In the same figure, 1
0 is the target, the POD of the 20-microbe pset analyzer.

80186 CPU and 8087 C on target 10
The PU is removed from the sockets) 11.12, and the POD side connectors 21.22 are attached to each socket. Connector 21.22 connects to POD via cable 23.24
The CPU 80186 and 80 on the POD 20 side are connected to the 80186 and 8087 installed in the POD 20.
87 K activates the target.

POD 20 uses this 80186 and 8087 CP
! 80186 chip 25 and 8087 chip 2 including U
6, and an active request control circuit 27. The POD 20 is connected to the main body of a microprocessor analyzer (not shown) via a cable 28.
It is configured to allow transmission and reception of signals and data. P.O.D.
80186 of 20.

The 8087 executes the corresponding program according to instructions from the main body as necessary.

The active request control circuit 27 8087 has a function of temporarily storing an active request given from the main body side during instruction execution and then giving it to the 80186 at a permitted time.

FIG. 3 is a block diagram showing details of this active request control circuit 27. In the same figure, 31 to 34 are J
-, flip 7o, flip (hereinafter abbreviated as FF), each F
The J and K input terminals of F are connected to the Q and 74 output terminals of the preceding FF, and the J and K input terminals of FF31 are both connected to the common line. Further, the clock terminals CP of the FFs 31, 33 and 34 are supplied with the fifth clock cycle signal ζ of the bus cycle, and the clock terminal CP of the FF 32 is supplied with an image signal via an inverter 35.

Furthermore, since the output of the gate 36 is given to the preset terminal P of FF31, the P terminals of py32, 33.34 are +5V.
K is pulled up. On the other hand, the clear terminal CK of FF 31 and 32 is given the output of the gate 41,
, 34 are supplied with a clock synchronization signal R8TB. This image signal is a clock synchronization signal for the reset input of the 80186 CPU.

The gate signal and the output signal of the gate 40 are input to the gate 41, and the Q output of the FF 34 and the Q output of the nine FF 32 are applied to the gate 4o via the inverter 39.

Gate 38 receives the output of FF 32 and the output of gate 37, and its output is an active request signal ACT.
It is given to the 80186 CPU as VREQ l.

An active request ACTVREQ applied from the main body side and an image signal via an inverter 35 are applied to the gate 37. Also, the gate 36 has ACTVREQ
and BUSY are being guided.

The operation in this configuration will now be described with reference to the time chart of FIG. FF 3:3.34 is first cleared by R8TB, then FF31.32.33
The Q output of
The ILI+ level and the output of the FF 34 are at the °°■° level in the figure. BUSY is “L” (
The 2m head signal with BUSY at "H'" level does not pass through the input OR gate 36, but passes through gates 37 and 38 and is ACT.
It is output directly as the VREQ' signal.

Next, BUSY is IIHI+ (Yogoga I+LI+)
At the level, the gate 37 outputs the output of the inverter 35 +
+H++, the other gate 36 is opened, and the output presets the FF 31, so the Q output of the FF 31 goes to the ゛°H°° level as shown in Fig. 4(b). This output is sent to FF32 at the rising edge of BUSY, and the Q output of FF32 is input as shown in the same figure (G).
It becomes IH1+ level.

Here, the output of pF32 is held until the output of gate 41 ((b) in the figure) reaches the IILI+ level. F
When the Q output of F32 reaches the °'H' level, one input of gate 4o (output of gate 39) goes to IIL++ level, so it becomes open. Also, at this time FF
32's mackerel's fall is in FF 33! 7FF
The input is set to J of 34, and FF is set at the next enable.
The output of the gate 41 becomes IILI+ as shown in the same figure, and the output of the - gate 41 (the same figure) becomes °“L”.
, clear 32. At this time, the output power of FF32 is +
ACTV, which is the output of gate 38,
REQI ((b) in the same figure) becomes inactive.
' In this way, when BUSY is IILI+, 2m head
is sent directly to 80186 CPUK and BUSY
+H+t When o, double 〒m order is latched and BUOY
80186 CP only after becomes inactive
given to U.

(Effects of the Invention) As explained above, according to the present invention, the pOD is 80
NMI control between 186 and 8087 can be performed, and there is an effect that erroneous recognition of the 8087 execution result due to active program running can be easily prevented.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main parts of an embodiment of the microprocessor analyzer according to the present invention, FIG. 2 is a schematic block diagram showing the connection state of an 80186 chip and an 8087 chip, and FIG. FIG. 4, which is an embodiment diagram of the request control circuit, is a time chart for explaining the operation. 10... Dege, ), 20... pOD, 25...
80186 step, 26...8087 step, 27
...Active request control circuit, FF31 ~
34...Flip 70 reps, 35.39...Inverter, 36.37, 38.40.41...Gate.

Claims (1)

[Claims] For a target that uses a microprocessor that requires a coprocessor, a microprocessor analyzer that is equipped with a POD equipped with the same type of microprocessor and tests the operation of the target by in-circuit emulation, when an active request arrives, When the processor is not executing an instruction, active requests are directly accepted and processed; when the coprocessor is executing an instruction, the active requests are stored until the execution is completed, and when execution is finished, active requests are accepted and processed. A microprocessor analyzer characterized by comprising an active request control circuit for controlling the microprocessor analyzer.