JPS613440A - Plug-in package - Google Patents
Plug-in packageInfo
- Publication number
- JPS613440A JPS613440A JP12465284A JP12465284A JPS613440A JP S613440 A JPS613440 A JP S613440A JP 12465284 A JP12465284 A JP 12465284A JP 12465284 A JP12465284 A JP 12465284A JP S613440 A JPS613440 A JP S613440A
- Authority
- JP
- Japan
- Prior art keywords
- terminals
- lsi
- ground
- power
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
イ、産業上の利用分野
本発明は、半導体素子を収納固着するキャピテイ部を有
するセラミ、り基体の前記キャピテイの開口面と反対側
の面から多数のリードビンを引出した集積回路、％ＫＬ
ＳＩ用として多く用いられるプラグインパッケージに関
する。DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention provides a ceramic substrate having a capillary portion for storing and fixing a semiconductor element, and a large number of lead bins are pulled out from the surface opposite to the opening surface of the capity. integrated circuit, %KL
This article relates to a plug-in package that is often used for SI.
口、従来の技術
従来のこの種のプラグインパッケージは、第３図（ａ）
の上面図、同図（ｂ）の側面図、同図（Ｃ）の底面図に
示すように、ＬＳＩ素子を収納固着するキャビティ部を
有するセラミ、りの基体１と、前記キャビティ部に半導
体チップを収納し固着後、該キャビティの開口に蓋をし
封止するキャップ２とを有し、さらに１キャ、プの封止
面と反対側の面には多数のリード端子３が植設されてい
る。多数のリード端子３は、一般に、複数の信号端子と
複数のグランド及び電源端子よ多構成されている。Conventional technology A conventional plug-in package of this kind is shown in Fig. 3(a).
As shown in the top view, the side view in FIG. 2B, and the bottom view in FIG. After storing and fixing, the cap 2 covers and seals the opening of the cavity, and a large number of lead terminals 3 are implanted on the surface opposite to the sealing surface of the cap. There is. The large number of lead terminals 3 are generally composed of a plurality of signal terminals and a plurality of ground and power terminals.
ハ１発明が解決しようとする問題点
近年、これらのプラグインパッケージに実装されるＬＳ
Ｉ素子は大規模なものとなってきておシそれに供給され
るグランド電流や電源電流も大きなものとなっている０
従って、プラグインパッケージには多数のグランド端子
と電源端子が必要となってきている。しかし、パッケー
ジサイズが−定の場合、その端子数も一定であシ、この
中でグランド端子と電源端子の数が増えることは信号端
子数の減少を引きおこすことになる。従って、数十もの
グランド及び電源端子を要するような大電流ＬＳＩを実
装する場合には、信号端子は少数となる。また、この時
、信号端子数を増やそうとすると、パッケージのサイズ
が大きくなシ、パッケージをプリント配線基板等へ実装
する場合、大きな実装面積が必要になるという問題があ
った。C1 Problems that the invention attempts to solve In recent years, the LS implemented in these plug-in packages has
As I elements have become larger in size, the ground current and power supply current supplied to them have also become larger.
Therefore, plug-in packages require a large number of ground terminals and power supply terminals. However, when the package size is constant, the number of terminals is also constant, and an increase in the number of ground terminals and power supply terminals causes a decrease in the number of signal terminals. Therefore, when implementing a large current LSI that requires dozens of ground and power supply terminals, the number of signal terminals is small. Furthermore, if an attempt is made to increase the number of signal terminals at this time, there is a problem in that the size of the package becomes large, and when mounting the package on a printed wiring board or the like, a large mounting area is required.
二６問題点を解決するだめの技術手段
本発明では、セラミ、り基体の従来のリード端子引出し
面と反対側の面に電源端子とグランド端子を引き出して
、上記問題点を解決している。26 Technical Means for Solving the Problems The present invention solves the above problems by drawing out the power supply terminal and the ground terminal on the surface of the ceramic substrate opposite to the conventional lead terminal drawing surface.
ホ、実施例 次に本発明を実施によシ説明する。E, Example Next, the present invention will be explained by carrying out the invention.
第１図（ａ）は本発明の一実施例を示す平面図であシ、
同図［ｂ）はその側面図であシ、同図（ｃ）は底面から
見た図である。これらの図において、ＬＳＩ素子の実装
されたセラミ、り基体１の上には、ＬＳＩ素子素子封止
用ツヤ２が取シつけられておシ、また、そのキャップの
取シつけられた面と同一の面にはＬＳＩ素子のグランド
及び電源と電気的にしっかシとｉ続されたグランド及び
電源端子６と５が取９つけられている。また、このグラ
ンド及び電源端子と反対側の底面には、ＬＳＩ素子の信
号線と電気的に接続された多数の信号端子４が取シつけ
られている。このように、セラミ、り基体１の全く別々
の面にグランドと電源端子６と５、ならびに信号端子４
を取９つけることによシ、従来構造のものよシも信号端
子の数を増やすことが出来る。また、信号端子とグラン
ド及び電源端子が則−面に取９つけられた従来構造では
、グランド及び電源端子と信号端子との間隔に制約があ
シ、グランド及び電源端子をＬＳＩ素子の付近にもって
いくことが不可能であったが、本発明によれば、グラン
ド及び電源端子をＬＳＩ素子の実装されている中心部分
までもっていくことが可能である。FIG. 1(a) is a plan view showing an embodiment of the present invention.
Figure [b] is a side view thereof, and figure (c) is a view seen from the bottom. In these figures, an LSI element sealing gloss 2 is attached to the ceramic substrate 1 on which the LSI element is mounted, and the surface to which the cap is attached is Ground and power supply terminals 6 and 5, which are electrically firmly connected to the ground and power supply of the LSI element, are attached to the same surface. Further, a large number of signal terminals 4 electrically connected to the signal lines of the LSI elements are attached to the bottom surface on the opposite side from the ground and power supply terminals. In this way, the ground and power terminals 6 and 5, as well as the signal terminal 4 are placed on completely different sides of the ceramic substrate 1.
By adding 9, the number of signal terminals can be increased compared to the conventional structure. In addition, in the conventional structure in which the signal terminal, ground, and power terminal are mounted on the same plane, there are restrictions on the spacing between the ground, power terminal, and signal terminal, and the ground and power terminal are placed near the LSI element. However, according to the present invention, it is possible to bring the ground and power terminals to the center where the LSI element is mounted.
このことは、グランド及び電源端子とＬＳＩ素子との間
を電気的に低抵抗で接続出来るため、大きなグランド電
流及び電源電流をもつＬＳＩ素子であっても実装可能と
なる。This allows electrical connection between the ground and power supply terminals and the LSI element with low resistance, so that even LSI elements with large ground and power supply currents can be mounted.
さらに本発明の実施例によれば、第２図の平面図に見ら
れるように、グランドと電源電圧との間に挿入する大容
量のコンデンサ７をプラグインパッケージの上に載せ、
電源端子５とグランド端子６の間に接続している。これ
によって、電源雑音の少ない電源電圧をＬＳＩ素子へ供
給するとともに、多数のプラグインパッケージを取シつ
けるためのプリント配線基板からコンデンサ７を除くこ
とが出来るため、プリント配線基板を小型にすることが
可能である。Furthermore, according to the embodiment of the present invention, as seen in the plan view of FIG. 2, a large capacitor 7 inserted between the ground and the power supply voltage is mounted on the plug-in package.
It is connected between the power supply terminal 5 and the ground terminal 6. As a result, it is possible to supply a power supply voltage with low power supply noise to the LSI elements, and also to remove the capacitor 7 from the printed wiring board on which a large number of plug-in packages are installed, making it possible to downsize the printed wiring board. It is possible.
へ、−発明の効果
上述のとおり、本発明では、複数の信号端子をもつ一つ
の面の反対側の面にグランドと電源の端子を設けたこと
によシ、信号端子の数を減らすことなく、マた、パッケ
ージサイズを大きくすることなく大電流のＬＳＩ素子を
実装することができる０-Effects of the Invention As mentioned above, in the present invention, by providing the ground and power terminals on the opposite side of one side having a plurality of signal terminals, it is possible to achieve this without reducing the number of signal terminals. , it is possible to mount large current LSI elements without increasing the package size.
第１図（ａ）は本発明の一実施例の平面図、同図（ｂ）
は側面図、同図（ｃ）は底面図、第２図は本発明の一応
用例を示す平面図、第３図（ａ） 、 （ｂ） 、 （
ｃｊはそれぞれ従来のプラグインパッケージの半面図、
側面図。
底面図である。
１・・・・・・セラミック基体、２・・・・・・キャッ
プ、３・・・・・・端子、４・・・・・・信号端子、５
・・・・・・電源端子、６・・・・・・グランド端子、
７・・・・・・コンデンサ。FIG. 1(a) is a plan view of an embodiment of the present invention, and FIG. 1(b) is a plan view of an embodiment of the present invention.
is a side view, FIG. 2(c) is a bottom view, FIG. 2 is a plan view showing an example of application of the present invention, and FIGS.
cj is a half-view of the conventional plug-in package,
Side view. It is a bottom view. 1...Ceramic base, 2...Cap, 3...Terminal, 4...Signal terminal, 5
...Power terminal, 6...Ground terminal,
7... Capacitor.
Claims (1)
ック基体と、この基体の前記キャビティの開口を封止す
るキャップと、前記キャビティの開口面と反対側の面か
ら垂直に引き出された多数のリード端子とを有するプラ
グインパッケージにおいて、前記キャップ封止側の面に
も端子が引き出されていることを特徴とするプラグイン
パッケージ。A ceramic base body having a cavity portion for storing and fixing a semiconductor element, a cap sealing an opening of the cavity of the base body, and a large number of lead terminals drawn out perpendicularly from a surface opposite to the opening surface of the cavity. 1. A plug-in package comprising: a plug-in package, wherein a terminal is also drawn out from the surface on the sealing side of the cap.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12465284A JPS613440A (en) | 1984-06-18 | 1984-06-18 | Plug-in package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12465284A JPS613440A (en) | 1984-06-18 | 1984-06-18 | Plug-in package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS613440A true JPS613440A (en) | 1986-01-09 |
Family
ID=14890704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12465284A Pending JPS613440A (en) | 1984-06-18 | 1984-06-18 | Plug-in package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS613440A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62204300A (en) * | 1986-03-05 | 1987-09-08 | 日本無線株式会社 | Voice switch |
| JPS6310199A (en) * | 1986-07-02 | 1988-01-16 | 東通電子サ−ビス株式会社 | Voice switch |
| US5475261A (en) * | 1990-09-19 | 1995-12-12 | Fujitsu Limited | Semiconductor device having many lead pins |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS516566B2 (en) * | 1972-11-17 | 1976-02-28 | ||
| JPS56121951A (en) * | 1980-03-03 | 1981-09-25 | Tokuichiro Kato | Utilization of hot water using both discharged gas from refrigerator and solar heat |
| JPS5897899A (en) * | 1981-12-08 | 1983-06-10 | 日本電気株式会社 | Chip case for integrated circuit |
| JPS5954249A (en) * | 1982-09-22 | 1984-03-29 | Fujitsu Ltd | Semiconductor device |
-
1984
- 1984-06-18 JP JP12465284A patent/JPS613440A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS516566B2 (en) * | 1972-11-17 | 1976-02-28 | ||
| JPS56121951A (en) * | 1980-03-03 | 1981-09-25 | Tokuichiro Kato | Utilization of hot water using both discharged gas from refrigerator and solar heat |
| JPS5897899A (en) * | 1981-12-08 | 1983-06-10 | 日本電気株式会社 | Chip case for integrated circuit |
| JPS5954249A (en) * | 1982-09-22 | 1984-03-29 | Fujitsu Ltd | Semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62204300A (en) * | 1986-03-05 | 1987-09-08 | 日本無線株式会社 | Voice switch |
| JPS6310199A (en) * | 1986-07-02 | 1988-01-16 | 東通電子サ−ビス株式会社 | Voice switch |
| US5475261A (en) * | 1990-09-19 | 1995-12-12 | Fujitsu Limited | Semiconductor device having many lead pins |
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