JPH05190765A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05190765A JPH05190765A JP142192A JP142192A JPH05190765A JP H05190765 A JPH05190765 A JP H05190765A JP 142192 A JP142192 A JP 142192A JP 142192 A JP142192 A JP 142192A JP H05190765 A JPH05190765 A JP H05190765A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor element
- electronic component
- qfp
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Abstract
Description
【0001】[0001]
【産業上の利用分野】この発明は、半導体装置特にピン
グリッドアレイ(以下PGAという)の基板構造に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate structure of a semiconductor device, particularly a pin grid array (hereinafter referred to as PGA).
【0002】[0002]
【従来の技術】図4および図5は従来のこの種半導体装
置の外観形状を示す図で、図において1は積層板、2は
積層板1に格子状に半田付けされた外部端子、3は積層
板1に半田付けされた四辺に端子4が設けられた四角形
状の半導体集積素子(以下QFPという)である。ここ
で゛QFP3の端子4と外部端子2が積層板1上にあら
かじめ配線された図示しない導体によって接続されてい
る。2. Description of the Related Art FIGS. 4 and 5 are views showing the external shape of a conventional semiconductor device of this type. In the figures, 1 is a laminated plate, 2 is an external terminal soldered to the laminated plate 1 in a grid pattern, and 3 is an external terminal. This is a quadrilateral semiconductor integrated device (hereinafter referred to as QFP) in which terminals 4 are provided on four sides soldered to the laminated plate 1. Here, the terminal 4 of the "QFP 3" and the external terminal 2 are connected by a conductor (not shown) pre-wired on the laminated plate 1.
【0003】[0003]
【発明が解決しようとする課題】従来の半導体装置は以
上のように構成されており、回路の複雑化により、半導
体装置にも回路を構成することが必要であるが、実装ス
ペースがあまりないという問題点があった。The conventional semiconductor device is configured as described above, and it is necessary to configure the circuit in the semiconductor device due to the complexity of the circuit, but there is not much mounting space. There was a problem.
【0004】この発明はこのような問題点を解消するた
めになされたもので、半導体素子と別の電子部品を基板
上で接続することにより、複雑な回路を構成した半導体
装置を得ることを目的とする。The present invention has been made to solve such a problem, and an object thereof is to obtain a semiconductor device having a complicated circuit by connecting a semiconductor element and another electronic component on a substrate. And
【0005】[0005]
【課題を解決するための手段】この発明に係る半導体装
置は、一面に複数個の外部端子が設けられた基板の他面
にQFPを取付けると共に、このQFPの実装部以外の
基板の他面に別の電子部品を取付け、これらのQFP、
電子部品および外部端子相互間を配線によって電気的に
接続したものである。In a semiconductor device according to the present invention, a QFP is mounted on the other surface of a substrate having a plurality of external terminals on one surface, and the other surface of the substrate other than the mounting portion of the QFP is mounted. Attaching different electronic components, these QFP,
The electronic components and the external terminals are electrically connected to each other by wiring.
【0006】一面に複数個の外部端子が設けられた基板
の他面に半導体素子を取付けると共に、この半導体素子
の下方の基板に凹部を形成し、この凹部に別の電子部品
を取付け、これらの半導体素子、電子部品および外部端
子相互間を配線によって電気的に接続したものである。A semiconductor element is mounted on the other surface of the substrate having a plurality of external terminals provided on one surface thereof, a recess is formed in the substrate below the semiconductor element, and another electronic component is attached to the recess. The semiconductor element, the electronic component, and the external terminal are electrically connected to each other by wiring.
【0007】一面に複数個の外部端子が設けられた第1
の基板の他面に半導体素子を取付けると共に、この半導
体素子の実装部上方に第2の基板を配置して第1の基板
に取付け、これら半導体素子、電子部品および外部端子
相互間を配線によって電気的に接続したものである。A first device having a plurality of external terminals on one surface
The semiconductor element is mounted on the other surface of the board, the second board is arranged above the mounting portion of the semiconductor element, and the second board is mounted on the first board. Connected to each other.
【0008】[0008]
【作用】この発明による別の電子部品は、QFP等の半
導体素子の実装部外周辺部、上方部および下方部に配置
されるので、複雑な回路を構成することができ、マザー
ボードの小形化が可能となる。Since the other electronic component according to the present invention is arranged at the outer peripheral portion, the upper portion and the lower portion of the mounting portion of the semiconductor element such as QFP, it is possible to form a complicated circuit and reduce the size of the mother board. It will be possible.
【0009】[0009]
【実施例】実施例1、以下、この発明の一実施例を図1
にもとづいて説明する。即ち図1において、5は積層板
1上に取付けられたQFP3の実装部以外の空スペース
に実装された別の電子部品である。なお、その他の構成
は図4および図5に示す従来のものと同様であるので説
明を省略する。ここで積層板1に図示しない導体配線を
施し、QFP3、電子部品5および外部端子2の相互間
を接続する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Embodiment 1 FIG. 1 is an embodiment of the present invention.
I will explain based on. That is, in FIG. 1, reference numeral 5 is another electronic component mounted in an empty space other than the mounting portion of the QFP 3 mounted on the laminated plate 1. Since the other structure is the same as the conventional structure shown in FIGS. 4 and 5, description thereof will be omitted. Here, conductor wiring (not shown) is provided on the laminated plate 1 to connect the QFP 3, the electronic component 5, and the external terminal 2 to each other.
【0010】実施例2、なお、実施例1ではQFP3の
実装部以外の空スペースに電子部品を実装したが、図2
に示すように積層板1にざぐりによって凹部11を形成
し、この凹部11に電子部品5を実装し、その上にQFP
3を実装してもよい。In Example 2, the electronic component was mounted in the empty space other than the mounting portion of the QFP 3 in Example 1, as shown in FIG.
As shown in FIG. 3, a recess 11 is formed in the laminated plate 1 by counterboring, the electronic component 5 is mounted in the recess 11, and the QFP is mounted thereon.
3 may be implemented.
【0011】実施例3、また図3に示すように、積層板
1を2段構造にし、一方の積層板にQFP3を実装し、
別の積層板に電子部品4を実装してもよい。As shown in Example 3 and FIG. 3, the laminated plate 1 has a two-stage structure, and the QFP 3 is mounted on one of the laminated plates.
The electronic component 4 may be mounted on another laminated plate.
【0012】[0012]
【発明の効果】上記のようにこの発明による半導体装置
は、QFP等の半導体素子の実装部以外の基板に別の電
子部品を取付けたので、複雑な回路を構成することがで
きマザーボードを小形化できる。As described above, in the semiconductor device according to the present invention, since another electronic component is mounted on the substrate other than the mounting portion of the semiconductor element such as QFP, a complicated circuit can be formed and the motherboard can be miniaturized. it can.
【図1】この発明の一実施例を示す側面図である。FIG. 1 is a side view showing an embodiment of the present invention.
【図2】この発明の他の実施例を示す断面図である。FIG. 2 is a sectional view showing another embodiment of the present invention.
【図3】この発明のさらに他の実施例を示す側面図であ
る。FIG. 3 is a side view showing still another embodiment of the present invention.
【図4】従来のこの種半導体装置を示す平面図である。FIG. 4 is a plan view showing a conventional semiconductor device of this type.
【図5】従来の半導体装置を示す側面図である。FIG. 5 is a side view showing a conventional semiconductor device.
1 積層板 2 外部端子 3 QFP 4 QFPの端子 5 電子部品 1 Laminated board 2 External terminal 3 QFP 4 QFP terminal 5 Electronic component
───────────────────────────────────────────────────── フロントページの続き (72)発明者 河井 優孝 兵庫県川西市久代3丁目13番21号 株式会 社ケーディーエル内 (72)発明者 竹村 誠次 伊丹市瑞原4丁目1番地 三菱電機株式会 社北伊丹製作所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yutaka Kawai, 3-13-21, Kushiro, Kawanishi-shi, Hyogo Stock company Kediel (72) Inventor Seiji Takemura 4-chome, Mizuhara Itami-shi Mitsubishi Electric Corporation Company Kita Itami Works
Claims (3)
板、この基板の他面に取付けられたQFP、このQFP
の実装部以外の上記基板の他面に取付けられた別の電子
部品、上記基板の他面に形成された上記半導体素子、電
子部品および外部端子相互間を電気的に接続する配線を
備えた半導体装置。1. A substrate having a plurality of external terminals provided on one surface, a QFP attached to the other surface of the substrate, and the QFP.
Another electronic component attached to the other surface of the substrate other than the mounting part of the semiconductor, the semiconductor element formed on the other surface of the substrate, a semiconductor including wiring for electrically connecting the electronic component and the external terminals to each other. apparatus.
板、この基板の他面に取付けられた半導体素子、この半
導体素子の下方の上記基板の他面に形成された凹部に取
付けられた別の電子部品、上記基板の他面に形成され上
記半導体素子、電子部品および外部端子相互間を電気的
に接続する配線を備えた半導体装置。2. A substrate having a plurality of external terminals provided on one surface, a semiconductor element mounted on the other surface of the substrate, and a recess formed on the other surface of the substrate below the semiconductor element. A semiconductor device comprising another electronic component, a wiring formed on the other surface of the substrate to electrically connect the semiconductor element, the electronic component, and the external terminal to each other.
1の基板、この第1の基板の他面に取付けられた半導体
素子、この半導体素子の上方に配置され上記第1の基板
に取付けられた第2の基板、この第2の基板に取付けら
れた別の電子部品を備え、上記半導体素子、電子部品お
よび外部端子相互間を電気的に接続したことを特徴とす
る半導体装置。3. A first substrate having a plurality of external terminals provided on one surface thereof, a semiconductor element attached to the other surface of the first substrate, and a semiconductor substrate disposed above the semiconductor element and arranged on the first substrate. A semiconductor device comprising a mounted second substrate and another electronic component mounted on the second substrate, wherein the semiconductor element, the electronic component and the external terminal are electrically connected to each other.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP142192A JPH05190765A (en) | 1992-01-08 | 1992-01-08 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP142192A JPH05190765A (en) | 1992-01-08 | 1992-01-08 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05190765A true JPH05190765A (en) | 1993-07-30 |
Family
ID=11501004
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP142192A Pending JPH05190765A (en) | 1992-01-08 | 1992-01-08 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05190765A (en) |
-
1992
- 1992-01-08 JP JP142192A patent/JPH05190765A/en active Pending
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