JPS61296629A - Three-phase ac switching circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

TECHNICAL FIELD The present invention relates to a three-phase AC switch circuit, and more particularly to a three-phase AC switch circuit that uses a relay switch to perform zero-crossing switching. BACKGROUND ART Electromagnetic switches (magnetic relays), solid state relays (SSR), and the like are used as switches for three-phase AC circuits. Among these switches, electromagnetic switches have low conduction resistance (ON resistance) and generate less heat when energized, resulting in lower temperature rises, so they can be made smaller, and solid-state relays have the advantage of long lifespans because they have no mechanical contacts. On the other hand, electromagnetic switches have short lifespans because their contacts are damaged by arcing when they open and close, and solid-state relays have high conduction resistance (ON resistance) and require large heat sinks because they generate heat when energized. However, it had the disadvantage of being difficult to miniaturize. For this reason, there has been a desire for an electromagnetic switch that has low conduction resistance when energized, generates little heat, has a long life, and is compact. Purpose The purpose of the present invention is to solve the above-mentioned technical problems, incorporate the advantages of conventional electromagnetic switches and solid-state relays, compensate for their shortcomings, and provide an AC switch circuit that has low conduction resistance, is compact, and has a long life. It is. Embodiment FIG. 1 is an electrical circuit diagram of an embodiment of the present invention. The a, b, and c phases of the three-phase AC power supply AC are connected to the power supply terminals al, bl, and cl of the three-phase AC switch circuit 1, respectively, and the three-phase loads Z constitute the three-phase load Z.
b. Each phase load of Zc is connected to load connection terminals a2, b2 and tc2, respectively. A relay switch swl is interposed between terminals al and a2 to open. Relay switch sw2. Each one terminal of sw3 and resistor R
One terminal of 1 is connected. One terminal of each of relay switches sw4 and sw5 and one terminal of resistor R2 are connected to terminal c1. The ring core K of the zero-cross detection transformer 2 has zero-cross detection coils L 1 , L separated by 120 degrees from each other.
2 and L3 are wound, and the detection coil L3 is connected to the comparison input terminal pl+p2 of the control circuit 3. One end of the detection coil L1 is connected to the resistor R1, and the other end is connected to the other terminal of the relay switch sw2. It is connected to terminal b2 via b. The 7th node of the diode D1 is connected to the other terminal of the relay switch sw3, and the cathode is connected to the other terminal of the relay switch sw2. One end of the detection coil L2 is connected to a resistor R2, and the other end is connected to the other terminal of a relay switch s+u4, and is also connected to a terminal C2 via a current re zero cross detection detector rhino passing through the ring 7K. The 7th node of the diode D2 is connected to the other terminal of the relay switch s+++5, and the cathode is connected to the other terminal of the relay switch su+4. Relays R8I to R85 are output terminals p3 +1) 4, p51 p6, p7 vl) 8, p91 forming each month of the relay drive circuit (not shown) of control circuit 3.
pio and pi 1 tl) 12 in this order. A power supply voltage +Vcc is connected to the terminal p13 of the control circuit 3, a resistor R3 is connected to the open terminal p13tp14, and the terminal p14. ON10 FF switch SW is connected between ρ15, and ON/○FF switch SW is open (O
When the FF switch SW is closed (ON), the terminal p14 becomes the Ll level. FIG. 2 is a circuit diagram of the control circuit 3. The detection coil L3 is connected to the comparison input terminals pi and p2 of the comparison circuit C1, and the output of the comparison circuit C1 is connected to the first and second differentiating circuits Ql,
Q2 is connected to each input terminal, and the output of the differentiating circuit Q1 is 3
The output of the differentiating circuit Q2 is connected to the input terminals of the three manual AND input terminals G2 and G3. A power supply voltage of 10Vcc is connected to the terminal p13, and a resistor R3 between the terminals p14. p15
An ON10FF switch SW is connected between them, and the terminal p15 is grounded. The input terminal p14 is connected to the input terminal of the input inter 7 ace C2, and the input inter 7 ace C2 is connected to the ON10 FF switch SW.
Output “H” or rLJ corresponding to the switching mode of
Line! 1. line! 1 is the input terminal of the first delay circuit DLI, NOT? -) G4 input terminal and 3-person AND date G5, G7. G9. It is commonly connected to each input terminal of G11 and G13. Said N
OT day) G4 output terminal is line! 2 through 3 people AND day) G6. G8. GI O, GI 2 and I/
'G14 each input terminal and 3-man power AND day)G
It is commonly connected to the input terminal of l3. The output of the first delay circuit DLI is N0T5'-) G 15
input terminal of the second delay circuit DL2, #IJ3
and fourth differentiator circuit Q3. Q4 is commonly connected to each input terminal, and the output of the second delay circuit DL2 is N0TAf-G.
16 input terminal, EX-OR day) G17. It is commonly connected to one input terminal of each of NOR date G18 and AND date G19. The output of the NOT date G16 is connected to the input terminal of the third delay circuit DL3, and the output of the third delay circuit DL3 is connected to the input terminal of the fj&4 delay circuit DL4 and the other input terminal of the EX-OR date G17, The output of the fourth delay circuit DL4 is connected to one input terminal of the EX-OR date G20 and the other input terminals of the NO"R, '5'-to G18, and AND date G19. EX-OR The other input terminal of gate G20 is connected to the output terminal of said NOT date G15, and EX
The output terminal of the -OR date G20 is commonly connected via the line 13 to the first input terminals of the three-person AND dates G5 to G14. The output terminal of the third differentiator Q3 is N
Connected to one input terminal of OR date G21, N. The other input terminal of RAI'-)G21 is connected to the fourth differentiator Q.
It is connected to the output terminal of 4. The output terminal of NOR day) G21 is connected to the input terminal of the fourth one-shot circuit F4.
The output terminal of is connected to the input terminal of the three-man power AND circuit F5 and the input terminal of the fifth one-shot circuit F5, and its output terminal is connected to the input terminal of the three-man power AND circuit F5. The output of the AND date G19 is commonly connected to one input terminal of the OR date G22, the input terminal of the three-man power AND date G3, and one input terminal of the AND date G23. The output terminal of the NOR date G18 is the O
The other input terminal of R date G22 and ANDAf-)
The output terminal of the EX-OR date GI7 is connected to the input terminal of the 3-person AND date G2, and the output terminal of the OR date G22 is connected to the input terminal of the 3-person AND date) GI. has been done. The input terminal of the three-man power AND date G1 is commonly connected to the output terminal of the first one-shot circuit F1, and the other input terminals of the AND date) G23 and G24, and the three-man power AND date
The input terminal of the AND date) G2 is commonly connected to one input terminal of the AND date G24 and the output terminal of the NOT date) G25, and the third input terminal of the AND date) G3 is connected to the output terminal of the second one-shot circuit F2. terminal, NOT day) G2
5 input terminal, AND date 626's other input terminal, and 3-man power AND date G14 input terminal 3-man power AND
Day) Gl's 1b power terminal is the input terminal of @2 fun shot circuit F2, 3 person power AND day) G2's output terminal is the first
The output terminals of the third one-shot circuit F3 are connected to the input terminals of the one-shot circuit F1, and the output terminals of the third one-shot circuit F3 are connected to the input terminals of the three-person AND date G11. connected to the input terminal. The output of AND?G23 is connected to the input terminal of the fifth delay circuit DL5, and the output of AND? -) The output terminal of G24 is 3-person AND date G8. G9. It is commonly connected to each fjS3 input terminal of G12, and the output of AND date 626 is the sixth
It is connected to the input terminal of delay circuit DL6. The output terminal of the fifth delay circuit DL5 is the third
At the input terminal, the output terminal of @6 delay circuit DL6 is 3-power A.
ND day) is connected to the third input terminal of G10. The set input terminal s1 of the first relay drive circuit is connected to the output terminal of the three manual AND input terminals G6 and the output terminal of the output terminal G5. The output terminal of the 3-man AND date G14 is connected to the set input terminal S2 of 2 in the second relay drive circuit, and the output terminal of the 3-man power AND date G14 is connected to the reset input terminal r3.
The output terminals of G13 are connected to each other. 3 set input terminal S3 to the third relay drive circuit
The output terminal of G12 is connected to the 3-person AND date), and the reset input terminal r3 is the 3-person AND date G12.
11 output terminals. 4 set input terminal S4 to the 4th relay drive circuit (3 manual AND day)
The output terminal of GIO is connected, and the reset input terminal r4
is connected to the output terminal of G9. 5 set input terminal s5 to the 5th relay drive circuit
The reset input terminal r5 is connected to the output terminal of 3-man power AND data) G8, and the reset input terminal r5 is connected to the output terminal of 3-man power AND data) G7. Output terminal p forming each part of 1 to 5 in the above relay movement circuit
3 yp4 +I]5 tp6 tp71ps +l)
9 The coils of relay switches R-81 to R85 are connected to tpl O and pH+p12, respectively.
When the set input terminal of each relay drive circuit is rHJ, the corresponding relay switch is driven, and when each reset input terminal is "I", the corresponding relay switch is restored. Figure 3 shows the three-phase AC of Figure 1. These are waveform diagrams of each part of the circuit, and Fig. 4 is a timing chart of the control circuit of Fig. 2@.While comparing Figs. 1 and 2 with Figs. The operation of a three-phase AC switch circuit according to an embodiment will be described. In Fig. Pt51, a series circuit of a first detection coil L1 and a resistor R1 of a zero-cross detection transformer 2 is connected between both contact poles of a relay switch sw2, and a second detection A series circuit of coil L2 and resistor R2 is connected between both contact poles of relay switch sw4.Also, line No.b through which the b-phase current Ib flows and line No.C through which the C-phase current IC flows pass through the ring core. Therefore, the b-phase voltage vb is applied to the tjS1 detection coil L1 until the relay switch 5IJJ2 becomes conductive.
The above detection coil L until the relay switch sw4 becomes conductive.
2 is applied with the C-phase voltage Vc. Furthermore, the relay switch sw2. After s+u4 conducts, the above line! B-phase current Ib and C-phase current IC flow in the directions shown by arrows at the first detection coil Ll. The second coil L2 is short-circuited by resistors R1 and R2. As a result, the relay switch sw2. Until the relay switch su+2.sw4 becomes conductive, the waveform of the voltage (Vb+Vc) shown in FIG. 3(5) is derived, and the relay switch su+2. After conduction of sw4, the waveform of the current (Ib-Ic) shown in FIG. 3(9) is derived, and these detected waveforms are applied to the input comparison circuit C1 shown in the second diagram via the terminal pl*p2. As a result, the voltage (Vb+Vc) or current (Ib-
When the waveform of Ic) changes from positive to negative, the level change H-L falls at the zero-crossing point, and when the waveform changes from negative to positive, the level change L-H rises at the zero-crossing point.
The voltage/current zero cross signal shown in FIG. 4(1) is obtained. When power is applied to the three-phase load Z, at time To, the above-mentioned 0
When the N10FF switch SW is closed, the terminal p14 becomes “
The rLl level changes from the H-level, and this level change of H-L is output as the ON signal shown in FIG. 4 (2) through the input interface 7ace C2 to the line! 1, and this ON signal is applied to the input terminal of the first delay circuit DL1. The #&1 delay circuit DLI is set in advance to a delay time t1 based on the time TO in order to cancel the bounce waveform at the time of opening and closing of the ○N10 FF switch SW, and at the time T1 shown in FIG. 4 (3). A signal A delayed by time L1 is derived from the ON signal. This signal A is the third signal. The signal A is input to the fourth differentiating circuits Q3 and Q4, and as the level changes from H to L, the fourth differentiating circuit Q4 outputs a pulse at the falling edge of the signal A, and this pulse passes through the NOR data) G2. 4 one-shot circuit F4, and the fourth one-shot circuit F4 is shown in FIG.
4) The preset time width w i (W i≧4
π). The signal, the inverted signal of the ON signal given via line 2, and the inverted signal of the signal A are the three human power A that generates the set signal S1S of 1 in the fp11 relay drive circuit.
The set signal SIS is applied to each input terminal of the ND date G6, and is applied to the relay switch su+ shown in the first diagram.
1 becomes conductive, the relay R81 is driven, and the set signal SI
As shown in Fig. 4 (19), the time width of S is Wl, which is equal to the signal, and the one-conducting operation of the relay switch S due to this is determined by the time measurement from time TO as shown in Fig. 4 (14). 6 I'm late. The second delay circuit DL2 is set in advance to a delay time t2 (t2 > t6) in order to cancel the bounce occurring within this time t6 and obtain a normal zero-crossing detection signal, and is set at the time shown in FIG. Level change H- at T2,
Derive the signal B of L. The signal B is inverted by the NOT gate 6 and is sent to the third delay circuit D.
Given to L3. The third delay circuit DL3 is connected to the relay switch su+ when the diodes Di and D2 shown in the first diagram are cut off.
3. The voltage required to make su+5 conductive (V b+
V c) Provided in order to obtain a zero-cross detection signal and a current (Ib-re) zero-cross detection signal necessary to cut off relay switch sw4 when power is turned off, which will be described later, and a delay time t3 (t3≧ 2π, however, π = 180 degrees), and at time T7 in Fig. 4 (7)
A signal C whose level changes →H is derived and applied to the fourth delay circuit DL4. The #&4 delay circuit DL4 is used to obtain a voltage (V b + V c) zero-cross detection signal necessary to make the relay switch 5I112 conductive when the diode D1 shown in the first diagram is conductive when power is applied, and to cut off the diodes Di and D2. It is provided to cut off the relay switch su+2ts3 at the time, and is set in advance to a delay time E4, and at time 10, a signal of level change L-H is derived. When the relay switch swl shown in vJ1 becomes conductive, the zero-cross detection transformer 2 changes the voltage (V b+
V c) is detected, and the output terminal of the input comparison circuit C1 has a fourth
A zero-crossing detection signal J shown in FIG. 1 is derived. After the level of signal B changes from H to L as shown at time T2 in FIG. 4 (6), the first fall of the zero cross detection signal J is detected, that is, at time T in FIG. 4 (1).
5, the second differentiator circuit Q2 shown in the second diagram outputs a pulse, which causes the first one-shot circuit F1 to operate.
@4 At time T5 in Figure (9), the level changes and a signal E of →H is derived. This signal E is set at W 3 (W 3 ≧ 3π/2) in advance in order to obtain the zero-crossing point of the voltage (Vb+Ve) from negative to positive, that is, the zero-crossing detection signal at time T9 in FIG. 3 (5). have. The second one-shot circuit F2 is activated by the output pulse of the first differentiating circuit Q1 at the rise of the zero-crossing detection signal J obtained during the period of the signal E, that is, at time T8 in FIG. 4(1).
operates, and at time T8 in FIG. 4(10), a signal F with a level change of L-+H and a time width W4 (W4≧relay operating time) is derived. The signal F passes through the AND data) G26 and then goes to the sixth delay circuit DL.
6 and preset delay time t6 (t6
A signal G shown in FIG. 4 (11) delayed by π/3) is derived. Here, the above delay time 〇 is the path of Guio HD2 shown in the first diagram;
It is set to conduct electricity. The inverted output of signal F obtained via signal E and NOT data) G25 is applied to AND date 626, and this AN
D output, the inverted output of the ON signal sold through the line /2, and the EX-OR data obtained through the line No. 3).
5 respective set signals S3S, S to the relay drive circuit
Three-person AND date G8 that generates 5S. G8゜G
12 derives set signals S3S and S5S shown in Pt44 diagrams (20) and (22) to respective relay drive circuits. This drives relays R33 and R85 to
The illustrated relay switch sw3 +su+5 is made conductive as shown in FIG. 4 (15) and (17). Signal F and line! 2 and the inverted output of the ON signal obtained through line 3 and EX-OR5'-) obtained through line 3.
The output of G20 is individually given to each input terminal of a three-person AND gate G14 that generates a set input signal of 2 to the second relay drive circuit, thereby causing the output of Figure 714 (21)
A set signal S28 shown in FIG. FIG. 4 (16) shows the timing. Signal G and line! The inverted output of the ON signal obtained through line No. 2 and the EX-OR output obtained through line no. #4 is generated, and the set signal S4S shown in FIG. FIG. 4 (18) shows the timing. Relay switch 51111~ by each set signal above
The operating order of sw5 is as follows. First, relay switch su+1 becomes conductive [Fig. 4 (14)
] Next, the relay switch sw3 connects the diode D shown in the first diagram.
When diode D1 is cut off, conduction [Fig. 4 (15)] occurs, and at the same time, relay switch sw5 is turned on when diode D2 is cut off [#IJ
4 (17)], then the relay switch sw2 conducts when the diode D1 conducts, and then the relay switch sw2 conducts when the diode D1 conducts.゜Relay switch like above
By the operation of II+1 to sw5, power energization for the three-phase load Z can be realized at zero cross. Next, when the power is turned off, when the 0N10FF switch SW is opened, the terminal p14 changes from the [LJ level to the "H level," and this level change L-H occurs at time T in Figure 4 (2).
20. This signal will hereinafter be referred to as an OFF signal. When the OFF signal is generated, the output changes according to delay times t1 to t4 set in advance by delay circuits DLI to DL4, respectively. The signal OFFM is delayed by a time L1 by the first delay circuit DLI, and the signal A1:k L is output at time T21 in FIG. 4(3).
-The level changes to H. This level change L→H is the third
The signal is applied to the differentiating circuit Q4, and the third differentiating circuit Q4 outputs a pulse in response to the rise of the signal A, and this pulse is a NOR
The signal K is applied to the fourth one-shot circuit F4 via the date G21, and the fourth one-shot circuit F4 receives the signal K having a preset time width W1 (W1→4π) at the time T in FIG. 4 (4).
It is derived again in 20. The above time width W for this signal
1 is the relay switch s shown in the first diagram when the power is turned off.
The time is set for w2-5Il15 to completely recover, and the rHJ level is maintained in the signal during this time. This is because relay switch su+1 is restored last, and when signal K changes to HL, relay R8 is restored. This timing is shown in Figure 4 (4). (14). The signal is also given to a fifth differentiating circuit Q5 which outputs a pulse at the rising edge of the input signal, and the output pulse operates the fifth one-shot circuit F5, and at time T2 in FIG. 4 (5).
At step 6, the level changes and at H, a signal having a time width W2 (W2>relay operating time) is derived again. The OFF signal is delayed by t2 by the f52 delay circuit DL2, and the level changes L- at time T22 in Fig. 14 (6).
The high signal B is derived again. The level of signal B goes from L to H.

[-Book addition] At the falling edge of the current (Ib-Ic) zero-crossing detection signal J, that is, at time T23 in FIG. This signal is applied to the shot circuit F1, and the one-shot circuit F1 thereby changes the level at time T23 in FIG. 4(9) and again derives the signal E having the time width W3 at the level →H. Current (Ib-Ic) zero cross detection obtained at time T24 in FIG. 4 (1) during the period of signal E (at the rise of W No. J, the first quantity dividing circuit Q1 outputs a pulse, and this pulse output is AND D) G 2 is input to the second one-shot circuit F2, and the second one-shot circuit F2
changes in level at time T24 in FIG. 4(10), and again derives the signal F of W 4 (W 4 =π) during 14H1 time. Power obtained during the time width W4 of signal F (■b-I
c) The falling edge of the zero-crossing detection signal J, that is, the falling edge of the zero-crossing detection signal J, that is, the falling edge of the zero-crossing detection signal J (
At time T25 in 1), the second differentiator Q2 outputs a pulse based on this falling signal, and this pulse is AND5'
- is input to the third one-shot circuit F3 via gate G3,
The third one-shot circuit F3 is thereby configured as shown in FIG.
At time T25 in 3), a signal (2) having a level change of L-4H and a time width of W5 (W5≧relay operating time) is derived. In order to replace the signal E with a signal generated at the zero-crossing point of the C-phase current Ic from positive to negative, delay time L5 (t5=5
The signal E is input to the fifth delay circuit DL5 of π/6), and the fourth
A signal H shown in Figure (12) is obtained. This signal (1) is synchronized with the negative phase of the C-phase current Ic as described above. signal E, the OFF signal applied via line 1, and the EX-OR data applied via line 13) G
' The output of 20 is a three-man power AND function that generates the reset signal S4R of 4 in the fourth relay drive circuit. A reset signal input terminal r4 of No. 4 is output to the fourth relay drive circuit, the relay R84 is restored, and the relay switch 5Il14 shown in the first figure is
) is shut off as shown. Signal I] and line! 1 and the OFF signal applied through the line! EX-OR day given via 3)G
The output of 20 is a three-man power AND function that generates a reset signal S5R of 5 to the 5th relay drive circuit. A reset signal input terminal r5 of 5 is output to the relay drive circuit, and the relay R35 is restored and the PI
The relay switch su+5 shown in S1 is cut off as shown in FIG. 4 (17). Signal F and line! 12 and the OFF signal applied via the line! EX-OR date G given through 3
The output of 20 is individually applied to each input terminal of the three-man power AND date G13 that generates the reset signal S2R of 2 to the second relay drive circuit, and the reset signal S2R shown in FIG. 4 (26) is applied to the second relay drive circuit. The reset signal input terminal r2 of No. 2 is outputted to the drive circuit, the relay R32 is restored, and the relay switch su+2 shown in the first diagram is cut off as shown in FIG. 4 (16). The output of the signal (1) and the EX-OR data (obtained via line 71) G20 are individually applied to each input terminal of the three-power AND gate G11, which generates the three reset signals S3R to the third relay drive circuit. , a reset signal S3R shown in FIG. 4 (27) is derived, the relay RS3 is restored, and the relay switch Sw3 shown in FIG. 1 is cut off as shown in FIG. 4 (15). OFF signal given via line 1, EX-OR data given via line 3) G2
An output of 0 means a reset signal S of 1 to the first relay drive circuit.
The reset signal SIR shown in FIG. 4 (28) is derived by being applied individually to each input terminal of the three-man power AND'l'-) G5 that generates IR, and the relay R8I is restored and the relay shown in FIG. The switch swl is cut off as shown in FIG. 4 (14). The function of the relay switch according to each of the above signals is as follows. First, the diode shown in Figure 1 [Figure 4 (1)
8) l, Next, when the diode D2 is cut off, the relay switch sw5 is cut off [Fig. 4 (17)], and then when the diode D1 is turned on, the relay switch sw2 is cut off, and rm4
Figure (16)], then when the diode D1 is cut off, the relay switch sw3 is shut off [Figure 4 (15) l, and finally the relay switch swl is shut off [Figure 4 (14) a series of operations over 1°]. This enables power dissipation of three-phase loads using relay switches at zero cross. rj45 is an electric circuit diagram of another embodiment of the present invention,
FIG. 6 is a circuit diagram of the control circuit, FIG. 8 is a waveform diagram of the AC circuit, and FIG. 7 is a timing chart of the control circuit. It should be noted that in this embodiment, two zero-cross detection transformers 52a and 52b are used to detect the second phase,
The voltage or current waveforms of the two phases are individually guided to the control circuit 53 by intervening in each of the third phases.As a result, the phase difference between each phase can be detected accurately, and the speeding can be accurately performed. Obtainable. Next, the operation of this embodiment will be explained while comparing FIGS. 5 and 6 with the fJfJS diagram and FIG. 8. 1 of the first zero cross detection transformer 52a in FIG.
Next side fill l751 and second zero cross detection transformer'
52b is connected in parallel with the primary coil L53, and a resistor R51 is connected in series thereto. This resistance R5
A series/parallel circuit of coils L51 and L51 and L53 is connected between both contact poles of the relay switch sw2. In addition, a line b through which the B-phase current rb flows passes through the ring core of the first zero-cross detection transformer 52a through the inside of the C-phase current IC.
A line C through which the flow passes through the ring core 52. Therefore, the primary coil L of the first zero-cross detection transformer 52a is connected until the relay switch 5w52 becomes conductive.
B-phase voltage vb is applied to 51, and relay switch 5
The C-phase voltage Vc is applied to the primary coil L53 of the second zero-cross detection transformer 52b until w54 becomes conductive. Furthermore, the above relay switches 5w52 and 5w54
After passing through, the b-phase current Ib flows in the line no. b and the C-phase current Ic flows in the line IC in the directions shown by the arrows, and the primary side fills L51. L53 is resistance R
Shorted by 1. Therefore, the waveform of the voltage Vb shown in FIG. Relay switch sw4 is installed on side coil L54.
The waveform of voltage Vc shown in FIG. 7(4) is derived until conduction occurs. Also, relay switch SU52.5114
After each conduction is conducted, the waveform of the current rb shown in FIG. 7(6) is derived from the secondary coil L52 of the detection transformer 51, and
54, the waveform of the current Ic shown in FIG. 6(7) is derived. These waveforms are connected to terminals ρ51. ρ52 and terminal p
Comparing circuits C51 and C5 via p53 and p54, respectively.
2. As a result, the output terminal of the comparator circuit C52 has a level 'e' at the zero cross point when the waveform of the voltage Vc or current Ic changes from positive to negative.
The current/voltage zero-crossing detection signal Z1 shown in FIG. 8 (6) is derived at the falling edge of L and the zero-crossing point when changing from negative to positive → the rising edge of H. Further, the output terminal of the comparator circuit C52 is connected to the zero cross point when the waveform of the voltage Vc or current Ic changes from positive to negative, the fall of the level change H→L, and the zero cross point when the waveform of the voltage Vc or current Ic changes from negative to positive. At point 8 [!] of the rise of the level change L-H. A current/voltage zero cross detection signal Z2 shown in 1(7) is derived. When applying power to the three-phase load Z, the above O at time To
N10 FF F Switch S When the field is closed, terminal p66
The level changes from HarHl level to rLJ level,
This level change of H-nL is output as an ON signal shown in FIG. 51, and this ON signal is output to the first delay circuit DLI.
is applied to the input terminal of The first delay circuit DL51 is the 0N10FFX switch SW.
In order to cancel the bounce waveform at the time of opening and closing, the delay time t1 is set in advance with time TO as f & empty,
At time T1 in FIG. 8 (9), 1 time elapses from the ON signal.
A level change HL signal A is derived with a delay. This signal A is applied to the fifth and sixth differentiating circuits Q5. When the signal A is input to Q6 and changes in level from H to L, the sixth differentiating circuit Q56 outputs a pulse at its falling edge, and this pulse is given to the fjrJ5 one-shot circuit F55 via the NOR gate G58. The fifth one-shot circuit 55 operates W 1 (W
1≧4π). The signal M, the inverted signal of the ON signal applied via the line No. 2 via the N0TE'-to G74, and the inverted signal of the signal A are connected to the set signal S of 51 in the first relay drive circuit.
5 Is is applied to each input terminal of the three-man power ANDAfp-) C76, the set signal 551S is derived, and the relay switch SW51 shown in FIG. relay R351 is driven, and the set signal ss is is equal to the signal M during time as shown in FIG. 8 (20).
It is l. The second delay circuit DL52 is preset to a delay time of 2 in order to cancel the bounce occurring within the time t1 and obtain a normal zero-crossing detection signal, and is set to a delay time of 2 in FIG.
At time T2 shown in 10), a signal B whose level changes from H to L is derived. Signal B is inverted at NOT day G66 and supplied to third delay circuit DL53. The third slow district circuit DL53 is the fifth delay circuit DL53.
When the illustrated diode D1 is cut off, the relay switch 5w5
The diode D
2 is provided in order to obtain a zero-cross detection signal of the current IC necessary to cut off the relay switch 5W54 when it is conductive, and is set in advance to open at the time of delay L3 (t3≧2π, where π=
180 degrees), and a signal C whose level changes from L to H is derived at time T4 in FIG. 8 (11) and is applied to the fourth delay circuit DL54. The fourth delay circuit DL54 is used to obtain a voltage vb zero-cross detection signal necessary to conduct the relay switch 5w52 when the diode D1 shown in the first diagram is conductive when power is applied, and to conduct the relay switch 5w54 when the diode D2 is conductive. It is provided to obtain a current Ic zero-crossing detection signal for the current Ic, and to obtain a current rb zero-crossing signal for cutting off the relay switch sw3 when the diode D1 is cut off, and to obtain a current rb zero-crossing signal for cutting off the relay switch sw3 when the diode D1 is cut off during power de-energization, which will be described later. It is also used to obtain a current 1c zero-cross detection signal for cutting off relay switch 5-55 at times, and to obtain a current Ib zero-crossing detection signal for cutting off relay switch 5w52 when diode D1 is cut off. @44 Yanting Road DL54 has a delay time t4 in advance
(t4≧2π), and a level change L-'H signal is derived at time TIO shown in FIG. 8 (12). When the relay switch 5w51 shown in the fifth figure becomes conductive, the first
The zero cross detection transformer 52a receives the voltage vb as described above.
is detected, and the output terminal of the input comparator circuit C51 is shown in FIG.
6) The first zero-crossing detection signal Z1 shown in FIG. That is, at time T3 in FIG. 8(6), the fJS2 differentiating circuit Q52 shown in FIG.
At time T3 in FIG. 15, a signal P with a level change L-H is derived. This signal P has a time width W2 (
W2≧π). First zero crossing detection signal Z obtained during the period of signal P
1, that is, at time T5 in FIG. 8(6), the second differential circuit F52 is activated by the output pulse of the first differentiating circuit Q51, and at time T5 in FIG. 8(16), the level changes at L-4H. A signal Q during time W 4 (W 4 ≧ relay operating time) is derived. The zero crossing point from negative to positive of the current 1c obtained first after the level change of H and L shown at time T2 in FIG. 8(10) of signal B, that is, the second zero cross point at time T6 in FIG. 7(7).
The zero-crossing detection signal Z2 rises at time T6 in FIG.
53 operates and derives a signal S having a time width W 5 (W 5 ≧ one relay operation time) with a level change L→■] at time T6 shown in FIG. In order to obtain a signal synchronized with the voltage Vc, the signal P is applied to the fifth delay circuit DL55 via the seventh node G68,
Time L5 equal to the phase difference between voltages vb and Vc Delay m
The signal R shown in FIG. 8 (17) is derived. AND output of the signal P and the inverted signal of the signal Q obtained via the NOT data) G69, and the line! The inverted signal of the ON signal given through line No. 2 and the output of EX-OR day G85 given through line no.
It is given individually to each input terminal of a4, and the above three-man power AN
D date G80 is $8 set signal 55 shown in figure (21)
3S is derived to 53 to the fA3 relay drive circuit. As a result, the relay R853 is driven and the relay switch sw3 shown in the first diagram becomes conductive as shown in FIG. 8(2). Signal R and line! The inverted signal of the ON signal obtained through 2 and the line! EX-OR Deday G8 obtained through 3
The output of 5 is the input AND data that generates the set input signal of 55 in the fifth relay drive circuit.It is individually applied to each input terminal of Ga4, thereby generating the set signal -555S shown in FIG. 8 (23). The relay R855 is driven, and the relay switch sw5 shown in FIG.
) conducts as shown. The inverted output of the ON signal obtained via signal Q and line 2, and the EX-OR data obtained via line 3)G
The output of a4 is individually applied to each input terminal of the 3-power AND date 078 which generates 52 set input signals to the second relay drive circuit, thereby generating the set signal 552S shown in FIG. 8 (22). The relay R352 is driven to conduct the relay switch 5W52 shown in the first diagram. FIG. 4(3) shows the timing. The signal R, the inverted output of the ON signal obtained through line No. 2, and the line! 8 (24 ) Set signal 55 shown in
4S is derived, the relay R854 is driven, and the relay switch 511154 shown in @5 is made conductive.7. FIG. 8(5) shows the timing. Relay switch su+51~ by each set signal above
The operating order of the SW 55 is as follows. First, the relay switch su+51 becomes conductive [Fig. 8 (1)],
Next, the relay switch 5153 connects the diode D shown in FIG.
The relay switch 5w55 is turned on when the diode D52 is cut off [Fig. 8 (4) 1, then the relay switch 5w52 is turned on when the diode D
When the diode D52 is conductive, the relay switch 5w54 is conductive [FIG. 8 (3) 1]. Finally, the relay switch 5w54 is conductive when the diode D52 is conductive [FIG. 8 (5)]. By operating the relay switches 5w51 to SW55 as described above, power energization for the three-phase load Z can be achieved at zero cross. Next, when the power is turned off, when the ON10FF switch SW is opened, the terminal p66 changes from the [L level to the [Ttle level], and this level change L-H is shown at time T20 in Fig. 8 (8). ing. Hereinafter, this will be referred to as an OFF signal. When the OFF signal is generated, the outputs change according to the delay times t1 to t4 set in advance by the delay circuits DL51 to DL54, respectively. The signal OFFM is delayed by time t1 by the first delay circuit DL51, and at time T21 in FIG. 8(9), the signal A is
I-I 1= Level changes. This level change L-4
8 is given to the fifth differentiating circuit Q55, and the fifth differentiating circuit Q5
5 outputs a pulse in response to the rising edge of signal A, and this pulse is NOR'! -G58 The fifth one-shot circuit F55 is given by wog, and the fifth one-shot circuit F5
5 is a signal M with a preset time width W1 (W1≧4π)
is derived again at time T21 in FIG. 8(13). The above-mentioned time width W1 of this signal M is set to the time required for the relay switches 5w52 to 5-55 shown in FIG.
Maintains HJ level. This is racey fsw
51 to recover to t ft the most, and the signal M is H.
→Relays R82-4 are restored by the time the state changes to L. This timing is shown in FIGS. 8(2)-(5) and (13). The signal M is input to the fifth differentiating circuit Q57 which outputs a pulse at the falling edge of the input signal, and the sixth one-shot circuit F is operated by the output pulse, and the timing T2 in FIG. 8 (14) is reached.
A signal U having a time width W6 is derived from the level change L-H shown in FIG. The OFF signal is delayed by a time L2 by the second delay circuit DL52, and at time T22 in FIG. 8 (10), the signal B changes from L to
Increase the H level to t. At the first rise of the current Ic zero cross detection signal Z2 obtained after the level of the signal B changes from L- to H, that is, at time T23 in FIG. 8 (7), the rise of the signal Z2 is detected by the third differentiator Q53.3. Human power AND date G52, NOR
The signal is applied to the first one-shot circuit F51 via the date G59, and the first one-shot circuit G51 again derives the signal P shown at #T23 in FIG. 8(15). The fall of the Ic zero cross detection signal Z2 shown at time T24 in FIG. 8 (7) obtained during the period of signal P activates the second fun shot circuit F52, and the signal shown at time T24 in FIG. 8 (16) is activated. Derive Q again. Zero cross detection signal Z1 obtained first after the level change from L to H of signal B shown at time T22 in FIG. 8 (10)
At the rising edge of , that is, at time T25 in FIG.
operates, and the signal S shown at time T25 in the fpkB diagram (18) is derived again. At the falling edge of the current Ib zero-crossing detection signal Z1 that is first obtained during the period of this signal S, that is, at time T26 in FIG. 8 (6), the second differentiating circuit Q5
2 outputs a pulse in response to the fall of the signal Z1, and this output pulse operates the fourth one-shot circuit F4, causing the level to change as shown at time T26 in FIG. 8 (19)→
W during H time? A signal ■ having (W 7≧relay one-movement response time) is derived. The AND output of the signal P and the inverted signal of the signal Q obtained through the NOT data) G69, the 0FF (Ft signal given through the line 51), and the EX-OR output of the signal Q given through the line 53. is individually given to each input terminal of the three-man power AND date G84 that generates 54 reset signals 554R to the fourth relay drive circuit,
A reset signal 554R shown in FIG. 8(25) is derived, the relay R354 is restored, and the relay switch 5tu54 shown in FIG. 1 is cut off as shown in FIG. 8(5). Signal Q and line! 0FFi issue given through 51 and line! EX-OR day given via 53)
The output of G85 is individually given to each input terminal of the three-man power AND date G75 which generates 55 reset signals 555R to the fifth relay drive circuit, and the reset signal 555R shown in FIG. 8 (26) is derived. Relay R355 is restored, and relay switch 5-55 shown in Figure 1 is switched to Figure 8 (4).
The signal is blocked as shown in . AND output of the inverted signal of the signal S and NOT data) obtained through G72, and the line! OFF signal applied via line 51 and E applied via line node 53.
The output of X-OR5/-) G85 is a three-man power ANr that generates 52 reset signals 552R to the second relay drive circuit.
) is given individually to each input terminal of date G78, and tj
A reset signal 552R shown in FIG. 8 (27) is derived, the relay R852 is restored, and the relay switch su+52 shown in FIG. 1 is cut off as shown in FIG. 8 (3). Signal V and line! The O'FF signal obtained through 51 and the line! EX-OR day obtained through 53)G
The output of 85 is a three-man power AND5/-) that generates a reset signal 553R of 53 to the third relay drive circuit.
The reset signal 553R shown in FIG. 8 (28) is derived, the relay R353 is restored, and the relay switch 5w53 shown in FIG.
2) is blocked as shown in 2). Signal U and line! 51 and the line J? The output of EX-OR day G85 given through 53 is f: 3-man power AND5/- which generates reset signal 553R of 51 to IS1 relay drive circuit.
It is applied individually to each input terminal of G75, and as shown in FIG.
The reset signal 551R shown in 9) is derived, and the relay R
351 is restored, and the relay switch 5w51 shown in the first diagram is restored as shown in FIG. 8(1). Relay switch 5tu51 by each of the above reset signals
The operating order of ~5w55 is as follows. First, when the diode D2 shown in Fig. 5 is conductive, the relay switch sw4 is cut off [Fig. 8 (4)], and then the diode D
2, the relay switch sw5 is shut off [8th
When the diode D1 conducts, the relay switch SII+2 is cut off [Pt48 (3) 1, and then when the diode D1 is cut off, the relay switch sw3 is cut off [Fig. 8 (2)], Finally, relay switch S...1
is blocked [tjIIB diagram (1)]. Through the series of operations described above, power dissipation of the three-phase load by the relay switch can be realized at zero cross. Effects As described above, according to the present invention, the phase difference between the two phases of a three-phase AC circuit is detected and the relay switch is activated to perform zero-cross switching, thereby eliminating the occurrence of 7 hogs when switching the load. It is possible to realize a three-phase alternating current circuit switch circuit that is small in size, has a long life, has no contact damage, and has low heat generation. Furthermore, since the phase difference between the voltages or currents of the two phases is detected, the timing of zero-cross opening/closing by the relay switch can be accurately obtained.

[Brief explanation of the drawing]

Figure 1 is an electric circuit diagram of a three-phase AC switch circuit, Figure 2 is a circuit diagram of control circuit 2, Figure fjfJ3 is a waveform diagram of a three-phase AC switch circuit, Figure 4 is a timing chart of control circuit 2, Figure 5 shows 10 of the three-phase AC stitch circuit! , FIG. 6 is a circuit diagram of the control circuit 53, and FIG.
The figure is a waveform diagram of the three-phase AC stitching circuit 51, and FIG. 8 is a timing chart of the control circuit 53.

Claims (1)

[Scope of Claims] A first switching means, a second switching means, and a third switching means interposed in series in each of the first, second, and third phase lines of a three-phase AC power supply; detection means for detecting the phase of current and voltage related to each line connected to the load side than the second switching means and third switching means in the phase and third phase lines; a first control circuit for controlling; a second control circuit for controlling opening/closing operations of the second switching means and the third switching means based on the signal from the detection means;
a third control circuit; the first switching means includes a first relay switch and a second control circuit;
a relay switch, and the second relay switch includes a third relay switch.
a relay switch, and the third relay switch includes a first relay switch.
The diodes are connected in series, the third switching means includes a fourth relay switch and a fifth relay switch, the second diode is connected in series to the fifth relay switch, and the second relay switch and the third relay switch are connected in series. The first diode is controlled to perform conduction/cutoff operations in response to the forward and reverse directions of current and voltage, respectively, and the fourth relay switch and the fifth relay switch are controlled to conduct current and voltage in the forward and reverse directions with respect to the second diode. A three-phase alternating current, characterized in that conduction/cutoff operations are carried out in response to forward and reverse voltage directions, respectively, and the detection means detects the phase of current and voltage for one or more lines. switch circuit.