JPS61296624A - Three-phase ac switching circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] Technical Field The present invention relates to a three-phase AC switch circuit, and more particularly to a three-phase AC switch circuit that uses a relay switch to perform zero-cross switching. With FM5 devices (J: Electromagnetic switch (?
net relay), solid state relay (SSl)
() etc. are used zl12. - Among the target openers,
Electromagnetic switches have low conduction resistance (ON resistor 1) and generate less heat when energized. Since the temperature of the I-1 scale is low, it can be miniaturized and the R length of the solid state lead is the key, but on the other hand, the electromagnetic gate opener has a - Contacts are damaged due to the occurrence of corrosion, shortening their lifespan.Also, solid state relays have continuity resistance (
There were drawbacks such as the large ON resistance (1.2), the need for a large heat sink to generate heat during energization, and the difficulty of downsizing.

, −, the conduction resistance when energized is low, and the amount of heat generated is low.
A small electromagnetic switch was desired.

Purpose The purpose of the present invention is to solve the above-mentioned technical problems, incorporate the advantages of conventional electromagnetic switches and solid state relays, compensate for their shortcomings, and support an AC switch circuit with low conduction resistance and a long lifespan. , offering "ru-" there is.

Embodiment @Figure 1 is an electrical circuit diagram of an embodiment of the present invention.
Each phase fj of 1 phase, H phase, and C phase of 3-phase AC power supply AC: :
'! 4ij AC switch circuit 1 power terminal a 1 ,
b 1 , c 1 i. ”'....%j″I
Now, connect the three-phase load Z.
5.

;The name phase load of UC is the load connection terminal &2, 112, c2f
-i i11. f is connected. Power supply terminal - fai
, a2 open 1" (upper relay switch swl is interposed at 1). Terminals ai and b1 are connected to a series circuit of resistor R1 and primary coils 1 and 1 of voltage zero cross detection 12/" switch PT. One terminal of the relay switch siv2 and the AND of the diode DI are connected to the terminal T-b1, and the cathode of the diode Di is connected to the other contact of the relay switch sw2. 1
') The 11-phase current zero-cross detection line passes through the current zero-cross detection transformer CTI and is connected to the load connection terminal b2.

One terminal of the switch sw3 and the 7 nodes of the diode D2 are connected to the power supply terminal c1, and the diode D is connected to the other contact of the relay switch 9m3.
A current zero-cross detection line passes through the current zero-cross detection transformer CT2 and is connected to the load connection terminal c2. Control circuit 2
comparison input terminal P1.

The secondary coil L2 of the voltage zero cross detection transformer PT is connected to P2, and the secondary coil L3 of the current zero cross detection transformer CTI is connected to terminals P3 and P4.
is connected to the terminals P5 and P6, and the secondary coil L4 of the current zero-cross detection transformer CT2 is connected to the terminals P5 and P6.

The power supply voltage +Vee is connected to the terminal P13 of the control circuit 2, and the terminal P15 is grounded. Terminal P13, PI3
A resistor R2 is connected to the terminal, and the distance between terminals P14 and PI3 is 1 m.
W is connected, and the switch SW is ljll(OF
F) When the terminal P14 is at the rHJ level, the switch s
When W is in the leap (ON) state, the terminal P14 is at the rLJ level.

FIG. 2 is a circuit diagram of the control circuit 3. The secondary coil L2 of the voltage zero-cross detection transformer PT is connected to the comparison input terminals Pi and P2 of the comparator C1, and the output of the comparator C1 is $1, and the second differential circuit Ql, Q2.
The output of the differentiating circuit Q1 is connected to the third input terminal of the 3-man power AND day) G7, and the output of the differentiating circuit Q2 is connected to the second input terminal of the 3-man power AND day) G8. There is.

The power supply voltage -)Vec is connected to the terminal P13, and the terminal P13 is connected to the power supply voltage -)Vec.
A resistor R3 is connected to terminals P14 and P14, and an ON10FF switch SW is connected to terminals P14 and P15, and terminal P15 is installed. The input terminal P14 is connected to the input terminal of the input inter 7/8 C4, and the input inter 7/8 C4 outputs an output rHJ or rLJ corresponding to the switching mode of the switch SW to the line No. 1. Line No. 1 branches into three branches, the first one goes to the input terminal of the delay circuit DLI of fjtJl, the second goes to the input terminal of NOTE'-)G6, and the third goes to the input terminal of the 3-manual AND day) G20, G2
2 and G24.

NOT Day) The output terminal of G6 is line! 2 through 3-person power AND day) G19. G21. It is commonly connected to each $1 input terminal of G23. MSl delay circuit DL
The output of I is branched and 1 is N.

T day) G25 output terminal, 2 is AND date G
1, G3, and one input terminal of each of the NOR dates G2 and G4. The NOTOR date G5 output terminal is branched, and one side is connected to the input terminal of the second delay circuit DL2, and the other side is connected to one input terminal of the EX-OR date G5.

The output of the second delay circuit DL2 is branched, one being the AN
One input terminal of each of the D date G3 and NOR date G4 is connected to the input terminal of the third delay circuit DL3. The output of the third delay circuit DL3 is branched to the EX-O
It is connected to one input terminal of the R date G5, and the other is connected to the other input terminals of the AND date G1 and NOR date G2. EX-OR day) The output terminal of G5 is connected to the three-person AND date G19 through line No. 3.
~G24 are commonly connected to the second input terminals. tI
The output terminal of IJ3 differentiator circuit Q3 is 3-man power AND day)G
G9 (connected to the second human power terminal of 9, 3 human power AND day)
The first input terminal of the AND gate is connected to the output terminal of the AND circuit F1, and the third input terminal thereof is connected to the output terminal of the first one-shot circuit F1 in common with the third input terminal of the AND circuit F1. ing.

NOR day) G2 output terminal is 3 person power AND day) G8
The output terminal of G3 is connected to the first input terminal of GIO, and the output terminal of G3 is connected to the first input terminal of GIO, and the output terminal of G4 is connected to the first input terminal of GIO.
It is connected to the second input terminal of G7. Further, the first input terminal of the three-man power AND gate G7 is connected to the third input terminal of the three-man power AND gate G10 and the output terminal of the NOT gate Gl4.

The output terminal of the fourth differentiator circuit Q4 is 3-man power AND day)Gl
1, and the output terminal of the fifth differentiator circuit Q5 is connected to the second input terminal of the 3-way AND-GIO.

3 people AND day) G7. Each output terminal of GIO is N0R
5'-) connected to each input terminal of G12 individually, NO
R day) The output terminal of Gl 2 is the first circuit F
1 input terminal.

3 people AND day) G8. Each output terminal of G9 is individually connected to each input terminal of Gl3 (NOR data),
The output terminal of the NOR date G13 is connected to the input terminal of the second funshot circuit F2.

The output terminal of the three-man power AND date G11 is connected to the input terminal of the third one-shot circuit F3.

Further, the third input terminal of the three-man power AND date G11 is connected to the output terminal of the second one-shot circuit F2.

The output terminal of the first circuit F1 is the fourth delay circuit D.
L4 input terminal and AND? -) is connected to one input terminal of G17, and the output terminal of the second one-shot F circuit F2 is NOT connected to one input terminal of G14. G input terminal and 3-person AND
D) Connected to the third human power terminal of G23. NOT
The OR date G5 input terminal is connected to the other input terminal of AND date) Gl7.

The output terminal of the third one-shot circuit F3 is the NOTOR date G5 input terminal and the third one-shot circuit G20.
connected to the input terminal. The output terminal of the N○T date G16 is connected to the other input terminal of the AND date 618, and the output terminal of the AND'f-) G17 is connected to the 3-man power AND
To the third human power terminal of date G19 and I/G24, also A
The output terminal of ND date G18 is 3-man power AND gate G2
2 is connected to the third input terminal of No. 2. The output terminal of tJIJ4 delay circuit DL4 is the third of
connected to the input terminal.

The set input terminal s1 of the first relay drive circuit is connected to the output terminal of the three-man power AND date G19, and the reset input terminal r1 is connected to the output terminal of the three-man power AND date G20. 9th II Le-1i l
h TEFI I&k K 9 A 4- ・7 L
'), force m - T - q2 1j i 13 human force AND? −
・The output terminal of G21 is connected, and the reset input terminal r
2 1 is connected to the output terminal of 3-man power AND5'-)G22. 3 set input terminals for the 3rd relay drive circuit! 1:( is connected to the output terminal of the 3-man power AND gate G23, and the 3-man power AND gate G23 is connected to the reset input terminal r3.
The output terminal of D--=-G24 is connected.

The relay drive circuit K i ~ has three pairs of output terminals P 7 , P 8 , P 9 . Coils 1z=R81t R62t R83 are connected to Plo, pH, and PI3, respectively, and when the set input terminal of each lid drive circuit is "11", the corresponding relay switch is activated and each When the reset input terminal is l'HJ, the corresponding relay switch L is inactivated. 3 is a waveform diagram of each part of the three-phase AC circuit l#8 of FIG. 1, and FIG. 4 is a timing chart of the control circuit of FIG. 2. The operation of a three-phase AC switch circuit according to an embodiment of the present invention will be explained below by comparing FIGS. 1 and 2 with FIGS. 3 and 4.

When power is applied to the load, the 0N10FF switch SW is closed at BTo as shown in Fig. 4, and the terminal P is turned on.
14 is from “■(” level to 1-, L,” level (4″
, changes, and this level change H-+ L 1.1・,ON
It is led out as a signal to the line 11 via the input C4 of the interface 7. 1st delay circuit ■) L 1 +, +: 0N above
In order to perform the 10-day switch, a delay time t1 is set in advance based on the time TO, and as shown in FIG.
Derive the signal at 4,; the second signal (''.A N
D5' -- ) G 1 s G 3 and NOR
data (1-G2, G4) is inverted via the NOT date G25, and is applied to the input terminal of the second delay circuit T2 and the input terminal of the second delay circuit T2.
'y'-) is applied to one input terminal of G5.

2nd M extension circuit D 1. ,, 2 is 1 and 2 in Figure 1.
-Y (when the relay switch S41 of Sl is turned off when the diode D1 is cut off, that is, at the time 'I' shown in (2) of Figure 4)
2 to time T4, in other words, the period of the positive half cycle of the voltage JEEae in Figure 3 (during this period, the voltage Eae is applied to the diode D1 in the opposite direction).
) to obtain a zero-cross signal for conduction within
In order to obtain a zero-cross signal of the C-phase current Ie to cut off the relay switch sw3 of the relay RS3 when the guide D2 is conductive, that is, at the time T7 in FIG.
Delay time 't2 (t2≧2x where y=L
80 degrees), and when power is applied, the angle shown in Figure 4 (
Signal B is derived at time T3 shown in 3). This signal B is applied to the input terminal of the third delay circuit 1) L3 and the
D day) G3, NOT game) G4 name is given to the other input terminal, AND day) G3 takes the AND of the signal A and signal B and outputs the output from the three-man power ANDAI-) G
1 Derived to the input terminal of 0, NOR data) G4
calculates the negative OR of the signal A and signal B, and delivers the output to the - input terminal of the three-man AND game) G7.

The third delay circuit DL3 switches the relay switch sw3 of the relay RS3 in FIG.
In order to conduct during the time period 111 from time T5 in FIG. 1 and FIG. sw2 to diode D1
In order to obtain a zero-crossing signal of the phase current Ib to be cut off when the power is turned off, a delay time t3 (t3≧7/2K) is set in advance with respect to time TO. The signal C is derived as shown in .

This No. 44 C is the other input terminal of the EX-OR date) G5, the AND date G1, and the NOR date G2.
The AND gate G1 thereby performs a logical product of the signals A and C and outputs the result to each one input terminal of the three-power AND gate G11.

EX-OR day) G5 performs an EX-OR of the inverted signal of signal A and signal C, and sends the output to the relay drive circuit, which will be described later, via line 13. 3 person power AND date 619 ~ G2
The ON signal derived to the input terminal 1 of each line 1 of 4 is applied to the input terminal 3 forming the set and reset signal generation circuits.
Human power AND date G20. This ON signal is applied to each input terminal of G22 and G24 (NOR data).
Gl 9. Inverted via G6, said 3-man power AND day via Line No. 2) It is applied to each one input terminal of G21 and G23.

After time T1 when the signal is derived, the first zero-crossing signal that changes from negative to positive at the zero-crossing point of voltage Eab from negative to positive shown in FIG. The circuit Q1 outputs a pulse to the input terminal at the position of the three-power AND circuit G7 at the rising edge of the zero-cross signal. The first zero-cross signal causes the first shot circuit F1 to derive a signal at time T2 as shown in FIG. It becomes a pulse signal.

During the above signal period, the voltage Ea shown in FIG. 3 (2)
At the zero cross of e from positive to negative, that is, at time T4, the input comparator circuit C1 derives a second voltage zero cross signal that changes from H to L, and the differentiator circuit Q2 performs a three-way AND operation on the pulse at the falling edge of the zero cross signal. Day) G 8
is derived to the input terminal of .

This second voltage zero-cross signal causes the second one-shot circuit F2 to derive a signal E at time T4 as shown in FIG. 4 (6), and this signal E has a time width t5 (t5≧π
) becomes a pulse signal. Here, the above signal is also AND
One input terminal of the date G17 is given, and the other input terminal is given an inverted signal obtained from the signal E through the AND date GIO, and the AND date G17 is
As a result, the signal G shown in FIG. 4(8) becomes 111T2.
G19
The 3-person AND date G19 is the aforementioned line!
2 and the inverted output of the ON signal applied through the line!
EX-OR data given via 3) the output of G5;
The above-mentioned signal G is ANDed and a set signal sls of 1 is generated in the first relay drive circuit shown in FIG. 4 (14),
As a result, relay R81 is driven, and its relay switch swl is switched from time T2 to time T as shown in FIG. 4 (11).
It becomes conductive within the period of 4. The signal is applied to a fourth delay circuit DL4. Here, the fourth delay circuit DL4 takes the voltage Eac and has a delay time t7 of π/2 corresponding to the phase difference with the C-phase voltage Vc, and the above signal is delayed by the time t7 as shown in the vJ4 diagram (10). A signal I is formed and is applied to the third input terminal of a three-power AND date G21 forming a set signal generation circuit of 2 to the relay drive circuit, where the lines /2. , /3 to generate a set signal s2s in the drive circuit shown in FIG. 4 (15),
This drives relay R82, and its relay switch SW2 becomes conductive as shown in Figure 4 (12). The above-mentioned signal E is applied to the other input terminal of G24, which forms a set signal generating circuit of 3 to the third relay circuit, and is an inverted signal of this signal E and the ON signal applied via line 72. And line! Waya ΔI 4-leg near pattern i
口V-8D aj L /' [^By the AND with the output, a set signal s3s of 3 is generated in the third relay circuit shown in FIG.
is driven, and its relay switch sw3 is activated as shown in Fig. 4 (13
) conducts as shown. In this way, 1 to 3 are driven in the relay drive circuit, and first, during the cutoff period of the diode D1 in FIG. 1, the relay switch sw of the relay R8I is
1 becomes conductive, then the relay switch sw2 of the relay R82 becomes conductive during the conduction period of the diode D1, and then the relay switch sw3 of the relay R33 becomes conductive during the conduction period of the diode D2 in FIG. Power energization can be performed at zero cross by the above series of operations. Next, when the power is turned off, the 0N10FF switch SW is opened at time T12 in the #IJS diagram and FIG. The time ti set in advance by the delay circuits DLI~D3 as
, t2, and t3, respectively.

First, at the time TIO shown in FIG. 4 (1), the ON/O
F switch SW is 011qx14, then time 1[11
After the lapse of time, the signal A is activated at time Tl 11- in FIG. 4(2).
is reversed! , so that I-, →H. The above signal A is I, -
) changes to t-1 (L"・, time □'!" of tangent 3rd tXI)
C at 12, phase current 1L-slip from negative to positive 1
J is connected to one point.
-1 Time width t40 reconnaissance l shown in Figure 4 (5)
) will appear again.

, 13-phase current Ib at time T12 during the period of width T4 of signal L).
At the zero point *:X from negative to positive, the second one-shot [-2 operates, and again outputs the signal E having the time width t5 shown in FIG. 4(6). , the width L of this signal E
Time T1 shown in FIG. 3 (7) obtained during time 5
The third one-shot circuit F3 operates at the zero-crossing point of the 11-phase current Ib from positive to negative, and as shown in FIG.
A signal F shown by is generated. This signal F is relay R
This pulse has a time width t6 that is longer than the operating time of 3I to R33.

A signal G is formed by the signal DJ and the inverted output of the signal E, and this signal G and the above-mentioned OFF signal Do nine, l?
Through 3, the given number is 16δ■ and the XOR de 1.G
5 - tr + output 77, ts 3 'J l/- drive circuit K 3 /7) +74 = nit number ' generator circuit form J
AMru three-man power A N I)tsu'l-('; 24
(y) Reset signal of RS 3! +31 is the third relay・The rear input terminal of circuit K3 is completed 1・31.
), the @3 relay Y-S3 returns 1■11, and the zonori 1/- switcher "3@3 is shut off, 211.".

-Fugi r, signal E):, inverted output of signal F 1j1, A
ND gate G1877) Each input terminal r゛-9-9 error AND 'IT'-toro 18 is shown in Fig. 4 (9). 11 and EX-
OR day) G5 output signal forms a 2/7 signal generation circuit in the second 1/- drive circuit. −
) is applied to each input terminal of G22, respectively. The second relay R8'2 shown in FIG. 4 (18) is a signal! 121- is the second relay/drive circuit/l
As shown in FIG. 4 (12), the second relay R82 is restored and its relay switch sw2 is cut off. OFF given via signal F and line, el
The signal and the output of the EX-OR date provided via line 13 form a single true signal generation circuit in the first relay drive circuit. The reset signal J+slr of the third relay RS3, which is applied to each input terminal of the three-man power AND date G20 and shown in FIG. 4 (19), is applied to the reset signal input terminal r1 of the 19th L-1 drive circuit I<1. As shown in FIG. 4 (11), the first sub-R8i is restored 1 and its relay switch 11T1 is not cut off.

As described above, the relay drive circuits 1 to 3 operate according to the reset signals g1r to s3r, and in FIG. When D1 is conductive, t: Relay switch of second relay R32! ! @2 is cut off, and finally, when the diode D1 is cut off, the relay switch swl of the first relay R8I is cut off. As described above, according to the present invention, the phase difference between the two phases of the three-phase alternating current is detected, and the relay switch is activated to perform zero-cross opening and closing. The generation of arc at 1gm is suppressed, the contacts are not damaged, and the heat generation is low. ♂) It is possible to realize a compact and life-saving three-phase AC switch circuit. Furthermore, it is possible to prevent leakage current that occurs when phase-to-phase voltage is detected in an open circuit from flowing to the load side.

[Brief explanation of the drawings] Figure 1 is an electric circuit diagram of the three-phase AC switch circuit, Figure 2 is the circuit diagram of control circuit 2, Figure 3 is a waveform diagram of the three-phase AC switch circuit, and Figure 4 is the control circuit. 3 is a timing chart of circuit 2. 1... Three-phase AC switch circuit, 2... Control circuit, A
C... Three-phase AC power supply, CTI, Cr2... Current zero cross detection transformer, C1, C2... Comparator,
DI, D2...Diode, PT...Voltage zero cross detection l/lance, RS 1 = RS 3-... Relay, 5l111~CI+ Ri-,, II 1
+ +-f No -ri Construction procedure amendment October 24, 1985 Patent application 1988-1.39649 2. Name of the invention Three-phase AC switch circuit 3. Relationship with the case of the person making the amendment Name of applicant's address (583) Matsushita Electric Works Co., Ltd. Representative 4, Agent address: 1-13-38 Nishihonmachi, Nishi-ku, Osaka Shinko Sangyo Building Country Equipment EX 0525-5985 INTAP
T J International FAX Gt[[&Gn (06)538
-0247 Tsuru %, ltlF, +M
ITH6, Claims column of the specification to be amended, Detailed Description of the Invention column and Drawing 7, Contents of the amendment (1) The claims are as shown in the attached sheet. (2) In the 13th line of page 6 of the specification, the phrase "installed" is corrected to "grounded." (3) In the first line of the specification @14fi, 1 pressure E in ['
[Correct the word adJ to read voltage EabJ. (4) 1 is restored in Ming #I, page 20, line 20 to page 21, line 1, and tJIJ, page 21, line 10,
Correct the statement to ``return to''. (5) Figure 1 of the drawings shall be corrected as shown in the attached sheet. More than 8 days I++ Mt 1 size no -l 5
2 books offshore C cusp 1 mu 1 $ 1) shi W Lll
1114 IP+W No. 1 First switch, second switch, and tj connected in series to the first, second, and third phase lines of the All Sanwa AC power supply.
Between the S3 switch and the line between the f51 phase and the second phase, a voltage detection 2S line connected to the power supply side than the first switch upper V second switch, and a voltage detection line 2S connected in parallel to the second switch. 1 diode, a tJS2 diode connected in parallel to the riS3 switch, a t51 current detection element provided in connection with the second phase line, and a second current detection element provided in connection with the third phase line. , in response to the output from the voltage detection winding, at the zero crossing of the voltage! The nl switch is turned on and the first or second
In response to the output from the current detection element, after the second and third switches are cut off, a period of time in which the radio waves are in the opposite direction to the first and second diodes is set. and in response to the output from the first current detection element, after the first switch is turned on, the second switch is turned on during a reverse current period for the first diode;
means for cutting off a second switch during a forward current period for the first diode;
A three-phase alternating current switch circuit having a W characteristic, comprising means for conducting a switch and for cutting off a third switch during a period of forward current to the t52 diode.

Claims (1)

[Claims] A first switch, a second switch, and a third switch connected in series to the first, second, and third phase lines of a three-phase AC power supply; Between the lines with the two phases, a voltage detection winding is connected in the first switch to the power supply side rather than the second switch, a first diode is connected in parallel to the second switch, and a voltage detection winding is connected in parallel to the third switch. a second diode connected to the second diode, a first current detection element provided in connection with the second phase line, a second current detection element provided in connection with the third phase line, and the voltage detection winding. In response to the output from the line, the first switch is made conductive at the zero crossing of the voltage, and in response to the output from the first or second current sensing element, after the second and third switches are cut off, the first and means for cutting off the first switch during a period in which the current is in the reverse direction to the two diodes; means for making the switch conductive and causing the second switch to be cut off during a period of forward current to the first diode; 3rd to current period
A three-phase alternating current switch circuit comprising: means for making the switch conductive and for making the third switch cut off during a period of forward current to the second diode.