JPS61296628A - Three-phase ac switching circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a three-phase AC switch circuit, and more particularly to a three-phase AC switch circuit that uses a relay switch to perform zero-crossing switching.

BACKGROUND ART Electromagnetic switches (magnetic relays), solid state relays (SSR), and the like are used as switches for three-phase AC circuits. Among these switches, electromagnetic switches have low conduction resistance (ON resistance) and generate less heat when energized, resulting in a lower temperature rise, so they can be made smaller, and solid-state relays have no mechanical contacts, so they have a long life. On the other hand, electromagnetic switches have short lifespans due to contact damage caused by arcing during switching, and solid-state relays have high conduction resistance (ON resistance) and require large heat sinks to generate heat when energized. It is difficult to miniaturize.
There was α. Therefore, there has been a demand for a compact electromagnetic switch that has a low conduction resistance t when energized, generates little heat, has a long life, and has a long life.

Purpose The purpose of the present invention is to solve the above-mentioned technical problems, incorporate the advantages of conventional electromagnetic switches and solid-state relays, compensate for their shortcomings, and provide a compact and long-life Shimoswitch circuit with low conduction resistance. That's true.

Example FIG. 1 is an electrical circuit diagram of an embodiment of the present invention.

The phases a, b, and c of the phase alternating current power supply AC are connected to the power supply terminals al, bl, and el of the three-phase alternating current switch circuit 1, respectively, and constitute a two-phase load Z.
b.

Each phase load of Zc is connected to load connection terminals a2, b2, and e2, respectively. A relay switch 5w1a is interposed between terminals al and a2. terminal bl, l)
A relay switch sw2 is interposed between the two. In addition, a first voltage zero cross detection transformer P is connected between terminals ml and b1.
A series circuit of a TI secondary coil L2 and a resistor R1 is connected, one terminal of a relay switch 5w1b is connected to the terminal b1, and a diode D is connected to the other terminal.
The anode of the diode D1 is connected to the diode D1, and the cathode side of the diode D1 is connected to the terminal b2.

A relay switch sw4 is interposed between the terminals cl and c2, and a secondary coil L4 of the 2'IIl voltage zero cross detection transformer PT2 and a resistor R are interposed between the terminals bl and c1.
Two series circuits are connected. Further, one terminal of the relay switch S replacement 3 is connected to the terminal c1, and the 7th node side of the diode D2 is connected to the other terminal. The primary coil L1 of the 1'IIL voltage zero cross detection transformer PTI is connected to comparison input terminals Pi and P2 of the control circuit 3. Further, the primary coil L3 of the second voltage zero cross detection transformer PT2 is also connected to the comparison input terminal P3.
．． Connected to P4.

The relays R8I to R34 are connected to output terminals P5, P6, P forming each village of a relay drive circuit (not shown) of the control circuit 3.
7, P 8, P9. PIO%Pi 1. They are connected to PI3 in this order. Relays R3I to R84 are the relay switches swl a, 1 b1 sw2.8w3
, sw4 individually in this order. The power supply voltage +Vcc is connected to the terminal P13 of the control circuit 3, and the terminal P13. Resistor R3 is connected to P14 open, and terminal P
14. Switch SW is connected to P15 open, and when switch SW is open (OFF), terminal P14 is at rHJ level, and when switch Sw is closed (ON), terminal P14 is at rHJ level.
[, becomes J level.

FIG. 2 is a circuit diagram of the control circuit 3. The aforementioned comparison input terminals Pi and P2 are connected to the inputs of the comparison circuit C1, and the output terminal of the comparison circuit C1 is connected to the input terminals of the @i differentiation circuit Q1 and the second differentiation circuit Q2. In addition, the comparison input terminal P3. P4 is connected to the comparison input terminal of the comparison circuit C2, and the output terminal of the comparison circuit C2 is connected to each input terminal of the third differentiation circuit Q3 and the fourth differentiation circuit Q4. The output terminal of the first differentiating circuit Q1 is connected to the third input terminal of the 3-person AND date G1, and the second input terminal of the 3-person AND date) G5.
The output terminal of the 29th branch circuit Q2 is connected to the input terminal.
Human power AND date G2! @2 input terminals and 3 human power A
ND day) is connected to the first input terminal of G6. Third
The output terminal of the differentiator circuit Q3 is the 3rd input terminal of G3 and the 4th input terminal (AND) of #52 of G7.
connected to the input terminal. The output terminal of the fourth differentiating circuit Q4 is connected to the third input terminal of the 4-man power AND day) G4 and to the tlS3 man-power terminal of the 3 man power AND day) G8. Power supply voltage +Vcc is connected to terminal P13,
Terminal P13. A resistor R3 is connected between terminals P14. P1
5 is connected to the ON10 FF switch S field, and the terminal P15 is grounded.

The input terminal P14 is connected to the input terminal of the input inter 7 ace C3, and the input inter 7 ace C3 has an output rHJ corresponding to the switch inter mode of the switch SW.
Or derive rLJ to line No. 1. Line J! i is the input terminal of the first delay circuit DLI, NOT data) G9
input terminal, and 3-man power AND day) G20. G22
．． G24. It is commonly connected to each second input terminal of G26. ! Note: The output terminal of G9 is 3-man power A.
ND date G19. G21. G23. It is commonly connected to each second input terminal of G25. First delay circuit D
The output of L1 is branched, one to the input terminal of NOT data) G33, and the other to the input terminal of AND data) GIO, G11 and 1N.
OR day) G12. They are commonly connected to one input terminal of G13. The output of the NOT date G33 is branched, one being connected to the input terminal of the second delay ffi circuit DL2, and the other being connected to one input terminal of the EX-OR date G14. The output of the second delay circuit DL2 is branched, and one is connected to the input terminal of the third delay circuit DL3, and the other is connected to the other input terminal of the AND date G11 and the NOR date G12. 13 delay circuit DL
The output of 3 is the other input terminal of the EX-OR data) G14 and the NOR data) G13, AND data) Gl
0, respectively, are connected to the other terminal of the terminal. EX-OR
Date G14 output terminal 1i3 manual AND? -)Gl
9. G20. G21,..., G25, G26
are commonly connected to each third human power terminal. here 3
Manual AND data) G19 to G26 all derive the set output or reset output of the relay drive circuit, which will be described later. The output of the above AND5'-) G10 is the result of the three-man power AND day) G6. The output of the AND date G11 is connected to the first input terminal of the 3-person AND date G5 and the third input terminal of the 4-person AND date G7. NOR Day) G 13
The output J! Three people AND? -) G2's! The s1 input terminal is connected to the second human power terminal of 3 human power AND5/-)G3, and the output of NOR date G12 is the 3 human power AND day)Gl second human power terminal and the 4 human power terminal of G4
are respectively connected to the second human power terminals of the terminals. 3 person power AN
The output of the D date G1 and the output of the 3-manual AND date G5 are each individually connected to the input terminal of the NOR date G15, and the output of the NOR date G15 is connected to the input terminal of the first one-shot circuit F1. The output of the 3-person AND date) G2 and the output of the 3-person AND date G6 are each individually connected to the input terminal of the NOR date 616, and the output of the NOR date) G16 is connected to the input terminal of the #IJ2 one-shot circuit F2. ing. 4 person AND
The output of D) G4 and the output of D) G7 are individually connected to the input terminals of N0R5'-) G17, and NOR? -) The output of Gl 7 is connected to the input terminal of the third one-shot circuit F3. 3 person power AN
D? -) The output of G'3 and the output of 3-man AND date G8 are individually connected to the input terminal of NOR date 618. The output of the first one-shot circuit F1 is connected to the input terminal of the third input terminal A.
ND date G2.4 human power AND date G4.3 human power AN
3rd input terminal of D date G6 and 4 person power AND date)
Connected to the fourth input terminal of G7, and further AND date G
It is connected to one input terminal of 29. tJIJ2 The output of one-shot circuit F2 is NOT day) G27°G2
8 input terminals and 3 more manual AND day) G21, G24
are commonly connected to the first input terminals of the two. The output of said NOT day) G27 is connected to the first input terminal of the three-man power AND day) G1 and the third input terminal of the three-man power AND day) G5. The output of the N0TP-)G2B is connected to one input terminal of the AND-)G29.

AND date G29 output terminal is 3 person power AND date)G
19. It is connected to each first input terminal of G2B. Third
The output of one-shot circuit F3 is 3-man power AND day)G3
．． It is connected to each first input terminal of G8 and one input terminal of AND date G32. The output of the fourth one-shot circuit F4 is connected to each input terminal of NOTOR date G14G31 and 3-man power AND date) G20. Each of the first input terminals of G25 is connected to the first input terminal of G25. Said NOT Date G
The output of 30 is 4 people AND date G4. It is connected to each first input terminal of G7. *TA NOTOR Date G14
is connected to the other input terminal of the AND date G32, and the output of the AND date G32 is the 3-man power AND date) G2
2. Each of the first input terminals of G23 is connected to the first input terminal of G23. In the first relay drive circuit, the set input terminal s1 of 1 is connected to the output terminal of the 3-person AND date G19, and the reset input terminal 1 is connected to the output terminal of the 3-person AND date G20.The second relay drive circuit The set input terminal s2 of 2 is connected to the output terminal of G21 (3-man power AND day), and the reset input terminal r2 is 3-man power AND
data) is connected to the output terminal of G22. 3 set input terminal s3 to the 3rd relay drive circuit is 3 manual input terminal
The reset input terminal r3 is connected to the output terminal of the three-man power AND5'-)G24.

In the fourth relay drive circuit, the set input terminal s4 of 4 is connected to the output terminal of the 3-man power AND date) G25, and the reset input terminal r4 is connected to the output terminal of the 3-man power AND date G2f3.

Output terminals P forming each village of 1 to 4 in the above relay drive circuit
5, P 6, P 7, P 8, P9. The coils of relays R8I to R84 are connected to PIO, pH, and PI3, respectively, and when the set input terminal of each relay drive circuit is rHJ, the corresponding relay switch is activated, and when each reset input terminal is "H", the corresponding relay switch is activated. The corresponding relay switch is deactivated.

3 is a waveform diagram of each part of the three-phase AC circuit of FIG. 1, and FIG. 4 is a timing chart of the control circuit of FIG. 2. The operation of a three-phase AC switch circuit according to an embodiment of the present invention will be explained below by comparing FIGS. 1 and 2 with FIGS. 3 and 4.

In the MS1 diagram, the first voltage zero cross detection transformer P
The primary coil L1 of the TI has two terminals a l in series with the resistor R1.
t b 1, and the waveform of the voltage Eab shown in FIG. It is applied to the comparator circuit C1. Further, the primary coil L3 of the second voltage zero-cross detection transformer PT2 is connected in series with the resistor R2 between the terminals bl and c1, and the secondary coil L3 is connected in series with the resistor R2 between the terminals bl and c1.
4, the waveform of the voltage Eca shown in FIG. 3(3) is derived, and the detected waveform is applied to the terminal P3.4. It is applied to the input comparison circuit C2 shown in the second diagram via P4. As a result, the comparator circuit C1
At the output terminal of , a level change H-L falls at the zero cross point when the voltage Eab changes from positive to negative, and a level change L falls at the zero cross point when the voltage Eab changes from negative to positive.
A voltage Eab zero cross detection signal at the rising edge of −4H is derived. Similarly, the voltage Eab zero cross detection signal is derived from the output terminal of the comparison circuit C2.

When applying power to the three-phase load Z, the ON10 F F switch SW is turned on at time To shown in tIIJ4 diagram (1).
When closed, terminal P14 changes from rHJ level to “T
l ++ A+++-1- 亦ILp l = 7
1% L+ -1z+ +, -+ ++ 亦1 and 14
The ON signal shown in FIG. 14 (2) is derived to line No. 1 via the input interface 721 C3, and this ON signal is given to the input terminal of the first delay circuit DLI, which is connected to the ON10 described above. In order to cancel the bounce waveform at the time of opening and closing of the FF switch SW, a delay time t1 is set in advance with respect to time To, as shown in Fig. 4 (2).
) At the time T1 shown in FIG. -) Inverted at G33 and second delay circuit DL
The second input terminal is applied to one of the input terminals of the EX-OR date G14.

The second delay circuit DL2 is used to obtain the Eab zero-cross detection signal necessary to make the relay switch swl at swl b shown in the diagram conductive when the diode D1 is conductive when power is applied, and to obtain the Eab zero-cross detection signal necessary to make the relay switch swl at swl b shown in the diagram conductive when the diode D1 is conductive, and to activate the relay switch sw3 when the diode D2 is turned off. In order to obtain the Eca zero cross detection signal necessary for conduction, open L2 (t2≧
7π/3), and the signal B shown in Figure (3) of tjS4 is derived to the input terminal of the tI&3 delay circuit DL3.

The third delay circuit DL3 makes the relay switch sw2 shown in the first diagram conductive when the diode D1 is conductive when the power is applied, and the relay switch sw4 is made conductive when the diode D2 is conductive in order to obtain the EAB zero-cross detection signal necessary for making the diode D1 conductive. In order to obtain the above-mentioned Eca zero cross detection signal necessary for
G14 is derived from the other input terminal of the signal C and the inverted output of the aforementioned signal A.
The X-OR output is derived to line No. 3.

The Eab zero-crossing detection signal rises at the first detected zero-crossing point of Eab from negative to positive after the level change, that is, time T2 in FIG. 3(2), and this causes the first One shot circuit F
1 operates and derives a signal having W 1 (W 1≧3A−π) during a preset time at time 32 shown in FIG. 4(5).

The Eab zero-crossing detection signal falls at the zero-crossing point from positive to negative voltage Eab obtained during the signal period, that is, at $11T4 in FIG. 3 (2), and this causes the second
The one-shot circuit F2 operates and derives a signal E having W (W2≧X) during a preset time at time T4 shown in FIG. 4 (6).

The Eca zero-crossing detection signal falls at the zero-crossing point from positive to negative of the voltage Eca that is detected first after the level of the signal A changes from H to L, that is, at time T3 in FIG. The shot circuit F3 operates and derives a signal F having a preset time period (W3≧2K) at time T3 shown in FIG. 4(7). Therefore, signal F is derived before said signal E.

E at the zero-crossing point from negative to positive of voltage Eca obtained during the period of signal F, that is, at time T5 in FIG. 3(3).
The ca zero cross detection signal rises, which causes the fourth
The fun shot circuit F4 operates and W 4 (W 4≧
π).

The AND output of signal RI, the inverted output of signal E, the inverted output of the OFF signal obtained via line 12, and the EX-OR output of Gl 4 obtained via line 3 are 3-man AND. The set signal SIS shown in FIG. 4 (14) is applied to each input terminal of the date G19, and the set signal SIS shown in FIG. b becomes conductive in conjunction with the fourth ff1 (9L (10)).

The AND output of signal F and the inverted output of signal G, the inverted output of the OFF signal given via line node 2, and the EX-OR date output given via line node 3 are 3.
It is given to each input terminal of human power AND date G23,
The set signal S3S shown in FIG. 4 (16) is outputted to the third relay drive circuit, the relay R83 is driven, and the relay switch sw3 shown in the first diagram is outputted as shown in FIG. 4 (12).

Signal E, the inverted output of the OFF signal provided via line 12, and EX-OR provided via line 3
The output of the date G14 is 3. A set signal S28 shown in Figure A (15) is derived to the second relay drive circuit, and the relay R82 is driven to switch the relay switch sw shown in the first figure.
2 is electrically connected as shown in FIG. 4 (11).

The signal G, the inverted output of the OFF signal given through line No. 2, and the output of EX-OR date G14 heard through line No. 3 are given to each input terminal of 3-power AND5'-) G25, and the fourth The set signal S4S shown in FIG.
84 is activated, and the relay switch sw4 shown in the first figure becomes conductive as shown in FIG. 4 (13).

Relay RIS is first driven by each of the above-mentioned signals to make relay switch swl conductive, and then relay R33 is driven when diode D2 is cut off to make relay switch swl conductive.
becomes conductive, then relay RS2 is driven when diode D1 is conductive, relay switch sw2 is rendered conductive, and finally relay R84 is driven when diode D2 is conductive, and relay switch S-4 is rendered conductive.

Through the above-described series of operations, power energization of a three-phase load using a relay switch can be realized with zero crossing.

When the ON10 FF switch S field is opened during power de-energization, the terminal P14 changes to the rLJ level, and this level change L-, H occurs at a preset time t1-t3 by the delay circuit DI, ~DL3. The output changes respectively.

First, at time TIO shown in FIG. 4(3), the level "L" of the ON signal is inverted to rHJ. Hereinafter, this inverted signal will be referred to as an OFF signal.

The above-mentioned OFF signal is turned off for a time t by the delay circuit DLI in FIG.
After one delay, the signal A becomes an inverted output at time Tll in FIG. 4(2). The first zero-crossing point of voltage Eab from negative to positive after signal A changes to L-hH, that is, the third
Figure (2) Eafr zero cross detection rises at time T12, and this rise causes the first one-shot circuit F1 to
operates and derives the signal again at time T12 in FIG. 4(5).

The Eca zero-crossing detection signal rises at the zero-crossing point of the voltage Eca obtained during the signal period from negative to positive, that is, time T14 in FIG. (
7), the signal F is derived again at time T14.

The Eab zero-crossing detection signal falls at the zero-crossing point from positive to negative voltage Eca obtained during the signal period, that is, time T13 in FIG. 3 (2), and this falling activates the second one-shot circuit F2. The signal is derived again at time T13 in FIG. 4(6).

The Eca zero-crossing detection signal falls at the zero-crossing point from positive to negative voltage Eca obtained during the period of signal F, that is, at time T15 in FIG. 3 (3), and this falling activates the fourth one-shot circuit F4. At time T15 in FIG. 4(8), the signal G is derived again.

AND output with the inverted output of the signal E, the OFF signal, and the line! EX-OR date G given through 3
The output of 14 is given to each input terminal of the 3-man power AND date G26, and is shown in FIG. 4 (18)! #4 relay R
The reset signal S4R of 84 is applied to the 4th reset signal terminal of the 4th relay drive circuit, and as shown in FIG. 4 (13), the relay R84 is restored and its relay switch sw3
Be cut off.

Signal E, OFF signal, and line J! EX-OR day given through 3) Gl 4 output is 3-man power AND
Given to each input terminal of date G24, Fig. 4 (19)
Reset signal S3R of #IJ3 relay R83 indicated by
is applied to the reset signal terminal 3 of the third relay drive circuit, and as shown in FIG. 4 (12), the relay R83 is restored and its relay switch sw3 is cut off.

Next, the AND output of the signal F and the inverted output of the signal G, and the OF
F signal and line! The output of the EX-OR date G14 given through 3 is given to each input terminal of the 3-man AND date G22, and the reset signal 9S2R of the second relay R32 shown in FIG. 4 (20) drives the second relay. As shown in FIG. 4 (11), relay R32 is restored and its relay switch sw2 is applied to the reset signal terminal 2 of the circuit.
is blocked. Finally, the signal G, the OFF signal, and the output of the EX-OR date G14 given through the line No. 3 are given to each input terminal of the 3-man power AND date G20 and the first relay shown in #IJ4 diagram (21) The reset signal SIR of R8I is applied to the reset signal terminal of the first relay drive circuit vrK1, as shown in FIG. 4 (9).

As shown in (10), relay R8I is restored and its relay switch swl at swl l) is interlocked and cut off.

As mentioned above, each signal sends 1 to 4 to the relay drive circuit.
Reset signals 5IR-84R are formed, and by applying these reset signals to the reset signal terminals of each relay drive circuit, the relay switch sw4 is first cut off when the diode D2 shown in the first diagram is made conductive, and then the diode D1 is made conductive. When the relay switch sw2 is cut off, then when the diode D2 is cut off, the relay switch swl a
t swl b are interlocked and cut off, and finally, when the diode D1 is cut off, the relay switch sw3 is cut off. Through such a series of operations, power energization of a three-phase load using a relay switch can be realized with zero crossing.

Effects As described above, according to the present invention, the phase difference between the two phases of a three-phase AC circuit is detected and the relay switch is activated to perform zero-cross switching, thereby preventing the occurrence of arcing when switching the load. It is possible to realize a three-phase AC switch circuit that is small in size and has a long life due to the low heat generation and no damage to the contacts. In addition, leakage current generated during voltage phase detection in an open circuit is prevented from flowing to the load, and a three-phase AC switch circuit capable of zero-cross switching in which the power supply side and the load side are completely isolated can be realized.

[Brief explanation of the drawing]

1 is an electric circuit port of a three-phase AC switch circuit, FIG. 2 is a circuit diagram of a control circuit, FIG. 3 is a waveform diagram of the three-phase AC switch circuit, and FIG. 4 is a timing chart of the control circuit. 1... Three-phase AC switch circuit, 2... Control circuit, A
C... Three-phase AC power supply, CI, C2... Input comparison circuit, DI, D2... Diode, DLI to DL4...
Delay circuit, F1-F4...Funshot circuit, K1-
4...Relay drive simultaneously, PTI, PT2...Zero cross detection transformer, R8I to R84...Relay, 5
W-ON/OFF switch, swl ay
swl b, sw2 wam13, sw4...Relay switch, Z...Three-phase load agent Patent attorney Number of strokes
Kei Part Procedural Amendments October 24, 1985 1,! Office Director's Palace 2, Name of the invention Three-phase AC switch circuit 3, Relationship to the case of the person making the amendment Applicant's address name (583) Matsushita Electric Works Co., Ltd. Representative 4, Agent address 1-chome Nishihonmachi, Nishi-ku, Osaka No. 13-38 Shinko Wave Building Country Equipment EX 0525-5985 1NTAPT
J International FAX GIII & G II (06)538
-02476, Detailed explanation of the invention column 7 of the specification subject to amendment, Contents of amendment (1) 1' in lines 3 to 4 of page 15 of the specification
-EAB zero-crossing detection signal”, l”Eab
Correct to "Zero Cross Detection Signal". (2) Specification @ page 18, line 1S [Relay RIS
J is corrected to [relay R8IJ]. that's all

Claims (1)

[Scope of Claims] A first switching means, a second switching means, and a third switching means respectively interposed in series in the first, second, and third phase lines of a three-phase AC power source; A plurality of voltages are detected between the phase and the second phase and between the second phase and the third phase, and each line is connected to the power supply side rather than the second switching means and the third switching means. a detection means, a first control circuit that controls opening and closing operations of the first switching means, and second and third control circuits that control opening and closing operations of the second and third switching means based on signals from each voltage detection means. and the first switching means includes a first relay switch;
The second switching means includes a second relay switch and a third relay switch, the first diode is connected in series to the third relay switch, and the third switching means includes a fourth relay switch.
a relay switch; and a fifth relay switch.
A second diode is connected in series to the relay switch, and the second relay switch and the fourth relay switch conduct conduction/interruption operations in response to each case of forward current and reverse current regarding the first diode, respectively. and the third relay switch and the fifth relay switch are controlled to conduct conduction and cutoff operations, respectively, in response to each case of forward current/reverse current with respect to the second diode. Phase AC switch circuit.