JPS60175127A - Ac switch circuit - Google Patents

Abstract

PURPOSE:To suppress the power consumption of a relay coil at a low level by detecting the change of the on/off state of the 1st and 2nd relay switches and preventing the regeneration of a relay driving signal. CONSTITUTION:A relay control circuit Y in an AC switch circuit turns on/off relay switches a1, a2 by the outputs of a current transformer CR and a voltage transformer PT and supplies AC power supply EO to a load L. As to the driving status of the relay switches a1, a2, current at the ON of the switches a1, a2 is detected by said current transformer CT and the voltage at the OFF of the switches a1, a2 is detected by the voltage transformer PT. The change of the relay switches a1, a2 from OFF to ON is detected by the change from the voltage detection to the current detection to control respective relay coils. Power is supplied to the load L by turning on the relay swithc a1 at the disconnection of the diode d and turning on the other relay switch a2 at the succeeding half wave. At the disconnection of the power supply, the switches a1, a2 are turned off.

Description

[Detailed description of the invention]

TECHNICAL FIELD The present invention relates to an AC switch circuit interposed between an AC power source and a load that prevents arcing between contacts that open and close. BACKGROUND ART Conventionally, relay switches and the like have been used to turn on/off the connection between a load and a power source. In order to minimize arcing between the contacts during on/off operation of the relay switch, the following steps were taken. Using a transformer that detects the entire voltage applied to the load from the power supply, a current transformer that detects the current, etc., each output of the transformer and current transformer and the input that generates the drive signal that drives the relay switch are used. By matching the signal, the relay switch was controlled to operate without arcing. Such transformers and current transformers are expensive and require a large circuit. Furthermore, the number of parts of the phase detection circuit formed by the 4i'7 circuit using transformers and current transformers increases, resulting in an increase in cost for the entire circuit. - If a non-contact semi-conductor switching element such as FC or Cyrisk is used, arc-free switching can be performed, but since the on-resistance of Cyrisk is large, the voltage drop when turned on is large. Moreover, the heat generated by this also increases. Purpose The purpose of the present invention is to solve all the technical problems mentioned above. To provide an AC switch circuit that performs opening and closing operations without arcing, is inexpensive, and consumes little power. Embodiment FIG. 1a is an electric circuit diagram for explaining a basic operation of an embodiment of the present invention. When supplying electricity from AC power supply EO to the load, relay switch ali diode D
The primary relay switch a2' (r
- When diode D is conductive, it is turned on. Conversely, when completely cutting off the power from the AC power supply EO that is being supplied to the load, relay switch a2i is driven off when diode D is conductive, and relay switch al is first driven off when diode D is shut off H'Jr. let Figure 2 is a block diagram for explaining the overall configuration of an embodiment of the present invention. The relay control circuit Y receives the output of the current transformer CT and the output of the transformer PT, detects all phases of the power given to the load from the AC power supply EO, and turns on/off the relay switches al and a2. let In other words, the relay switches al and a2 are turned on and off at the operation timing explained in section 1(9) above. In addition, the transformer PT has relay switches al, a2
The voltage of the AC power source EO is detected when the current transformer CT is off, and the total current of the AC power source EO is detected when the relay switches al and a2 of the current transformer CT are on. Based on this force, the ON/OFF state of the relay control circuit Y, relay switches al, and a2 is detected. In other words, the output of transformer I) 1' is in phase with the AC power source EO (or in opposite phase) when detecting voltage, and the output of current transformer CT is in opposite phase (or in phase) with AC power source EO when detecting current. By this, relay control circuit Y changes from voltage detection to current detection, that is, relay switches al, a2 (
7) All changes from off state to on state can be known. In addition, the relay control circuit changes from current detection to voltage detection, that is, relay switch AL. It is possible to know the change of a2 from the on state to the off state. As a result, the relay control circuit Yt stops supplying power to the relay coils driven by the relay switches al and a2i. g! FIG. 3 is an electrical circuit diagram of an embodiment of the present invention. With reference to the timing chart of FIG. 4, the entire operation when power is applied to a load will be explained. (1) Output U of coil L2 of transformer T, diode D
I, clamped by D2 and given to comparator l〇(2)
When the relay switches al and a2 are in the OFF state, the two outputs of the coils of the transformer T generate outputs in phase with the AC power source EO and 11-phase. Figure 4 +11 is the voltage 1 voltage v of AC power supply EO
+21 in FIG. 4 shows the input of comparator 1. (3) The comparator 1 converts the output of the coil L2 of the transformer T into a rectangular waveform, and generates pulses in the positive direction at the rise and fall of the output. Figure 4 (3) shows AND gate 3
The output P3 of the NOR gate 4 is shown in FIG. 4, and the output P4t of the NOR gate 4 is shown in FIG. In other words, this output P3゜P4 becomes the 0 point detection pulse of the AC power supply vehicle pressure VO. When the signal P5 changes from a low level to a high level, the time limit circuit TM4 operates at the rising edge of the signal P5, and the time limit circuit TM4 operates as one cycle of the AC power supply EO + tl.
Pulse I1gW4? It has a pulse P6 of +44 and +61. (5) OV point detection where the phase of the output of the time limit circuit Th14 and the AC power supply voltage vO changes from negative to positive (hereafter color 1
detection pulse) and a time limit circuit TR41. By ANDing the output of T M 2 with the inverted signal of the OR output, the input signal P5 changes from low level!・The first detection pulse shown in Figure 4 (7) after the level IC is turned on is A.
Obtained from ND Game) 21. (6) The above 'A I detection pulse t-t generates a pulse at the falling edge of the rectangular wave with the time limit circuit TM6 in order to generate an IC relay drive signal so that the relay switch a1 turns on when the diode D is cut off. gate 24 and NO'ROR gate 34.

[Delayed by 1 h. The pulse P8 shown in FIG. 4 (8) is sent out from the time limit circuit TMO, and the output power from the AND gate 26 is shown in FIG.
A pulse P9 shown in 9) is sent out. However, the time t
l t'i,, Shorter than half cycle of AC power supply voltage ■0. (7) First detection pulse P9 delayed by time tl. Time limit circuit TM1'5-! for generating relay drive signal! III
0 time limit circuit T M 1 to make J, Figure 4 (11
) is sent out, and its pulse width W1 is half the cycle of the voltage VO. On the downhill] (time limit circuit TM for generating a pulse and generating a relay drive signal
2'? make it work. From the time limit circuit TM2, the circuit shown in Fig. 4 (
A pulse P12 shown at 121 is sent out, and the pulse width W2 is longer than the relay ON operation time tON.
output P13 and input signal I'5? The ON drive signal P, 14 for the relay switch a1 shown in FIG. 4 (14) is generated by AND with the noise-cut signal P5, and current flows through the relay coil due to the upward movement. 1101 Also, the A of the time limit circuit T M 2 and the input signal P5
1g4 FIG. 11 [i
1.) When the on-driving signal P15 of the relay switch a2 shown in ) is not obtained. This causes current to flow through the relay coil. (Nakasuke, here relay switch al+a 2f) 'Suppose that it did not turn on due to a malfunction. (The pulse generated at the rising edge of the input signal P5 also operates the time limit circuit TM5 in addition to the time limit circuit TM4.
A pulse P25 shown in c) is generated. 0 cloudy again. First detection valve, D flip-flop FF
is applied to the trigger input terminal T of , via an OR gate 36. In addition, the input terminal of the D flip-flop FF is connected to the inverted output from the inverted output terminal Q and the time limit circuits TMI and TM2.
The output of an AND gate 35 which is ANDed with the OR output of is given. Therefore, the output from the output terminal Q of the D flip-flop FF is
The ml detection pulse generated when the R output is at a high level causes the low level to become a high level, and the next first
The detection pulse becomes I rehigh level and color low level. D
The output of the output terminal Q of the flip-flop 1FF is shown in Fig. 4 (
This is the pulse P18 shown at 181. (The 15I time limit circuit TM4 is an AND output of the output of the D flip-flop FF, the output of the time limit circuit TM5, and the 07 point detection pulse (hereinafter referred to as the second detection pulse) when the AC power supply voltage ■0 changes from positive to negative. The output of the time limit circuit TM4, which is generated again by !ILIJ, is the pulse P6 shown in FIG. , when relay switch a1 is in the cutoff state of diode D, it is turned on when relay switch a2 is in the conduction state of diode D. Due to gravity biasing, the output of coil L2 of transformer T is as follows. The voltage detection output becomes the tt flow detection output.As shown in Fig. 4 (2), the output of the coil L2 sends out the detection output 4 as a phase opposite to the AC power supply phase. 07) Time limit circuit T M 01d , the inverted signal of the time limit circuit TM4 and the time limit circuit TM1. 〇(18
The first detection pulse is delayed by 2 hours t1 by a circuit consisting of a time limit circuit TM (1) and a NOTOR gate 34 that generates a pulse at the falling edge of a rectangular wave, and N0R25, and the k first detection pulse is AND gate 27 with an inverted signal of time TM4.
In addition, the inversion of the output of comparator J (AN with fi
D? The signal is taken by an AND gate 38a, and is further taken by an AND gate 37a. Sara through OR gate 36, D flip flow l
"The tri-power terminal TG of F is applied, and the output of D flip-flop FF is changed from high level to low level. A
Vi from the N D gate 38a, the pulse shown in FIG.
The pulse shown in Figure (19:) is sent out.
Since the high level changes to the low level before being ANDed with the second detection pulse after the power is applied, the relay driving error signal no longer occurs after the power is energized. Note that Figure qA4 C/Jl+ shows the on/off state of relay switch al, and Figure 4 (
21) Indicates the on/off status of relay switch a2. Also, the 41st R1 shows the load current r. Next, refer to the timing chart in Figure 5. The operation when the load power is turned off will be explained. As shown in Figure 15 (2)) of 0!0) and Figure 5 21), when relay switches al and a2 are in the ON state,
As shown in Figure (2), the output 7 of the coil L2 of the transformer T [
, an output with a phase opposite to that of the load current shown in the fifth position occurs. (21) When the input signal P5 in this state changes from high level to low level, the time limit circuit TM4 operates at the falling edge, and the pulse P6? of pulse width W4? generate. (2a time limit circuit T M 4 output and time limit circuit TMI, T
AND of the OR output of M2 and the second detection pulse? Toru AN
D gate 2] output P7 causes the time limit circuit TM O'7
drive. From the time limit circuit TMO, Figure 5 (8)
A pulse P8 shown in is sent out. 2) The fl5 diagram (9
) is further delayed by a time t via the delay circuit DYZr. The delay circuit DY2 sends out the pulse shown in FIG. 5 (10). Here, for the time tl+t2, the relay switch a2 is turned off when the diode D is in the 4) oil state, and the relay switch a1 is turned off when the diode D2 is in the cutoff state, so that the relay is turned off in order to generate a relay pulse. The number of shifts is determined in advance, taking into account the time required for one production. (241 delay circuit DY2 output it, time limit circuit TMI is activated, and time limit circuit TM2 operates at the fall of the output of time limit circuit TM1. time limit circuit TR4) to i-j fifth
Figure (11 pulse pH is sent out, time limit circuit TM 2
[Figure 45 (Pulse P of 1 odor] 2 is sent out. I) Time limit circuit Tljil and TM 2 are ORed.
Output P13 of R gate 34 (d, input signal P5? AND with the inverted signal of noise-cut signal P5? Take AN
D gate:) 9 turns off tga11+signal P23 of the X-shaped relay switch a2 shown in FIG. Off drive signal P of relay switch al 24 tonal. Qη Off drive signal of relay switch a2.al 4n No. P
23, P24 causes current to flow through each relay coil. When relay switch a2 and diode I) are in a conductive state, relay switch alld and diode D are in a cutoff state and are turned off. (281 In this way, the power is de-energized without arcing. The time-limiting circuit TMI.
The signal from the output terminal Q changes from low level to high level, and the second detection pulse is delayed by the time tl and becomes fC.
Ws5 diagram (by Hi! pulse) - goes from high level to low level. ) Therefore, relay switch a2. After al is turned off, the off drive signal P23. P24 does not occur. As described above, the output of the transformer T is connected to the ON/OFF state of the relay switch a1+a2 fJM? Detect. Relay drive! Prevents reoccurrence of 1+IJ signal. Power consumption of relay coil by kneading? It can be kept small. FIG. 6 is an N air circuit diagram of another embodiment of the present invention. 6th
In the figures, the same reference numerals are given to parts corresponding to the drawing elements shown in FIG. First, refer to the timing chart of f471gl and explain the operation when energizing the load. do. 2 outputs on the coil of transformer 1, diode D1.
A force is applied to the comparator through the clamp circuit by D2. Comparator] input in Figures 19 to 7 (shown in 21. Since the output of the coil L2 of the transformer T is shaped into a rectangular wave,
The output of the comparator is a signal synchronized with the AC power supply voltage V (l). After cutting the output noise of this comparator, the NOTOR gate 13 and A generate 9 pulses at the rise of the rectangular wave.
By passing through the circuit of ND game (ND game) 5a, a pulse signal synchronized with the Ov point where the AC power supply voltage VO changes from negative to positive is generated. The pulse shown in FIG. 7 (31) is output from the AND gate 5a. In such a state, the input signal A4 changes from low level to high level. If the input signal A4 is a signal that has a bounce value , time limit m3TM at the fall of Irukai No. 11
3 operates and has a pulse width W3' of the time when the bounce meeting can be canceled. 9J< 7 Pulse Δ5 shown in Figure (5)
? - occurs. The output of this time limit circuit TM3 and the input signal A
OR with 4? By the OR gate 13, an input signal A6 with bounces canceled as shown in Fig. 6 is obtained. At the rise of the bounce-cancelled input signal A6, the time limit circuit TM5 performs an arbitrary operation. Pulse A7?/sending of pulse width W5 shown in 7th Cabinet (7), 1) Provide time to decide whether to send excitation current to the v-coil 0 Inverted signal of time limit circuit TM5 and time limit circuit Tλ14 ( In this case, A between the H level) and the 07 point detection pulse in Figure (3) @7
ND? The rAND gate 8a operates the time limit circuit TMO'. The pulse 88 shown in FIG. 7(8) is sent from the timer circuit T to the time limit circuit T. Time limit circuit T M Ol/'i Relay switch a1 turns on when diode D is cut off, so that the relay drive signal light is generated.jl)NTrConsiderationNj
, l, te(l The time sound for delaying the V point detection pulse is set. The pulse width tl of the pulse 88 is [!pressure v
Make it shorter than half the period of O. The output of the time limit circuit TMO is passed through the NOTOR gate 13 and NOROR gate 13 circuits that generate pulses at the falling edge of the rectangular wave, so that the 07 point detection pulse is detected at time r! l t delayed by 171
．． AND' with the inverted signal (H level in this case) of the OR output of time limit circuit TMI and time limit circuit TM2.
1-AND gate 13a and further bounce-cancelled input signal with 6 (ANI)? r and is applied to the time limit circuit TMI through the OR gate 31''f.The time limit circuit Tλ11 is connected to the relay switch a l't IIJ.
After issuing the signal to operate, relay switch a2'? Approximately half the period of the voltage vO is set up to generate the operating signal, and at the fall of the output, the time limit circuit T M 2 k !
Let's make 1ilJ. Time limit circuit TMI Karakake @7 diagram (ti
A pulse AIO shown at ll is sent out from the time limit circuit TM2. f47 Pulses All shown in Figure (11) are sent out h. The time limit circuit Tλ12 is provided to ensure the operating time when the relay is on, and the pulse width of the pulse All is set to be longer than the operating time tON when the relay is on. Time limit circuit T
MI, TM2 OR? AND' (output #-t of the AND gate 40 taken by r-t,
When the relay switch ai is turned on, the drive signal becomes A13. AND gate 3 that ANDs the time limit circuit TM2 and the bounce-cancelled input signal A6
The output of 8 is. When the relay switch a2 is turned on, the drive signal AI4 shown in FIG. 704 is obtained. Each ON drive signal Al3. A14 is high level ru+, excitation current flows through the relay coil,
Relay switch al is turned on when diode D is cut off, and relay switch a2 is turned on when diode D is turned on. The high level of the signal shown in 711i% 1071 indicates the on state of relay switch al. The high level of the signal shown at fB 71V (+8i) indicates that relay switch a2 is in the ON state. Through the above operation, the load cannot be energized without arcing. Time limit circuit TMOI/'i, time limit circuit TM5 While the output is at high level, it operates by the 07 point detection output. 0V point detection pulse pulse A8# delayed by the meeting time t1
-i, time limit circuit TM1. OR output of TM2 and comparator 1
AND with the inverted signal? The relay switch is operated by the output of the AND gate 11a which takes r, and only when the l1lt force is energized, a full pulse is generated. The pulse 15 shown in FIG. 7 (15j) is generated from the ANDG) 11a.In other words, the output of the coil L2 of the transformer T is in phase with the AC power supply voltage vO when the power supply voltage is detected, and the pulse 15 shown in FIG. It is connected so that the output with the opposite phase to the voltage V (+) is ?4J. Therefore, when the power is energized, the phase of the coil L2 output of the transformer T changes from the same phase of the AC power supply voltage ■0 to the opposite phase. . Only the pulse A15, which is delayed by the time t1 from the 0 point detection pulse generated at this time, is obtained. This pulse A15 causes the time limit circuit TM4 to operate 101 times. The 07 point is detected when the output of the time limit circuit TM4 is at a high level. The time limit circuit T hlo will not operate due to the pulse. Figure 1iA7 of the time limit circuit TM4 (pulse width W4'e W4 of output pulse A16 shown at +61) WS-tl-W
l, when the output of the time limit circuit TΔ14 goes from high level to low level, the output of the time limit circuit TM5 is at low level, so the time limit circuit TM(+, TM
I, TM2 does not work. Therefore, when the relay is turned on, the drive signal A13. '□A14 also does not occur. In other words, after the relay switch al'+a2 is turned on, the current flowing through the relay coil when it is on does not flow. Next, with reference to the timing chart of FIG. 8, the operation when power is turned off under load will be described. relay switch al, a
When T2 is on, one transformer T whose output is in the opposite phase to the load current phase is generated as shown in Figure (2) of @8. The output of the coil L2 of the transformer T is waveform-shaped into a rectangular wave by the comparator l, and the NOT game having a delay time) 4a and A
The signal is applied to a circuit that generates a pulse signal at the rising edge of a rectangular wave formed by the ND gate 5a. This AND gate 5a
It is synchronized with point 07 where the phase of the pulsed lamp load current changes from positive to negative shown in fBs diagram (3) from . From then on, the 8th m (3
The T pulse is called the second detection pulse. In this state, when the input signal B4 changes from high level to low level, the time limit circuit TM3 operates at the fall of the input signal B4, and the pulse width W of the time provided for bounce cancellation is activated.
3 pulses B5 are generated. By ORing input signal B4 and time limit circuit TM3. Bounce canceled signal B6 from OR gate 13? 4) It will be done. At the fall of this signal B6, the time limit circuit TM
5 operates, and the time limit circuit TM5 operates when 1. A pulse B7 having a pulse width W5 of 1 is generated. In other words, the time limit circuit Tλ15 and fB2B2 are set to shorten the detection pulse detection time. Time limit circuit T
The output of M5 and the output inverted signal of time limit circuit T M4 and the second
The time limit circuit 1'MO is operated by the output of the AND gate 8a which combines ANII with the detection pulse. Time limit circuit TM (l
j,) A time is set to detect sound that the relationship between the phase of the output of the coil L2 of the lance T and the phase of the AC power supply voltage vo is reversed.
Pulse B8 shown in figure (8)? /Occur. Time limit circuit T
The output of R411 is sent to the time limit circuit TM1. AND'? with the OR output inverted signal of TM2? The AND gate 13a that was taken caused a delay of one hour. ! This results in pulse B9 shown in FIG. 8 (9). AN between this pulse B9 and the inverted signal of signal B6
f'L given to delay circuit DY2 by D, delay circuit DY
2 is delayed by time 1'fli t 2 and is
Pulse B shown in 7] 5? Send 〇1mtl at this delay
+t2 OFF operation time of relay switch a2 jOFF? so that relay switch a2 is turned off when diode D is conductive +7 Thoughts IA (, then relay switch a2
This is the timing v4 adjustment time for generating all the off-spinning signals. The output of the delay circuit DY2 operates the timer gate vFTM1, and the fall of the output of the timer circuit TMI causes the timer gate [jJ path T
M2 operates, each pulse width W1. Pulses BIO and Bl l' in W2 are generated. OR output of time limit circuit Tλ12, output inversion signal of comparator 1, and time limit IFI circuit T
The time limit circuit TM4 is activated by the output of the AND gate 11a, which is ANDed with the pulse generated at the fall of the output of M and 0.
works. OR output of time limit circuit TM1.7M2 and 4
By AND with the inverted signal of No. 4 B6, Fig. 8 (16)
As shown in , the off dispatch signal B1 of relay switch a2
6 is generated from AND gate 39, and relay switch a2
Turn it off. OFF state rrx of relay switch a2,
The low level of the signal shown in Fig. s chain is shown. Time limit circuit T
By ANDing the output of M2 and the inverted signal of signal B6, relay switch a1 is turned off as shown in FIG. 8 (1η).
J signal B17 is generated from AND gate 4]. Turn off relay switch alij. relay switch a1
The off state is indicated by the low level of the signal shown in Figure 8 (l). Relay switch al*a2 is turned off. When the electric power is deenergized, the relationship between the output phase of transformer T and the phase of AC power supply voltage vO is reversed from out-of-phase to in-phase, so
The pulse B13 shown in FIG. 8 (131) is obtained from ANDG) 11a.
Since it is performed only when the M5 output and the time limit circuit TM4 output inversion signal are at high level, the relay off drive signal B1 (>. 9 shows an electric circuit diagram of still another embodiment of the present invention.The complete timing chart 116 in FIG.
I will explain one work session when applying the H1 force of the load. Relay switch a1. ．． When a2 is off, the output of the coil L2 of the transformer T is in phase with the AC power supply voltage VO shown in FIG.
, D2 to the comparator l via a clamp circuit. The input signal of the comparator 1 is the signal shown in FIG. 1g41 (2). Transformer T whose waveform is shaped into a rectangular wave by comparator 1
The output of coil L2 is. NOTOR gate 3 that generates a pulse at the rise of a square wave
4 and an AND gate 3b, the pulses shown in Fig. 1 and 10 (31) are synchronized with the point 07 at which the phase of the AC power supply voltage VO changes from negative to positive. The pulse shown in 3) will be referred to as the first detection pulse.In such a state, when the input signal q4 applied to the input terminal Si changes from low level to high level, the input signal q4 becomes A N l ) A noise cut circuit including a gate 8 and an OR gate 9, and a time-limited circuit 1i, -Il that performs bounce cancellation 1.
? , (through 3w, and further through a circuit system consisting of a NOT gate 14 and an AND gate 15, which generate pulses at the rise of the rectangular wave, is applied to the time limit circuit TM4. Pulse width W shown in (5)
Pulse q5 with 4? Send r'. Its pulse width W
4 is - relay drive! It is provided to obtain a pulse signal for generating the ll11 signal, and is one cycle of the AC power supply 1d voltage vO. Time limit circuit T M 4 and time limit circuit T
MI, TM2 OR? The inverted signal (at this time) of the output of the gate 34 (in this case) lB1 detection pulse is AND' (r taken, AND gate) 11b is given to the time limit circuit T M (l) The output Iri of the OR gate 34 is the pulse q12 shown in FIG. 10 (1), and the output of the OR gate 13b is the pulse q6 shown in FIG.
In order to generate a relay-on drive signal so that the relay is turned on when the relay is in the cut-off state, the time t1 is set to match the timing after considering the relay's on-driving time σ11.1.
The pulse q shown in Figure (7) of 9iS10 has a pulse width of
7? Occur. The output of the time limit circuit TMO is a NOTOR gate 13b which generates a pulse at the falling edge of a rectangular wave.
A circuit arrangement consisting of a gate 16b and a time limit circuit TM
], ANII with the OR output inverted signal of the output of TM2, AND'e with the (lance-cancelled input signal)
By taking the power applied to the time limit circuit TMI. Limited time 1
1'6T M I H, after the ON drive signal of relay switch a1 is generated, relay switch a2? Diode D
Relay switch a to be turned on when the continuity status of
The timing for generating the on-drive signal tube of 2 and the pulse width Wll17) shown in Figure 10 (10) for 4 adjustment.
Pulse cL, 10'i is generated. NOTOR generates a pulse tube at the rising edge of the square wave to the output Vi of the time-limited time mTMt
The entire circuit consisting of gate 34 and NOR gate 33 is applied to time limit circuit TM2. The time limit circuit TM2 is set to allow the relay coil current to flow only during the relay operation time.The pulse q has a pulse width W2 shown in FIG. 10 (11).
], 1? Occur. The OR output of the time limit circuits TMI and TM2 is ANDed with the bounce-cancelled h4r input signal q4? ON drive signal q1 of relay switch a1 is applied to AND gate 40.
It becomes 3. The output of the time limit circuit TN12 is ANDed with the bounce-cancelled input signal q4? The ON drive signal q14 of the relay switch a2 is turned on by the AND gate 38.
becomes. The relay coil is on! l1Il signal q1
3. Excitation current flows only when q14 is at high level, and turns on when relay switch a1 and diode D are cut off, and turns on when relay switch a2 and tf diode l) are open, making it possible to energize the magnet without arcing. can. to the trigger terminal T of the D flip-flop F1. Of the first detection pulse and a pulse delayed by the time t1 from the first detection pulse, the pulse shown in FIG. 10, which is obtained only when the switching state of the relay changes, is given. Since the phase of the output of the coil 2 of the transformer T is reversed when the current is detected and when the voltage is detected, the phase is also reversed when the switching state of the relay changes. The detection pulse generated at this time is AND'ed by the pulse delayed by the time t and the inverted signal of the output of comparator 1.
ND output is obtained. In other words, the output of the gate 17b can be obtained only when the switching state of the relay changes. .The output of the AND gate 17b is shown in FIG.
The input terminal of the OD flip-flop F1, which is the pulse q18 shown in FIG. TM2 OR
The output of the output and the output of the inverting output terminal Q of the D flip-flop F1 is connected to the output of the AND' (AND game with i") 22b, so that the output of the output terminal Q of the D flip-flop F1 is connected to the time limit circuit TR11. , TM2 is at a low level unless the output terminal Q of the D flip-flop Fl operates.
Changes from low level to high level. The output of the output terminal Q of the D flip-flop F1 is a pulse q20 shown in FIG. The output of the D flip-flop Fl is applied to the trigger terminal T of the D flip-flop F2 through a circuit r consisting of a NOT gate 24 and an AND gate 25b, which generate a pulse at the rise of a rectangular wave. The output of the AND gate 25b is the signal D shown in FIG.
Trigger terminal TI of flip-flop F2 is broken. Furthermore, similarly to the p flip-flop F1, the pulse q8 from the ANr) gate 7b can also be input. For input L'AA of D flip-flop F2. Output of D-flip 70 tube F1 and D-flip-flop F
The output of the AND gate 26b obtained by taking ANII with the inverted output of 2 is not given. From the output terminal Q of the D flip-flop F2, a pulse q22 shown in the lower part of FIG. 10 is sent out. AND game) AND of the output of the 5b D flip-flop Fl, the output of the D flip-flop F2, the output of the comparator 1, and the first detection pulse delayed by the time t1? Take. The output of the AND game 5b is the signal shown in FIG. The time limit circuit TM4 is activated again by the output of the AND gate 5b. However, when the relay switches a1 and a2 are turned on, no signal is obtained from the AND gate 5b, so the time limit circuit TM4 does not operate. The on state of the relay switch a1 is the high level of the signal shown in FIG. 1110 (151), and the on state of the relay switch a2 is the high level of the signal shown in FIG.
(This is the high level of the signal shown at +. Since the time limit circuit TM4 is set to the time required to detect the first detection pulse, the fact that the time limit circuit TM4 does not operate means that the ON drive signal q13 is higher than the first detection pulse. .q14 will not occur.Therefore, once the power energization is completed, the on-excitation current will not be applied to the relay coil again.In addition, in Fig. 10, the signal γ) shown in Fig. The load current is shown below. Next, the operation when power is turned off under load will be explained with reference to the timing chart shown in FIG. ILII. relay switch al,
When a2 is on, the output of the coil L2 of the transformer T is out of phase with the AC power supply voltage vO. A signal shown in FIG. 11(2) is applied to the comparator l. The output of the coil L2 of the transformer T is processed in the same way as when power is energized. AND game): (Occurs from b. From M,
The pulse 'r shown in Figure 31 will be called the detection pulse. When the input signal g4 changes from high level to low level in this state !l!-, the time limit r + s 7 at its fall.
M3 operates, and a pulse g5 of a pulse width W3 having a time for bounce cancellation by the time limit circuit TM3 is generated. 0 between the output of the time limit circuit Tλ13 and the input signal g4
By OR gate 13 which took 11. The bounce-cancelled input signal g6 shown in FIG. 6 is obtained t14. At the fall of this input signal g6, time limit circuit TM4 operates, and time limit circuit TM4 is the second detection pulse? A pulse g7 having a pulse width W4 having a time required for detection is generated. Time limit circuit T1114
AND gate 1 with the output of time limit circuit TMI, TM2's OK output inversion (AND?r with the second detection pulse of No. 3)
1b causes the time limit circuit TM to operate, and the time limit circuit TMO detects that the relationship between the phase of the output of the coil L2 of the transformer T and the phase of the AC power supply voltage vO is reversed (in this case, the relationship changes from reverse phase to positive phase). The OR gate 13b generates the pulse shown in Figure 9R11 (9R11) with a pulse width of time t1 to detect the sound.
Send the pulse system shown in 8). A circuit consisting of a time limit (the output of the fil path TMO is a NOT game in which a pulse is generated at the falling edge of a rectangular wave) 15b and a NOR gate 16b? As a result, the pulse is delayed by the second detection pulse meeting time [1]. This pulse and time limit circuit TMI. ANI) with the OR output inverted signal of T1142?
r- taken AN I) by the AND output of the pulse glO obtained by the gate 18b and the inverted signal of the input signal g6. Delay circuit DY2 operates, delay circuit DY2 pulse gl
OV is further delayed by time t2. Delay circuit DY2#
-j, second #-j, sends out a pulse gll shown in l. Here, the time tl+t2 is set to generate an off drive signal g21' for the relay switch a2, which is turned off when the relay switch a2 is broken in the conductive state of the diode D.
This is the timing adjustment time taking into account the off-operation time tOFF'% of relay switch a2.D flimp flop 1) The output of Y2 is the time limit circuit TMI''? Further, when the output of the time limit circuit TMI falls, the time limit circuit TM2 generates a full pulse with a pulse width W] and W2. Is the time limit circuit TMI ?11 Pulse g12 shown in Figure 04? The sending and timing circuit T Iil 2 outputs the pulse g1 shown in FIG.
3% - Send. The OFF drive signal g21 of the relay switch a2 is obtained by ANDing the OR outputs of the time limit circuits TMI and TM2 and the inverted signal of the input signal g6. This off jljA! 11II signal g2] is sent out from the AND gate 39. By ANDing the output of the time limit circuit TM2 and the inverted signal of the input signal g6, the relay switch a1 is turned off 1.
A 2 uJ signal g22 is obtained. This off drive signal g
22 is sent out from the AND gate 41. A current flows through the relay coil only when the off drive signal is at a high level, and the relay switch a2 turns off when the diode D is turned on, and the relay switch a1 turns off when the diode D is turned off. D flip flon 1Fl,
Since it operates in the same way as when F2 is energized, the time limit circuit TM
When the off-operation time of the four-way race switch 11 and a2 was 0, the second detection pulse caused the off-drive signal g2, g22 to be generated, and the relay switch al. a2? Kakeru! No current flows through the relay coil that causes vI. This allows the power consumption of the relay coil to be kept low. FIG. 12 is an electrical circuit diagram of a relay drive circuit in which the output terminals SMN, SMF, SSN, and 5SFI in FIGS. 3, 6, and 9 are each connected to f1. line 1
5() is given the tun source pressure Vcc. Line l!
50trF, resistor R51 ox to the base of transistor Tr51 via resistor R52. Resistor R53? to the collector of transistor 'l' r51 through resistor R53 and resistor R54? The transistor Tr52 is connected to the base of the transistor Tr52 and the emitter of the transistor Tr52 through the transistor Tr52. Also line 150tt,
r, transistor Tr54 is connected to the emitter of transistor '1' r54 via resistor R57 and resistor R56.
The transistor T'56
Add resistor R59 to the collector of ↓resistor R5g'! i-
The supernatant is connected to the base of the transistor Tr56 through the supernatant. The collector of the transistor Tr52 is the cathode of the Zener diode D51, and the -! of the relay coil A2. ;L
and connected to the collector of transistor T r 53. The collector of the transistor Tr54 is the cathode of the Zener diode D52, and the other end of the relay coil A2. and is connected to the collector of transistor Tr55. The anode of the Zener diode D5 is connected to the anode of the Zener diode D52. Transistor T r 51 * T r 53 * T
r55*Each emitter of Tr56 is grounded. The terminal S M N is. Resistor R52? Mt is connected to the base of the transistor Tr51 through the resistor R57? It is connected to the base of the transistor Tr55 through the transistor Tr55. The terminal SMF is. Resistor R55? Connected to the base of transistor T r 53 through resistor R5B? The power supply voltage Vcc is applied to the line 160 which is connected to the base of the transistor Tr56 through the line 160.The line 160 is connected to the base of the transistor Tr61 through the resistor R61 and R62? To the collector of Tr61. Transistor T via resistor R63 and resistor R64'
H is connected to the base of r62 and the emitter of transistor Tr62, respectively. Also, on line /60, resistor R67 and resistor R66 are connected to the emitter of transistor Tr64.
A resistor R67 is connected to the base of the transistor Tr64 via
A resistor R6 is connected to the collector of the transistor Tr66 through the
9 and the base of the transistor Tr66 via a resistor R68k. The collector of the transistor Tr62 is the cathode of the Zener diode D61. One end of relay coil A1 and transistor Tr63
Connected to the collector of h=. 6. The collector of the transistor Tr64 is connected to the cathode of the Zener diode D62, the other end of the relay coil A1, and the collector of the transistor Tr65. ;, 4 g nru. Zener diode D
The anode of 61 is connected to the anode of Zener diode D62. Transistor Tr61. Tr63. Tr
65. Each emitter of Tr66 is grounded. Terminal SMN
is connected to the base of the transistor Tr61 via a resistor R62, and is connected to the base of the transistor T'6 via a resistor R67'.
Connected to the base of 5. The terminal S M F iu is S-connected to the base of the transistor Tr63 via the resistor R65, and connected to the base of the transistor Tr66 via the resistor R6B'. The entire operation of this circuit will be explained below. The signal applied to the terminal SMN is applied to the connection point between the resistors R51 and R52 and to one end of the resistor R57. As a result, the transistor Tr51 is turned on, and then the transistor Tr52 is turned on. Further, the signal applied to the terminal SMN turns on the transistor Tr55. Therefore, relay coil A2
for. Relay switch a2 shown in FIG. Coil current flows in the direction of turning on. Next, the signal applied to the terminal SMF is applied to the base of the transistor Tr53 via the resistor R55, turning on the transistor Tr53i. Also, the signal given to the terminal SMF is the resistor R58? I- is applied to the base of the transistor Tr56 via. When the transistor Tr56 is turned on, the transistor Tr54 is also turned on. Transistor Tr53. When Tr54 and Tr56 are turned on, a coil current flows through the relay coil A2 in the direction of driving the relay switch a2' (i-off) aIJ. Next, the signal given to the terminal SSN is passed through the resistor R62? It is applied to the base of the transistor Tr61, turns on the transistor Tr61?r, and then turns on the transistor Tr61?r.
Turn on 62f. Also, the signal f applied to the terminal SSN is applied to the transistor Tr65 via the resistor R67F.
i, transistor Tr65? Turn it on. As a result, the relay coil A1 is turned on. Coil current flows in the direction that turns it on. Next, the signal applied to the terminal SSF is applied to the base of the transistor Tr63 via the resistor R65, t, fl, etc.
Turn on transistor Tr 63Th. Also terminal SSF
The signal given to resistor R68? Through the transformer Tr
66, and the transistor Tr66'? Then, the transistor Tr64Th is turned on. As a result, relay switch a is applied to relay coil A1.
]The coil current flows in the direction that turns off IIIUJG. As described above, the signal applied to the terminal SMN causes a current to flow through the IJ relay coil A2 in the direction of turning on the relay switch a2, and the relay switch a2 is turned on.
Further, in response to the signal applied to the terminal SMF, current flows through the relay coil A2 in the direction of turning off the relay switch a2, turning off the relay switch a2. terminal S
SN to 4. The output signal causes the relay switch
Current flows through relay coil A1 in the direction that causes k to turn on. Relay switch a1 is turned on. In addition, a current flows through the relay coil AI in the direction of turning off the relay switch a1 in response to a signal applied to the terminal 5SFl, and the relay switch a1 is turned off. Effects As described above, according to the present invention, all changes in the on/off state of R1 and the second relay switch are detected. 1st. Since it prevents the re-generation of the relay drive signal that drives the second relay switch, the power consumption of the relay coil?
It can be kept small.

[Brief explanation of drawings]

FIG. 1 is an electric circuit diagram for explaining the basic operation of one embodiment of the present invention, and the fFtZ diagram is a block diagram for explaining the overall t4 configuration of one embodiment of the present invention. 31st ZIVi An electric circuit diagram of an embodiment of the present invention, 4th diagram is a timing chart for explaining the operation of the circuit of FIG. 3 when the Vu power is activated, and FIG. A timing chart for explaining the operation when the power of the load is turned off, FIG. 6 is an electric circuit diagram of another embodiment of the present invention, and FIG. 7 is a diagram of the circuit shown in FIG. 6 when the power of the load is turned on. FIG. 8 is a timing chart for explaining the operation of the circuit shown in FIG. 6 when the power is turned off; FIG. The electrical circuit diagram, R10 diagram, is 11 of the load of the circuit in Figure 9.
Fig. 11 is a timing chart for explaining the operation of the circuit shown in Fig. 19 when the load is on the electric power market.
i Z diagram Fi Figure 3, Figure 6 and Figure 9 terminal S8f
Relays connected to N, SMF, SSN, and SSF (this is an electrical circuit diagram of a pivot circuit. T...transformer, al, A2...relay switch. L...load, EO ...AC power supply, Si...input terminal, D1-D4...diode, D51.D52.I
)61°D62... Zener diode, AI, A2.
...Relay coil 5Tr51 to Tr56. Tr6]~T
r66...Transistor, R1-R5, R51-R5
9゜R61~R69...Resistance, SMN, SMF, SS
N. ssp...terminal, TB4 (1, TMI, 7M2.Th
I4゜7M4, 7M5...Time limit circuit, DY2...Delay circuit. FF, Fl, F2...D flip-flop, 1...
Comparator, 2.5, 7, 10, 11, 14.19.2 (+
, 24. 29. 32. 37. 4a, 6a, 9a
. 12a, 2b, 7b, 9b, 10b, ], 4b, 15
b, 20b, 24b, 28b, 29b...NOT gate, :(,6,8,] 2.15,21,22°2G,
27. 28. 30. 35. 38. 39. 4
0, 41. 37a, 38a, 2al 5a, 8a. 11a, 13a, 3b,' 4b, 5b, llb, 12
b, 17b, 18b, 19b, 21b, 22b. 25L+, 26b...AND gate,
4. ] 6. 25°33, l Oa, 1 6
b-NOR gate, 9, 13° 17, 18.
23. 31. 34. 36. 7a, 8b, 13
b, 23b, 27b...OR gate agent patent attorney
Saikyo Kei Part 125i1 Hand I! Written amendment March 25, 1985 Patent Application No. 59-30770 2. Name of the invention AC switch circuit 3. Relationship with the case of the person making the amendment Applicant's address and name (583) Matsushita Electric Works Co., Ltd. Representative 4, Agent Address 1-chome Nishihonmachi, Nishi-ku, Osaka @ 13-38 Shinko Sangbu Building Country Equipment EX 0525-5985 INTAPT
J International FAX GI[[&GII (06)53B-0
2476, Detailed explanation of the invention in the specification to be amended and Drawing 7, Contents of the amendment (1) On page 7, line 13 of the specification, “Time limit circuit TM
6J is corrected to [time limit circuit TMOJ. (2) Line 14 of page 8 of the specification is corrected as follows. AND with the signal P5 written in ANt) Date 40 shown in FIG. 4 (14).
1 Correct. 1AN of the OR output of note 2 and the second detection pulse (zero point detection output pulse whose phase changes from positive to negative)
Take D (4) In the first line of page 18 of the specification, select “Output A11
” should be corrected to “Output A12.” Correct the statement to "number of applications." (6) At the beginning of the third line on page 25 of the specification, the phrase "only time" should be corrected to "F time t1 only." ()) In the 9th line of page 25 of the specification, the word "pulse" is corrected to "first detection pulse." (8) At the beginning of page 27, line 19 of the specification tA, “10th!
1 (19) J [Corrected to Figure 10 (18) J V
Ru. (9) In the 5th line of Meisho S NS29x, it says [NOT date] 24J, and in “rNOT date 24b” i
1 Correct. 10) In the specification @ page 29, line 7 to NS line 8, r
A N D date... it is a signal. ” Please delete the text. 11) The 12th line of page 29 of Book #1 should be changed as follows:
Correct. This is the signal shown in FIG. 10 (21). For the input terminal of the lip 70 knob F2, there is a 70 knob DY2.
"J" should be corrected to "Delay circuit DY2J. (13) Line 7 of page #33 of the specification is corrected as follows. At the falling edge of
” [Corrected to terminal 5SNJ.] (15) On page 37, line 9 of the specification, “Terminal SMF
" is corrected to "terminal 5SFJ. (16) Figures 2, 7, and 9 of the drawings are corrected as shown in the attached sheet. That's all for Figure 2.

Claims (1)

[Claims] Two FF1L, second relay switches inserted in a series circuit of an AC power source and a load and connected in parallel to each other for switching the load, the first relay switch being When diodes are connected in series and a relay switch is turned on ωJ, the first relay switch is turned on when the voltage waveform of the AC power source is in the opposite direction of the diode, and the second relay switch is turned on by the power. The second relay switch is turned on during the half period in the II direction, and the relay switch is turned off in the half period in the forward direction of the diode. In an AC switch circuit that turns off at regular intervals. The transformer for detecting the phase of the AC power source includes a first and a second transformer.
The relay switch of 9B1. Detects the current of the AC power source when the second glue switch is in the on state. The phase of the transformer output during voltage detection and the transformer output during current detection are inverted, and one of the transformer outputs is in phase with the AC power supply, and the other is in reverse phase with the AC power supply, and the change from voltage detection to current detection is detected. 1st by detecting. ! 2
By detecting the change of the relay switch from the OFF state to the OFF state, and by detecting the change from current detection to voltage detection, by detecting the change from the ON state to the OFF state of the 1st relay switch. , ill, $2
An alternating current switch circuit characterized by stopping the supply of power to each relay coil driven by a relay switch.