JPS61296625A - Three-phase ac switching circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] Technical Field The present invention relates to a three-phase AC switch circuit.
, I'm going to use a relay switch to set up a zero clock U.S. switch circuit). Technology ゛, phase 9 circuit switch and 1. Then, electromagnetic switch (NGMU゛ptoS i/-), solid state relay (SS1
'() etc. are used. This 11. Among RRM switches, electromagnetic switches have a low conduction resistance (ON resistance), generate heat when energized, and have a low temperature range, so they can be miniaturized and are the only solid state relay. FM: Although it has the advantage of having a long life as it has no mechanical contacts, the electromagnetic switch has short lifespan due to damage to the contacts due to the occurrence of arcs when opening and opening, and also has a short lifespan. Sude Tori!
- Is the conduction resistance (ON fold) large 1? 'Heat generation when energized.・Mef7') It required a large heat sink,9 and it was difficult to miniaturize, which had the following disadvantages. Therefore, the conduction resistance when energized is low, the heat generation is low, the life is long, and the compact 7
A magnetic switch was desired.

Purpose This invention...7 Purpose 1. t, 1- Solve the technical problems mentioned above, take the advantages of the conventional electromagnetic switch and solid input switch, compensate for the drawbacks of the conventional electromagnetic switch, and make up for the shortcomings of the L-h-
Our goal is to provide a compact, long-life, two-current switch circuit.

Embodiment FIG. 1 is an electrical circuit diagram "C" of an embodiment of the present invention. Three-phase AC power supply A, 9 phases of C, B, C, and 8 phases IJ.
11. Mi-phase AC power switch/Circuit 1 electric pick-up-F
al.

Each phase load ZatZbt Ze is connected to the diaphragm terminals a2, h2, and e2 after the load, respectively. There is. End 'j' ai, a21'ij has relay switch sw+1, which is 1-1, 1-1, 1) between 1) and 1, resistor R1 and 1, and T pressure is zero for j person detection. Tobuns P
1 large gAI''2 of T is connected in series with 141., I to terminal b 1, t+2 ii1!
:l-= Riss・f border 9m2) 7, This is!・=−nu, i)・Diode 1 in parallel with Qi 2
) 111/end 111 to end j゛1, (:i'': forward connection in the direction, 11, above λ - switch sw
2 and the contact block/ra terminal b 2 on the can side of the diode D1, it passes through the detection circuit L3 of the first redundant cooling, i-lance CTI for detecting lance CTI.

I'm here.

ell -r-e i, e 2 open, relay switch sw3 is interposed l, terminal c1 and one terminal of said relay switch sw3 to which connection point 151, one power terminal of relay switch sw4 and resistor R2. - terminal is connected to tongue 1, and the other terminal of relay switch 7fsw4 is connected to the cand of diode D2.
The other terminal of the relay switch sw3 marked with # is connected to the 7th/- wire of 2, and from this connection point to the terminal c2, the ring wire of the second current zero cross detection transformer CT2 is connected to the ring wire of the second current zero cross detection transformer CT2. ．． ``r: 8 The above zero clock l':l is connected to 1' of the detection transformer CT2, and one of the coils L4 is -
・One terminal IJ:, AND of diode D2 @1.
The secondary coil 142 of the detection transformer PT, which is connected to the other terminal of the terminal 1 and the other terminal of the resistor R2, is connected to the comparison input terminal (■-゛i,
The detection coil 143 of the detection transformer C″r1 is connected to the comparison input terminal −P3.P of the control circuit 3.
4, and the secondary coil 1 of the detection transformer CT' 2.
The relays RS 1-R84 correspond to the relays 1/-switches swl to sw4, which are also connected to the comparison input terminals P5 and P6. Connecting terminal P7 for each month
．． P8, P9. PIO, Pli, PI3, and U'P1
3° Connected to PI3 in this order #'1. '1r+-ro,
7 control circuit; (A power supply voltage 10Vec is connected to the terminal P15 of the circuit, and a resistor R is connected between 1r and P15.
3>5'! =, between fP 16 and P 1.7 [
:l: let: ON / OF F X I'!
fsW is connected to C1, and end 'PPI'/ is floating to ground If1. , :, A'1r- Therefore, the switch SW is open (
When it is off (OFF), the end fP i 61j:rH] is set, and when it is off (ON),
End-fP1G is II2 Lebel-1, Fig. 2 is,
Circuit diagram of the control circuit (1:").The first comparison circuit (21
Comparison input terminal P h t P 2 if, previously mentioned υ) Voltage zero cross r7 Secondary side l of voltage zero cross detection transformer P T
2 is connected, and the second comparison circuit/(comparison input J of 2) terminal P
3. P4 is the detection circuit of the first current zero cross detection transformer CTi! -, 3 are connected % tt, the third comparison circuit C3 is connected to the comparison input terminal f P , "1. The secondary coil L5 of the second current zero cross detection transformer CT2 described above is connected to P6. 1st comparison circuit C1
The output terminal of is connected to one input terminal of ANDday)Gl, and the other input terminal of ANDday)Gl is connected to NOT
The output terminal of the NOTOR gate G36 is connected to one input terminal of the AND gate G2.

Also, the output terminal of the second comparison circuit @C2 is the NOT day)
Connected to the input terminal of G21. Third comparison circuit C3
The output terminals of the first differentiating circuit Q1 and the second differentiating circuit Q
2 input terminals, respectively. Also, the AN
D day) Gl and G2 output terminals are OR day)
connected to each input terminal of G3 individually, OR data) G3
The output terminals of the third differentiating circuit Q3 and the fourth differentiating circuit Q
4 input terminals, respectively.

The power supply voltage +Vce is connected to the terminal P15, and the terminal P15 is connected to the power supply voltage +Vce.
15. A resistor R3 is connected between terminal P16 and
, terminal PI3, an ON10 FF switch S field is connected, and terminal P17 is grounded. *Terminal P1
6 is connected to the input terminal of the input inter 7 ace C4, and the input inter 7 ace C4 outputs an output corresponding to the switching mode of the switch SW to the line J? 1. line! 1 is an input terminal of the first delay circuit DLI;
NOT day) G42 input terminal and V3 manual AND day) G5. G7. It is connected to each first input terminal of GIO and Gl 1 . The output of the first delay circuit DLI is the input terminal of NOT gate G41, AND date G15, and NOR date G1.
6, is connected to one input terminal of each of the OR date G18 and the AND gate G19. NOTOR
The output terminal of the gate G36 is connected to the input terminal of the second delay circuit DL2 and one input terminal of the rEX-OR gate G36, and the output terminal of the second delay circuit DL2 is connected to the input terminal of the third delay circuit DL3. and one input terminal of AND date G12, NOTOR gate G36 terminal, one input terminal of AND date G17, AND NO date i5,
NOR data) are commonly connected to each input terminal of G16. The output terminal of the third delay circuit DL3 is connected to the fourth delay circuit DL3.
Input terminal of delay circuit DL4 and the NOR date G1
8, AND Day) Each other input layer of Gl 9! BiN
OT? -G22, one input terminal of AND5/-G14, and one input terminal of the AND gate G2. The NOTOR gate G36 output terminal is connected to the other input terminal of AND date G12.

The output terminal of the fourth delay circuit DL4 is the other input terminal of the EX-OR gate) G136 and the NOT gate) Gl.
35 input terminals are connected to one input terminal of AND date G137, respectively.

The output terminal of T date G135 is connected to the other input terminal of AND date G17. NOT? -)G42
The output terminal of 3-man power AND gate G4. G6. It is commonly connected to each second input terminal of G8 and GIO.

The output terminal of the EX-OR date 6136 is 3-man power A.
ND date G4゜G5. G6. G7. G8. G9. Gl
It is commonly connected to each input terminal of O and G11.

The output terminal of the first differentiating circuit Q1 is an AND date G2.
5. Connected to each second human power terminal of AND date G26,
The output terminal of the second differentiator circuit Q2 is the 3-person AND date G
23. It is connected to each second input terminal of G24. In addition, the output terminal of the third differentiating circuit Q3 is the 3-person AND date G
27. G28. G2
9 are connected to each of the second input terminals. AND gate G
The output terminal of 12 is connected to the third terminal of the 3-power AND gate G20, and the output terminal of the AND gate G14 is
It is connected to the first input terminal of the three-person AND date 628. The output terminal of NOT day) G13 is connected to the other input terminal of said AND day) Gl 4, and is further connected to the AN
It is connected to the other input terminals of the D dates G13, G30, etc. AND date) Gl 5's output terminal is connected to the first input terminal of 3-person AND date G23, AND
The output terminal of date G17 is 3-man power AND day) G26
N.

T day 1-G i 6 output terminal 1i, 3 manual AND
The second input terminal 1'' of date G17 is connected.N
OI Kuday) G i, 8 output terminals 1 soil, 3 human power A
3rd input terminal 1. Second contact/kasa jll, A N F) "7' -1-G 1
Output of 9, fj terminal 1. 3 people ty A N mouth'f-)
The first input end of G25 (: Connection tongue 6.3
ANDA) Output IJ terminals t9 and 3 of Note G 27,
,,% power AND gate G23 output terminal (Y, NOR
'i' - Individually connected to each input 21 terminal E of G31 7
1.3 human power AND gate (output terminal of stone 29) and 25 output IJ terminal for 3 human power AND date
f-) is individually connected to each input terminal -r- of G32, and 3
The output terminal of G2)3 is N OR
The input terminal l of G33, the two individual 1"" connected Jll, the output terminal of G30 and the output terminal f- of G26 are: It is individually connected to each input terminal of the JOR game board 34.

The output terminal of G3t (NOR day) is connected to the input ζ of the first mat circuit F'1 (NOR day).
D) Output terminal 1 of G31A, $2 one-shot circuit F
2 input jll -f <, ″: Connect, N OR?
-=) The output terminal of G33 is connected to the third one-shot circuit T'3L>) Jl terminal, and the NOR data)
The output terminal of G34 is connected to the input terminal r of the fourth one-shot circuit F4. It's completely connected. The output terminal of the first three-three circuit F1 is an AND data ()G4.
O's/I'j input terminal Upper 13 manual ANDJf-)0
25 and G29 input terminal 1: Connected. , the output terminal of the second wire/shot circuit F2 is NOT'
?・G36=G37 and 3-person AND date G
! '; The output terminals of the first and third one-way circuits F3 connected to the input terminal of HG9 are AND data (λ
35) and one input terminal of 3-man power ANDAf・-1
,G3Q.

are connected to each of the 26 input terminals, and the output terminal of the fourth one-seat circuit F4 is NOT'〆・−1・(member 3j)9
(Even if connected to the input terminal of i38, 1.-゛, 3
A', F7AND date G6. Each input terminal f of Gl 1
– is connected to. The output υ end r-If of the NOT date G38, the other input terminal of the AND Y-to G39.
:connection;! 〆11, A N D 'f) G 39
i7) Output terminal -j' let, 3-man power AND de-
・)G7. Connections are made to the 8 input terminals of GIO. Also, the other input terminal of G 40 is connected to the N
OT day) G3 '7's output terminal 1゜2 is connected,
AND''~G40 output terminal is 3-person AND data.
)G4. Connect to each input terminal of G9.1. ing.

Said NOT de...1, et al: (The output terminal of 5 is the 3-person power ANDY-) Input terminal 1 of G24.9 and G28
This is connected to the output terminal 1 of the NOT gate G36, and the 3-man power AND? ”-) G23 o1, ti G27
(7) Input terminal - D connection 1. I'm here.

The set input terminal T-S1 of 1 to the first read drive circuit is 3
Connected to the output terminal of human power A N D DE) G4,
Reset input terminal completion key 1 is a three-man power A N D operation.
) Connect the output terminal F1 of GSA to il-. 2nd relay/drive circuit I/(?'s +!7 input terminal S2
is connected to the output terminal of the 3-man power AND date G7, and the reset input is connected to the output terminal of the 3-man power AND date G7. 1-
One drive circuit has 03's driver, '7j and Sei i'shi:,
1li1.1'(su, force, \NI',')', 1'-・
l.(-8 is connected to the output terminal 4, and the reset input terminal I.3 is the 3-man power ANDAf-) G9 output terminal 1.゛It is connected. The set input terminal S4 of 4 in the fourth relay drive circuit is connected to the output terminal of 3 human power AND5/-) G10, and the relay human power terminal r4 is connected to the output terminal of 2 (man7, !AND-r'=) G11. Connect to the output terminal 1, and connect each month of 1- and K4 to the relay drive circuit, j7 end P7. P8, P9. P 10,
Pll, PI3, [)13, and PI3 are connected to the coils of Harire relay -RS i l- (S4), and the set input terminal of each relay drive circuit is set to "1,". , the corresponding relay switch is activated, and each reset manual E'l';

Figure 3 is a waveform diagram of each part of the general policy in Figure 1.
), Figure 4 is the timing chart 1"c" of the control circuit!・
H11, B1 Figure 1 and Figure 2 and Figure 3 and Figure 4 are paired with Black 1.
,),) Hereinafter, the positive phase AC switch f゛ times 1!1 of an embodiment of the present invention will be described. The operation will be explained. 'E, when the wattmeter 5 is input to the phase load Z, the time T 01 shown in FIG. 41 (1) is reached.
: ! ; I"C said ON,'OF F switch S
W h'close chive 11 1. ', the terminal pi 6 changes from the rHJ level to the rLJ level, and this level change of H-IL is transmitted as an ON signal shown in FIG. 4 (1) to the line ! 1 is derived and this ON
The signal is given to the input terminal of the first delay circuit DLI, and the first delay circuit DL1 converts the bounce waveform at the time of opening and closing of the ON10 FF switch S field into a delay time t with TO as a reference.
1, and the time T1 shown in FIG. 4 (2)
A signal A with a level change H−nL is derived at NOT
The data is inverted by the EX-OR data G41 and applied to the input terminal of the second delay circuit DL2 and one input terminal of the EX-OR data G36. In Fig. 1, the primary coil L1 of the voltage zero cross detection transformer PT is connected to terminals al and bl, and its secondary coil L2 is connected to the terminals al and bl, as shown in Fig. 3 (2
) is derived, and the waveform is applied to the first human comparison circuit C1 via the terminal p1y92. As a result, a voltage Eab zero-crossing detection signal is derived from the output terminal of the comparator circuit C1, at which the level changes from H to L at the zero-crossing point when the voltage Eab changes from positive to negative.

Further, in FIG. 1, the detection coil L3 of the b-phase current IC zero-cross detection transformer CTI is connected between terminals p3 and 14, and after power is applied to the three-phase load Z, the inside of the conductor passing through the coil L3 is connected. Flowing b shown in Figure 3 (7)
The waveform of the phase current Ib is detected and applied to the second manual comparator circuit C2, and the output terminal of the comparator circuit C2 receives a level change from H to L at the zero cross point when the current Ib changes from positive to negative. At the zero-crossing point when the current changes from negative to positive, a current Ib at the rise of the level change L-4H and a zero-crossing detection signal are derived.

Furthermore, in Fig. 1, the primary coil L4 wound around the ring core K of the C-phase voltage/current zero-cross detection transformer PCT is connected between both poles of the relay switch sw4 of the relay R84, and the C-phase current is connected to the ring core. The conductor passes through 2
The next coil L5 is connected to the input terminal of the third human power comparison circuit C3 via terminals p5 and p6. The secondary coil L5 is ON10 F F The waveform of the C phase voltage Vc is detected at the time when the F F switch S field is closed and the relay switch swl of the relay R31 is cut off, and then the relay switch sw3 is conductive and the C phase voltage Vc is detected. When the load current Ie flows through the ring core, the waveform of the C-phase current Ic is detected, and these detected waveforms are applied to the output terminal of the third human power comparison circuit C3.
Zero-crossing detection signal Ic is derived as a zero-crossing detection signal.

When the second delay circuit DL2 is energized, the aforementioned relay R3I
In order to obtain the Eab zero cross detection signal for making the relay switch swl conductive when the diode D1 shown in the first diagram is cut off, and when the power is turned off as described later, the relay R33 is
It is provided to obtain an Ic zero cross detection signal for cutting off the relay switch sw3 when the diode D2 shown in the first diagram is conductive, and is set at a preset time t2 (t2=π, where π= 180 degrees) Figure 4 (
3) is led out to the input terminal of the delay circuit DL3 in FIG.

The third delay circuit DL3 is connected to the aforementioned relay R82 when power is applied.
When the diode-01 of the 1M line is connected, the relay switch S change 4 of the relay R34 is connected to the diode D2.
The relay R84
It is provided to obtain the tb zero-cross detection signal for cutting off the relay switch sw4 of the relay R82 when the diode D2 is cut off, and cutting off the relay switch sw2 of the relay R82 when the diode D1 is turned on, and is set in advance from the rising edge of the signal B. The signal C shown in FIG. 4 (4) delayed by the time t3 (t3≧2π) is delivered to the terminal of the fourth delay circuit DL4.

The fourth delay circuit DL4 is used to obtain the Vc zero cross detection signal for making the relay switch sw3 of the relay R33 conductive when the diode D2 is conductive when the power is turned on, and to turn on the relay switch swl of the relay R8I when the power is turned off, which will be described later. It is provided to obtain the Ib zero cross detection signal to be cut off when the diode D1 is cut off, and is set at a preset time t4 (t4≧2π) from the rise of the signal.
) delayed signal I (shown in FIG. 4 (13)) is
OR data) is derived from the other input terminal of G36.

Signal A! Eab zero crossing point from negative to positive voltage Eab obtained first after the level change to H-+L, that is, at time T2 in FIG. 3(2)
The first one-shot circuit F1 operates and derives a signal having a preset time width t5 (t5≧K) shown at time T2 in FIG. 4(5).

E
The ab zero cross detection signal falls, which causes the one-shot circuit F2 in FIG. 2 to operate, and at time T4 in FIG. 4 (6).
A signal E having a preset time width t6 (t6≧2π) shown in is derived.

The Vc zero-crossing detection signal rises at the zero-crossing point of the C-phase voltage Ve obtained during the period of the signal E from negative to positive, that is, at time T5 in FIG. , t7 (t7≧21r) during the preset time shown at time T5 in FIG. 4(9)
) is derived.

The Vc zero-crossing detection signal falls at the positive-to-negative zero-crossing point of the C-phase voltage Vc obtained during the period of the signal F, that is, at time T7 in FIG. 3 (5), and thereby the fourth one-shot circuit F4 operates. , time T in Fig. 4 (10)
A signal G having a preset time width t8 (t8≧operating time of the relay switch) shown in FIG.

AND output of the inverted signal of signal RI and signal E, and line! 2
The inverse output of the ON signal obtained via When driven, the relay switch swl shown in the first diagram becomes conductive as shown in FIG. 4 (7).

The signal G, the inverted output of the ON signal obtained via line No. 2, and the output of EX-OR date 036 obtained via line e3 are given to each input of G6, and the fourth The set signal S2S shown in FIG. 4 (15) is derived, the relay R32 is driven, and the relay switch sw2 shown in the first diagram is derived as shown in FIG. 4 (8).

AND output of signal F and the inverted output of signal E, and! 2 and the inverted output of the ON signal obtained through line J! The output of EX-OR data (G36) obtained through EX-OR data (3) is given to each input of G8
) is derived, the relay R34 is driven, and the relay switch sw4 shown in FIG.
Conductivity occurs as shown in 1).

Signal E, the reverse output of the ON signal obtained via Line No. 2, and Line! The output of EX-OR date G36 obtained through 3 is given to each input terminal of G8, and a set signal S3S shown in FIG. The illustrated relay switch sw3 conducts as shown in FIG. 4 (12).

Relay R8I is first driven by the above-mentioned signals to make relay switch swl conductive, then relay race switch sw2 is made conductive, then relay R84 is cut off when diode D2 is cut off, and relay switch sw4 is made conductive. Relay R33 is driven when diode D2 is conductive, and relay switch 5tU3 is conductive.

Through the series of operations described above, power energization of a three-phase load using a relay switch is realized at zero cross.

Next, when the power is turned off, when the ON10 FF switch S field is opened, the terminal +116 changes from [LJ level to rHJ
This level change L-H is caused by the delay circuit DL.
Time t1 to L4 preset by I to DL4
The output changes accordingly.

First, the level "L" of the ON signal shown at time TIO in FIG. 4(3) is inverted to rHJ. Hereinafter, this signal will be referred to as an OFF signal. The above OFF signal is delayed by a time t1 by the ml delay circuit DLI, and the signal A is inverted at time Tll in FIG. M h M q
The Ic zero-cross detection signal rises at F'71/01 Hetiya T, and this rise activates the first one-shot circuit F1, and at time T12 in FIG. 4 (5). to output the signal again.

At the positive-to-negative zero-cross point of the C-phase current Ic obtained during the signal period, that is, at time T15 in FIG. 3 (7), the Ib zero-cross detection signal rises, and the one-shot circuit F2 in FIG. Time T15 in Figure 4 (6)
A signal E shown as is derived again. The Ib zero-crossing detection signal rises at the zero-crossing point from negative to positive of the b-phase current Ib obtained within the period of this signal E, that is, time T17 of the third e(7), and this rising causes the third one-shot circuit F3 to operate. Then, the signal F shown at time T17 in FIG. 4(9) is derived again.

The fourth one-shot circuit F4 operates at the zero-crossing point from positive to negative of the b-phase current rb obtained during the period of signal F, that is, at time T19 in FIG. 3(7), and the fourth one-shot circuit F4 operates as shown in FIG.
The signal G shown at time T19 is derived again.

The AND output of the signal R and the inverted output of the signal E, the OFF signal, and the output of the EX-OR gate obtained via the line No. 3 are given to each input terminal of the 3-man AND date G9, and as shown in FIG. A reset signal S3R shown as 18) is derived, the relay R83 is restored, and the relay switch sw3 shown in the first figure is cut off as shown in FIG. 4 (12).

Signal E, OFF signal, and line! EX-OR data obtained through 3) The output of G36 is 3-man power AND day)
Given to each input terminal of Gl 1, tlS4 diagram (19)
The reset signal S4R shown in is derived, the relay R84 is restored, and the relay switch sw4 shown in FIG.
) is blocked as shown.

AND output of signal F and inverted output of signal G, OFF signal, and line! EX-OR date G obtained through 3
36 is given to each input of G7, the reset signal S2R shown in FIG. 4 (20) is derived, the relay R82 is restored, and the relay switch sw2 shown in FIG. 8).

Signal G, OFF signal, and EX-OR data obtained through line 3) The output of G36 is 3-man power AND data)
A reset signal SIR is applied to each input terminal of G5 and shown in FIG. 4 (21) is derived, relay R3I is restored, and relay switch su+1 shown in FIG. 1 is cut off as shown in FIG. 4 (7). 6 As described above, reset signals 1 to 4 are formed in the relay drive circuit by each signal, and by giving these reset signals to the reset signal terminal of each relay drive circuit, first the diode D2 shown in the first diagram is Relay switch sw3 is cut off when conductive, then relay switch sw4 is cut off when diode D1 is cut off, and then relay switch 5 is cut off when diode D1 is turned on.
112 is cut off, and finally the relay switch swl is cut off. Through such a series of operations, power dissipation of a three-phase load using a relay switch can be realized at zero crossing.

Effects As described above, according to the present invention, the phase difference between two phases of a three-phase AC circuit is detected, and the relay switch + operation 1! Since the I'I is made to perform zero cross mm, the occurrence of arcing when switching the load is suppressed, there is no damage to the contacts, and low heat generation makes it possible to realize a three-phase AC switch circuit that is compact and has a long life. be able to.

[Brief explanation of the drawing]

FIG. 1 is an electric circuit diagram of the three-phase AC switch circuit 1, FIG. 2 is a circuit diagram of the control circuit, FIG. 3 is a waveform diagram of the three-phase AC switch circuit, and FIG. 4 is a time chart of the control circuit.

Claims (1)

[Scope of Claims] A first switching means, a second switching means, and a third switching means interposed in series in each of the first, second, and third phase lines of a three-phase AC power supply; means for detecting the phase of the current and voltage of each line, which is connected to the load side of the second switching means and the third switching means in the phase and third phase lines; a voltage detection means for detecting the voltage between at least one line; a first control circuit for controlling the opening/closing operation of the first switching means; second and third control circuits that control opening/closing operations, the first switching means includes a first relay switch,
The second switching means includes a second relay switch and a third relay switch, the first diode is connected in series to the third relay switch, and the third switching means includes a third relay switch and a fourth relay switch. and the fourth relay switch includes a second
The diodes are sequentially connected in series, and the second relay switch and the fourth relay switch are controlled to conduct conduction/interruption operations in response to each case of forward current and reverse current regarding the first diode, and A three-phase AC switch characterized in that the third relay switch and the fourth relay switch are controlled to conduct conduction/interruption operations in response to each case of forward current and reverse current with respect to the second diode. circuit.