SU845287A1 - Energy-independent storage cell - Google Patents

Description

one

The invention relates to a pulse technique and can be used in discrete automatics .f devices.

A trigger that stores information during power supply breaks, is implemented on transistors, and is equipped with a magnetic core with a rectangular hysteresis loop (BCP), which contains write and read windings flj.

The disadvantage of the device is that the reading pulse must have sufficiently flat leading and trailing edges, which leads to an increase in the recovery time of the information;

} 1 is known to be a nonvolatile memory cell with BCP transformers, containing non-OR elements, resistors, diodes G.

The disadvantages of this cell are low reliability and low switching frequency.

The purpose of the invention is to increase the reliability and increase the frequency of cell switching.

For reach the target in a non-volatile memory cell,. containing a core with a BTS and a winding, logic elements and a resistor, a trigger is introduced, and logic elements are made on the elements of NAND. The middle point of the winding is connected through a resistor to the power source, the end of the winding is connected to the output of the first NAND element, the beginning to the output of the second NAND element and to one of the inputs of the third NAND element, the second input of which

10 is connected to the resolution bus, and the output is connected to a single trigger input, the zero input of which is connected to the reset bus, the counting input to the information bus, the forward and inverse outputs 15 to the outputs of the first and second elements AND –NE, respectively, whose second inputs connected to the bus reversal.

Fig, 1 is given a structural diagram

20 cells; in fig. 2 - time diagrams of her work.

The cell contains trigger 1, core 2 with cross-clamping switch and winding, elements AND-NO 3, 4 with open collectors, included according to the OR scheme, element AND-HE 5, resistor 6, information bus 7, remagnetization bus 8, reset bus 9, resolution bus 10.

Claims (2)

The device works as follows. The input pulses, coming through the data bus 7 to the counting input of the trigger 1, change its state. In 3 counting mode, each input pulse of the information bus 7 is accompanied by a pulse in the remagnetization bus 8 (Fig. 2.7.8). At the same time, the potential of logic O, is established in the single state of trigger 1 at the output of element I-HE 4, and the current in the right (Fig. 1) half of the winding reversal core 2 to state 1. In the zero state of trigger 1 core 2 is reversal in the state About current in the left half of the winding. When the power is disconnected and subsequently restored via the reset bus 9, the zero input of trigger 1 receives a pulse setting trigger 1 into state O. If trigger 1 before the power was turned off, it was in one state. then, after the trigger 1 is set to O with the arrival of pulses through the reversal bus 8 and the resolution bus 10 at the output of the NAND element 5, a pulse is produced (Fig. 2, IX), which sets trigger 1 to state 1 This happens as follows. When a pulse arrives at bus 8, level O is established at the output of the element NE-3. In the left half of the winding (Fig. 1), a current appears in relation to which the winding has a large inductive resistance, since Before the power was turned off, the core was in state 1. The voltage drop in the left half of the winding provides level 1 on bus 12 by the time the resolution pulse arrives, (Fig. 2, 10, 12). The leading edge of the resolution pulse is delayed relative to the leading edge of the magnetization reversal pulse for the response time of the NAND element 3. The impulse from the output of the NAND element 5 restores the single state of the trigger 1. In this case, since on the reversal bus 8, impulse 1 is still present, and trigger 1 changes the state to a single one, core 2 is remagnetised to a single state, T-. E. The read out is regenerated 1. If the trigger 1 before the disconnection of the power plant was in the zero state, then there is practically no voltage drop in the left-hand floors, since only the previous condition of the core is confirmed, and with the arrival of the magnetization reversal pulse in the bus 12, the potential O is set equal to the potential at the output of the AND-NOT element 3. The AND-NOT element 5 does not work, and the trigger 1 remains in the zero state. Three cases are illustrated in timing diagrams (Fig. 2): counting operation mode, recovery mode 1 after a power interruption, recovery mode A. On time diagrams, the response time of the device elements is taken into account. The use of this device distinguishes this non-volatile memory cell from the prototype, since eliminates the possibility of loss of cell content due to the influence of the rise time of the supply voltage when switched on to the information recovery process. In addition, the absence of a second winding in the cell, the core allows to increase the switching frequency of the cell. A non-volatile memory cell containing a core with a VGA and a winding, logic elements and a resistor, characterized in that, in order to increase reliability and increase the frequency of cell switching, a trigger is inserted into it, with In this case, the middle point of the core winding is connected via a resistor to the power source, the end of the winding is connected to the output of the first NAND element, the beginning to the output of the second NAND element and to one of the inputs of the third NAND element, the second input of which is It is connected to the resolution bus, and the output is connected to a single trigger input, the zero input of which is connected to the reset bus, the counting input of the information bus, and the direct and inverse outputs to the inputs of the first and second elements AND NOT, respectively, the second inputs of which are connected to the bus remagnetization. Sources of information accepted in the attention of the examination 1.Kolomiytsev AK, Lagunovich Ye.F. Magnetic transistor and magnetically thyristor counting devices that store information during power interruptions. Sat Magnetic elements of discrete action, ed. Science, 1972. 2. Blum G.E. Non-volatile memory cell with BCP transformers, well. Electronics, No. 7, 1977, ed. World, 1977, p. 60 (prototype). Fe8.1