JPS61295765A - Run-length coding and decoding system - Google Patents

Abstract

PURPOSE:To perform the run-length coding and decoding of data economically at a high speed without requiring any complex hardware by a run-length coding table and a decoding table previously and performing processing according to each table during the coding or decoding. CONSTITUTION:Object data of run-length coding or decoding is stored in a buffer memory 81 from a host device through a data signal line 2-2, an AND gate 86, and an OR gate 87. An instruction code from an address signal line 2-1 is stored in a flip-flop 74 through an instruction accepting circuit 72, but when the flip-flop 74 is set, a microprocessor 71 processes data in a buffer memory 81 under the control of a microprogram in a control memory 91 according to the instruction code. The data in the buffer memory 81 is read in the microprocessor 71 through a data line 100 and processed as specified and the result is written on the buffer memory 81 through a data line 101, an AND gate 85, and an OR gate 84.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a run-length encoding/decoding method for high-speed run-length encoding of character and image data and decoding of run-length encoded data. It is.

[Background of the invention]

The reality is that character and image data in videotex and facsimile are compressed by run-length encoding using a method based on Modified No. 7 Man (MH) code or the like. By the way, when displaying such characters and images on a TV display such as Videotex, high-speed processing is required for MH encoding and decoding. When processing, extremely high-speed processing is required. For this reason, for example, Japanese Patent Application Laid-Open No. 58-121866 discloses a method for increasing the speed of decoding, but this method requires complicated circuit configurations such as a code decoding circuit and various counters.

[Purpose of the invention]

An object of the present invention is to provide a run-length encoding/decoding method that can perform run-length encoding of data and decoding of run-length encoded data at high speed and economically without requiring a complicated hardware configuration. .

[Summary of the invention]

For this purpose, the present invention stores a run-length encoding table and a run-length decoding table in advance, performs run-length encoding processing using the run-length encoding table during run-length encoding, and performs run-length decoding. When encoding, run-length decoding processing is performed using a run-length decoding table.

[Embodiments of the invention]

The present invention will be explained below with reference to FIGS. 1 to 10.

First, a run-length encoding/decoding device according to the present invention will be explained. FIG. 2 shows an example of the configuration. The one in this example is microprogram-controlled, and the microprogram-accessible buffer memory 81 includes an input buffer into which data to be encoded or decoded is written, as shown in FIG. 404
, an output buffer 405 into which encoded or decoded data is written, run-length code tables 400, 401 for encoding, and a run-length decode table 402 for decoding. 403 is now available. The data to be processed from the host device is once written into the input buffer 404, then encoded or decoded with reference to the run length table, and then transferred to the host device via the output buffer 405. It is something.

Now, although FIG. 2 mainly shows a configuration centered on the flow of data, the microprocessor 71 performs control by executing a microprogram stored in the control memory 91. There is. The connection with the host device is the address signal line 2-1. Data signal line 2-
2. This is done via the read/write control line 10° initial setting line 11, etc.

As described above, the buffer memory 81 is used for data transfer between this device and a host device and for data processing executed by this device.

By the way, the content from the address signal line 2-1 includes an instruction code sent from the host device to this device, and the instruction code is stored in the 7-lip flop 74 via the instruction reception circuit 72. There is. Also, control memory +91
and the address of the backup memory 81 are assigned different addresses in the same address space from the host device, and the microprogram to the control memory 91 is sent via the address signal line 2-11 and gate 93.5 or gate 94. Writing from a host device is possible using supported addresses and data applied via the data signal line 2-2 and the AND gate 95. Ant gate 92 also causes microprocessor 71 to control memory 9 provided that flip-flop 74 is set.
This gives the address from which to read the microprogram No. 1.

Next, to explain the data in the buffer memo IJ81K, run-length encoded or decoded data is stored in the buffer memo IJ81 from the host device via the data signal line 2-2, the AND gate 86, and the OR gate 87. It has become so. In this case, the address to the buffer memory 81 is given from the host device via the address signal line 2-1, AND gate, and OR gate.

Now, when the data to be processed is stored in the backup memory 81 in this way, the host device gives an instruction code to this device via the address signal line 2-1 as described above, but this instruction code is an instruction code. Flip 7 via reception circuit 72
When the flip 70 knob 74 is set, the microprocessor 71 executes processing on the data in the buffer memory 81 under the control of the microprogram in the control memory 91 according to the instruction code. This is the result. Backer memory 81
The data is read into the microprocessor 71 via the data line (operand bus) 100 and subjected to predetermined calculations, and then written to the buffer memory 81 via the data line (result bus) 101, AND gate, and OR gate 87. It has become.

In this way, run-length encoding or decoding processing is executed by repeatedly executing a series of operations such as reading data from the microprocessor 71 and memory 81 and writing data to the backup memory 81. It is something. The processed data in the buffer memory 81 is then read by the host device via the data line 100° and the data signal line 2-2, but the address to the buffer memory 81 in this case is the address signal line 2-2. 1 is given from the host device via the AND gate 83 and the OR gate 84. In addition, the microprocessor 7
1 resets the flip-flop 74 via the OR gate 73 at the end of processing.

FIG. 3 shows an example of the internal configuration of the microprocessor 71 in FIG. 2. The data in the register group 204 (for example, configured as 16 registers with 16 bits per word) is transferred to the shift register 2 via the operand path 100.
01 as the first operand, and the shift register 202 as the second operand. If it is not a shift operation, shift register 201
, 202 is given to the arithmetic circuit 203 as is.

The arithmetic circuit 203 executes addition, subtraction, and logical operations under the control of the microprogram in the control memory 91 and writes the results to the register group 204 via the Zaruto bus 101. On the other hand, when the microprogram controls the shift operation, the shift register 201 A rightward or leftward shift is executed by the specified number of digits between .202 and the shift result is written to the register group 204 via the arithmetic circuit 203. Note that the status register 200 indicates that the calculation result of the calculation circuit 203 is in an over 70- state or in an over 70- state.
It displays something like a 0-state, and by testing its contents by the microprogram, the microprogram can execute a branching operation within its flow.

Next, to explain the relationship between run length and MH code, Figures 4 and 5 show @O'' run length and '
This shows the relationship for a 1" run length. Run lengths from 0 to 31 can be expressed with a terminator code, but if the run length is 32 or more, a make-up code is used.

By the way, as shown in FIG. 1, the buffer memory is located between addresses A and B-1 in an input cover 7a 404 where data to be encoded or decoded is stored, and between addresses B and B-1.
Between 1 and 2 is allocated to an output buffer 405 in which encoded or decoded data is stored, and furthermore, addresses C and D are allocated.
-1, addresses D and E-1 are 'O'', @1'' run length code table 400 used during encoding.
, 401 K, and between addresses E and F-1 and between addresses F and G-1 are IO" and gi used during decoding.
Run length decoding table 402 of ll. 403
It has been assigned to. The run length code tables 400 and 401 (the contents of D are shown in FIGS. 6(A) and CB, respectively). If we explain the contents of the silane length code table using these figures 6 (a) and [F]), we will explain the MH codes shown in figures 4 and 5 and the bit length of the MH code of 16 bits per word. It is stored in memory. That is, the sixth
As shown in the figure (to), [F]), the bit length is stored in Do-D3, and the MH code is stored in D8 to D15 with the MH code compressed to the D15 bit side. In this case, the run length is used as the memory address, but the memory address in this example is displayed as a relative address with respect to addresses C and D. Furthermore, the contents of the memory are valid only when the run length and memory address match.

Next, each of the run length decoding tables 402 and 403 will be explained using FIG. 7 (4), [F]).
The bit length of the MH code is stored in DO-D3 in the 16-bit memory, and the run length corresponding to the MH code is stored in the 9 pits D4 to D6 and DIO to D15, and the MH code is stored as the memory address. To explain the @O' O run length decode table 402 in detail, for example, when adding a memory address, from FIG. @
sjj, so DO-D3 has a bit length of “5”.
In addition, run length "5" is stored in D4 to D6, and the memory data becomes '0055' in the end.Moreover, to explain the memory address IF and its memory data "0436", % IF (hexadecimal representation) (=”0
0011111”) is the sitter terminated code in Figure 4.
corresponds to '000111' and therefore has a bit length of 6
(in decimal notation), and the run length length is 11 (in decimal notation). 11 in decimal notation is “1011” in binary notation
Therefore, LL has 1011" and LH has 0.
000001' is stored. As shown in FIG. 1, the microprogram 406 is stored in the backup memory 81 after address G, but this is the control memory 91 itself, and from the perspective of the host device,
This shows that the addresses of backup memory 81 and control memory 91 are consecutive.

Now, to explain the relationship between line-by-line uncompressed data and compressed line-by-line data, FIG. 8 is a book showing an example of uncompressed data. As shown
At the beginning of line 41, there are 8 consecutive ``0'' bits, followed by 17 consecutive ``1'' bits, and at the end of that line, i1'' is consecutive bits, followed by redundant bits 10'', and the line ends. (EOL'). Also, at the beginning of line 2, K is set so that 11" bits are continuous, but the uncompressed data created in this way is compressed by encoding as shown in Figure 9. That is, the first encoded data of the line is 10
If the run length is 31 or less, start from the run length of ", then use only the terminator code (T),
If it is 32 or more, it will be compressed using a combination of make-up code (M) and termination code. Note that in FIG. 9, the additional bits of decision 1 in FIG. 8 are not encoded.

This means that if the bit length of one line is known, even if there is a run length of "IO" at the end of the line, that one
This is because 0'' can be expressed by EOL.

By the way, FIG. 10 (5) shows how uncompressed data is stored in the input buffer in the case of FIG.
B) shows how the data is stored in the output buffer after encoding. On the contrary, Fig. 10 [F]
) When the encoded data shown in ) is stored in the input buffer, the manner in which the data is stored in the output buffer upon decoding is such that it can be stored as shown in FIG.

Finally, as an example, how the run length of feather bit "O" is encoded, and conversely, how the encoded thing is decoded is explained as follows. It is. - That is, assuming that '01' are continuous bits at the beginning of the first line, the data corresponding to addresses A and A+1 in the input cover 7a are all 10'', and the data corresponding to address A+2 is t.
The 1st bit and 14th bit are stored as 1o'' and @1'', respectively. If a higher-level device issues an encoding command while data is stored in the input port 7a 404 in this way, first the data corresponding to address A is read out from the buffer memory to the microprocessor, and then the left By shifting in the direction, the number of consecutively shifted out bits of @O" or 'Bi is counted. In this case, all data corresponding to address A is '0'. Therefore, l□I
After counting 16 I's, data corresponding to address A+1 is then read out and similar counting processing is performed. After all, since R1'' is shifted out only when the data corresponding to address A+2 is shifted two pits to the left, the value of the O'' counter at this point becomes 0, and the value of the 111 counter becomes l.

33 (in decimal notation) is “0001000 in binary notation
Since it is expressed as 01', the lower 5 bits of it are ``''
00001' is @Os as an address with run length 1
From the run length code table, "4004 (in hexadecimal notation)" is obtained as memory data, and "@0100" is obtained as the termination code.On the other hand, the upper bit "0001" is added as 00100.
000' and ended up with a run length of 3 in hexadecimal.
As the address 020 of “Oll run length code table, @EOO4 (16
You can get the progress display and use @111 as the makeup code.
0” is obtained. Therefore, the bit O
The run length of " is expressed as @11100100". Thereafter, by performing similar processing, each time two or more bytes of encoded data are received, the two bytes of encoded data are written onto the output buffer.

Next, the decoding will be explained. In this case, the data corresponding to the address A of the input 1 cover is "1110010"
Assuming that 0'' is stored packed in the 15th bit side, the microprocessor first reads the data corresponding to the sea address A from the input buffer in response to the decoding command from the host device, and then writes the 15th bit to the 15th bit. The data up to the 8th bit, that is, the data from the 10" run length decode table is read out using @E4" as the address. '1004' is read out as the data. Therefore, it is known that the run length is 32, and 10'' is written for 32 pits in addresses B and B+1 of output cross 7A.Next, based on the bit length 4, data corresponding to address A @ E4XX”
is shifted 4 bits to the left, so '4XX
Q'', and data is read out from a 10'' run length decode table using 4x'' as an address. '0014' is read out as data. In this case, since LH=0, "O#" is not written to the output buffer, and after this, data "'4XXQ" is shifted 4 bits to the left based on the bit length 4. Yo5 “XXQQ
``'' is obtained, but since the first 1×'' is run-length encoded data of at least ``1'', the decoding process is thereafter performed in the same manner as in the above case. However, since the data corresponding to address 4x is @0014', the second bit at address B+2 will be written later as @0''.

〔Effect of the invention〕

As described above, the present invention has the advantage that run-length encoding of data and decoding of run-length encoded data can be performed at high speed and economically without requiring a complicated hardware configuration.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a memory map of an example of a buffer memory according to the present invention, and FIGS. 2 and 3 show the configuration of an example of a run-length encoding/decoding apparatus according to the present invention and its microprocessor. 4 and 5 are diagrams showing the relationship between the run lengths of 10" and 1", respectively, and the MH code, and FIGS.
Figures 7 (to) and [F]) are diagrams showing run length decode tables for O'' and ``'1'', Figures 8 and 9, respectively. is a diagram for explaining the relationship between uncompressed data and compressed data in line units, and Figure 10 (to), a3) is a diagram showing an example of data stored in the manual buffer and output capacitor 7a, respectively. 71...Microprocessor, 81...Buffer memory, 91...Control memory, 400...fiO'' run length code table, 401...@Is run length code table% 402... “O” run-length decoding table, 403...”1', F-length decoding table, 404...input buffer, 405...output buffer Agent Patent attorney Tadashi Akimoto Minoru No. 3 Figure 4 Figure 5 Figure 6 (A) (B) Figure 7
Figure 8 Figure 9 Figure 10

Claims (1)

[Claims] After the uncompressed data and compressed data from the host device are temporarily stored in the input data buffer, they are encoded and decoded by referring to the run-length code table and run-length decoding table stored in advance under microprogram control. A run-length encoding/decoding method characterized in that the data is encoded and temporarily stored in an output data buffer, and the data in the buffer is transferred to the host device at any time.