JPS61292328A - Manufacture of semiconductor sealing structure - Google Patents

Manufacture of semiconductor sealing structure

Info

Publication number
JPS61292328A
JPS61292328A JP11464386A JP11464386A JPS61292328A JP S61292328 A JPS61292328 A JP S61292328A JP 11464386 A JP11464386 A JP 11464386A JP 11464386 A JP11464386 A JP 11464386A JP S61292328 A JPS61292328 A JP S61292328A
Authority
JP
Japan
Prior art keywords
resin
layer
chip
substrate
organic resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11464386A
Other languages
Japanese (ja)
Inventor
Shinji Ogawa
真二 小川
Hajime Murakami
元 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Hitachi Ltd
Hitachi Tohbu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Tohbu Semiconductor Ltd filed Critical Hitachi Ltd
Priority to JP11464386A priority Critical patent/JPS61292328A/en
Publication of JPS61292328A publication Critical patent/JPS61292328A/en
Pending legal-status Critical Current

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain a sealing structure of an organic resin layer without resin stopper by using resin flow restricting material layer such as silicone grease or oil and deciding the profile of the resin layer with the surface tension of the resin. CONSTITUTION:A resin flow restricting material layer 17 made of silicone grease is formed substantially in a square loop shape to surround a chip 14 in space on the surface of a substrate 11 to which wirings 15 are bonded completely. Then, epoxy resin is supplied by potting on the surface of the substrate inside the layer 17. A heat treatment of 150 deg.C for 30min is, for example, executed in the state that the resin is restricted to expand by the layer 17 to hold the shape by the surface tension to harden the resin, thereby forming an organic resin layer 16 for coating and sealing the chip 14. Thereafter, a cleaning with trichloroethylene is applied to remove the layer 17.

Description

【発明の詳細な説明】 本発明は、絶縁性基板に半導体チップを取付けて有機レ
ジン層で被覆封止した型の半導体封止構造体の製法に関
する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor encapsulation structure in which a semiconductor chip is mounted on an insulating substrate and sealed with an organic resin layer.

従来提案されているこの種の半導体装置としては、第1
図に示したようなものがある。第1図において、lは一
般に印刷回路基板と称されているLメL倣h 絶縁性基板で、その表面には多数の配線層2が形成され
ると共K、凹部が形成されている。基板10の凹部内に
は適当な接着材層3により集積回路内蔵半導体チップ手
が固着され、チップΦ上の多数の電極はボンディングワ
イヤ5を介して対応する配線層2に電気的に接続されて
いる。そして、基板100表面にはチップ4を離間して
取囲むようにレジンストッパー6が接着材により取付け
られ、このストッパー6の内側に有機レジンrgI7を
充填してチップ4をM、慢封止するようになっている。
The first semiconductor device of this type that has been proposed in the past is
There is something like the one shown in the figure. In FIG. 1, reference numeral 1 denotes an insulating substrate generally referred to as a printed circuit board, on the surface of which a large number of wiring layers 2 are formed, as well as recesses. A semiconductor chip with a built-in integrated circuit is fixed in the recess of the substrate 10 by a suitable adhesive layer 3, and a large number of electrodes on the chip Φ are electrically connected to the corresponding wiring layer 2 via bonding wires 5. There is. Then, a resin stopper 6 is attached to the surface of the substrate 100 with an adhesive so as to surround the chip 4 at a distance, and the inside of this stopper 6 is filled with organic resin rgI7 to seal the chip 4 permanently. It has become.

しかしながら、このような半導体装置においては、次の
ような問題点がある。
However, such a semiconductor device has the following problems.

(1)レジ/ストンパー6を形成して基板10に取付け
るので、それに伴って材料費、加工費、取付費などが必
要で、装置のコストアップをもたらす。
(1) Since the register/stomper 6 is formed and attached to the substrate 10, material costs, processing costs, installation costs, etc. are required accordingly, resulting in an increase in the cost of the device.

°(2)有機レジン層7を形成する際に、レジ/ストッ
パー6でレジン流れを規制すると共にレンン厚さを規制
するようになっているので、有機レジン層7はストッパ
ー6の厚さに対応し、て相肖厚くなり、装置を薄型且つ
小型に構成しにくい。
(2) When forming the organic resin layer 7, the resist/stopper 6 regulates the flow of the resin and also regulates the thickness of the resin, so the organic resin layer 7 corresponds to the thickness of the stopper 6. However, it becomes bulky and difficult to make the device thin and compact.

(3)レジンストッパー6を設けるために特別に設置ス
ペースを確保する必要があり、基板表面における利用可
能面積及びレイアウトの自由度が低下する。
(3) It is necessary to secure a special installation space to provide the resin stopper 6, which reduces the usable area on the substrate surface and the degree of freedom in layout.

なお、上記(3)の問題点を解決するために、有機レジ
ン層7を形成後、レジンストッパー6を取外すことも考
えられるが、この場合には取扱い中に有機レジン層7の
ステップ状端縁部が損傷を受けやすく、このため外観不
良の発生頻度が高くなったり、封止の気密性が害されて
装置の信頼性が低下したりする問題点がある。
In order to solve the problem (3) above, it is possible to remove the resin stopper 6 after forming the organic resin layer 7, but in this case, the step-like edge of the organic resin layer 7 may be removed during handling. There are problems in that the parts are easily damaged, which increases the frequency of appearance defects and impairs the airtightness of the seal, reducing the reliability of the device.

本発明の目的は、上記した種々の問題点を解決した新規
な半導体封止構造体の製法を提供することにある。
An object of the present invention is to provide a novel method for manufacturing a semiconductor encapsulation structure that solves the various problems described above.

本発明は、シリコングリースやシリコンオイルのような
レジン流れ規制材層を用い且つレジンの表面張力を用い
て有機レジン層の外形を決定するようにしたことを特徴
とするものであり、以下、図面に示す実施例について詳
述する。
The present invention is characterized in that the outer shape of the organic resin layer is determined by using a resin flow regulating material layer such as silicone grease or silicone oil and by using the surface tension of the resin. The embodiment shown in will be described in detail.

第2図は、本発明をウォッチモジュール用集積回路装置
に適用した一実施例を示すもので、11は例えばガラス
クロスにエポキシレジンを含浸させて成る絶縁性基板、
12は、基板10に被着したCu箔をホトリングラフィ
技術によりバターニングした後、Cuメッキ、Niメッ
キ、Auメッキを施して形成した多数の配線層である。
FIG. 2 shows an embodiment in which the present invention is applied to an integrated circuit device for a watch module, and 11 is an insulating substrate made of, for example, glass cloth impregnated with epoxy resin;
Reference numeral 12 denotes a large number of wiring layers formed by patterning Cu foil adhered to the substrate 10 using photolithography technology and then applying Cu plating, Ni plating, and Au plating.

基板11に設けられた凹部底面には、エポキシ接着材又
はAgペーストなどからなる接着材層13により集積回
路内蔵半導体(シリコン)チップ14が固着され、チッ
プ1Φ上の多数の電極は例えば超音波式ネイルヘッドボ
ンディングではりわたされるボンディングワイヤ15に
より対応する配線層12に電気的に接続されている。そ
して、基板11上には、チップ14と、ボンディングワ
イヤ15と、配線層1zの端部とをおおうようにエポキ
シレジンからなる有機レジン層16が形成されている。
A semiconductor (silicon) chip 14 with a built-in integrated circuit is fixed to the bottom surface of the recess provided in the substrate 11 with an adhesive layer 13 made of epoxy adhesive or Ag paste, and a large number of electrodes on the chip 1Φ are connected using an ultrasonic method, for example. It is electrically connected to the corresponding wiring layer 12 by a bonding wire 15 that is passed through nail head bonding. An organic resin layer 16 made of epoxy resin is formed on the substrate 11 so as to cover the chip 14, the bonding wires 15, and the ends of the wiring layer 1z.

この有機レジン層16はチップ14を被覆封止するため
のもので、流動時に広がりを規制された際に表面張力に
よって形成されるなめらかな球面を呈した形で基板表面
に終端している点に特徴を有する。
This organic resin layer 16 is for covering and sealing the chip 14, and terminates on the substrate surface in a smooth spherical shape formed by surface tension when its spread is restricted during flow. Has characteristics.

ここで、第3a図を参照して第2図の装置の製造過程を
説明すると、まず第3a図に示すように、ワイヤ15の
ボンディニIグが終了した基板11の表面にチップ14
を離間して取囲むようにほぼ方形ループ状にシリコング
リースからなるレジン流れ規か1材層17を形成する。
Here, the manufacturing process of the device shown in FIG. 2 will be explained with reference to FIG. 3a. First, as shown in FIG.
A resin flow guide material layer 17 made of silicone grease is formed in a substantially rectangular loop shape so as to surround and space apart from each other.

このためには、例えばシリコングリースを層17に対応
するパターンで吸着した後基板110表面にそのまま押
圧して転写又は塗布することのできる器具を用いるとよ
い。
For this purpose, it is preferable to use, for example, an instrument that can adsorb silicone grease in a pattern corresponding to the layer 17 and then press it directly onto the surface of the substrate 110 to transfer or apply it.

°°次に、第3b図に示すようにレジン流れ規制材層1
7の内側の基板表面部分上にポツティングによりエポキ
シレジンを供給する。そして、エポキシレジンが規制材
層17でその広がりを規制されて表面張力でその、形状
を保持している状態で例えば15(I’、30分程度の
熱処理を施してエポキシレン、/を硬化させることによ
りチップ14を被覆封止する有機レジン層(メツシュを
付した部分)16を形成する。このようにして形成され
た有機レジン層16は第2図に示すような好ましいなめ
らかな外形を呈するものとなる。
°°Next, as shown in Figure 3b, the resin flow regulating material layer 1
Epoxy resin is supplied onto the inner surface of the substrate 7 by potting. Then, while the epoxy resin is restrained from spreading by the regulating material layer 17 and its shape is maintained by surface tension, heat treatment is performed for about 30 minutes to harden the epoxy resin. By doing this, an organic resin layer (a portion with a mesh) 16 that covers and seals the chip 14 is formed.The organic resin layer 16 formed in this way has a preferable smooth outer shape as shown in FIG. becomes.

この後は、第3c図に示すように例えばトリクロールエ
チレンによる洗浄処理を、適用してシリコングリースか
らなるレジ/流れ規制材層17を除去する。
Thereafter, as shown in FIG. 3c, a cleaning treatment using, for example, trichlorethylene is applied to remove the register/flow regulating material layer 17 made of silicone grease.

このようにレジン流れ規制材層17を除去するのは、そ
れが残存していると、その設置スペースを自由に利用で
きないこと、外観上好ましくないこと、基板上の配線層
に付着して導通不良を招くおそれがあること、取扱い中
に作業者や他の部品に付着するおそれがあることなどに
よるものである。
The reason why the resin flow regulating material layer 17 is removed in this way is that if it remains, the installation space cannot be used freely, the appearance is unfavorable, and it adheres to the wiring layer on the board, resulting in poor conductivity. This is because there is a risk that the product may cause damage to the product, and that it may adhere to workers or other parts during handling.

第4図は、本発明を混成集積回路装置に適用した他の実
施例を示すもので、21はセラミックスからなる絶縁性
基板、22は基板210表面に形成された多数の配線層
、23は例えば金属ろう材からなる接着材層、24は接
着材層23により基板21の表面に固着された集積回路
内蔵半導体チッフミ25はチップ24上の多数の電極を
対応する配線層22に!気接続するボンディングワイヤ
、26は第3a図〜第3c図について前述したのと同様
の方法でチップ24を被覆封止すべく形成された有機レ
ジン層である。
FIG. 4 shows another embodiment in which the present invention is applied to a hybrid integrated circuit device, in which 21 is an insulating substrate made of ceramics, 22 is a large number of wiring layers formed on the surface of the substrate 210, and 23 is, for example, An adhesive layer 24 made of a metal brazing material is fixed to the surface of the substrate 21 by an adhesive layer 23. A semiconductor chip 25 with a built-in integrated circuit connects a large number of electrodes on the chip 24 to the corresponding wiring layer 22! The bonding wires 26 are organic resin layers formed to encapsulate the chip 24 in a manner similar to that described above with respect to FIGS. 3a-3c.

なお、上記した実施例において、レジン規制材層17と
しては、シリコングリースの他にシリコンオイルを用い
ることもできる。これらのシリコングリースやシリ、コ
ンオイルはレジンの熱処理温度に十分針えうるので、本
発明の実施上好都合なものであるが、本発明の実施に6
たりては、これらのものに限定されず、レジン流れを規
制でき且つ熱処理温度に耐えつる他の物質を利用しても
よい。また、有機レジン層16.26の材料としても、
エポキシレジンのような熱硬化性レジンに限らず、適当
な熱可塑性レジ/を使用することもできる。
In addition, in the above-mentioned embodiment, as the resin regulating material layer 17, silicone oil can also be used in addition to silicone grease. These silicone greases, silicone, and silicone oils are suitable for carrying out the present invention because they can reach the heat treatment temperature of the resin.
However, the material is not limited to these materials, and other materials that can regulate resin flow and withstand heat treatment temperatures may be used. Also, as a material for the organic resin layer 16.26,
In addition to thermosetting resins such as epoxy resins, suitable thermoplastic resins may also be used.

以上に詳述したように1本発明によれば、組立部品とし
てのレジンストッパーを用いなくてすむので、大幅なコ
ストダウンが可能であること、装置を薄壓且つ小型に構
成できること、基板表面における利用可能面積及びレイ
アウトの自由度が増大されること、有機レジン層の端縁
部が損傷を受けにくいなめらかな形状であるため外観不
良並びに信頼性低下が起こりにくいことなど優れた作用
効果が得られるものである。
As detailed above, according to the present invention, there is no need to use a resin stopper as an assembly component, so it is possible to significantly reduce costs, the device can be made thin and compact, and the Excellent functions and effects can be obtained, such as increased usable area and freedom of layout, and the smooth shape of the edges of the organic resin layer, which makes them less likely to be damaged, making it less likely that defects in appearance or deterioration in reliability will occur. It is something.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来の半導体装置の断面図、第2■は、本発
明の一実施例による半導体装置の断面図、 第3a図乃至第8c図は、第2図の装置の製造過程を示
す斜視図、 第4図は、本発明の他の実施例による半導体装置を示す
断面図である。 1.11.21・・・絶縁性基板、2.12.22・・
・配線層、3.13.23・・・接着材層、小、14.
24・・・半導体チップ、5.15.25・・・ボンデ
ィングワイヤ、16,26・・・有機レジン層、17・
・・レジン流れ規制材層。 第  1  図 第  2  図 第  4  図
1 is a sectional view of a conventional semiconductor device, 2) is a sectional view of a semiconductor device according to an embodiment of the present invention, and 3a to 8c show the manufacturing process of the device of FIG. 2. FIG. 4 is a sectional view showing a semiconductor device according to another embodiment of the present invention. 1.11.21... Insulating substrate, 2.12.22...
・Wiring layer, 3.13.23...Adhesive layer, small, 14.
24... Semiconductor chip, 5.15.25... Bonding wire, 16, 26... Organic resin layer, 17.
...Resin flow regulating material layer. Figure 1 Figure 2 Figure 4

Claims (1)

【特許請求の範囲】[Claims] 1、表面に半導体チップが固着され且つこのチップの多
数の電極が前記表面上の対応する配線層に電気接続され
た絶縁性基板を用意する工程と、前記基板の表面上に前
記チップを離間して取囲むようなパターンでレジン流れ
規制材層を形成する工程と、前記レジン流れ規制材層の
内側で前記基板の表面上に前記チップをおおうように流
動化した有機レジン材料を供給する工程と、この供給さ
れた有機レジン材料が前記レジン流れ規制材層によりそ
の広がりを規制され且つ表面張力でその形状を保ってい
る状態において前記有機レジン材料を硬化させることに
より前記チップを被覆封止する有機レジン層を形成する
工程とを含むことを特徴とする半導体封止構造体の製法
1. A step of preparing an insulating substrate on which a semiconductor chip is fixed and a number of electrodes of the chip are electrically connected to corresponding wiring layers on the surface, and separating the chip on the surface of the substrate. forming a resin flow regulating material layer in a pattern surrounding the chip; and supplying a fluidized organic resin material on the surface of the substrate inside the resin flow regulating material layer so as to cover the chip. The supplied organic resin material covers and seals the chip by curing the organic resin material in a state where its spread is regulated by the resin flow regulating material layer and its shape is maintained by surface tension. A method for manufacturing a semiconductor encapsulation structure, comprising the step of forming a resin layer.
JP11464386A 1986-05-21 1986-05-21 Manufacture of semiconductor sealing structure Pending JPS61292328A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11464386A JPS61292328A (en) 1986-05-21 1986-05-21 Manufacture of semiconductor sealing structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11464386A JPS61292328A (en) 1986-05-21 1986-05-21 Manufacture of semiconductor sealing structure

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP9726279A Division JPS5623758A (en) 1979-08-01 1979-08-01 Semiconductor device and manufacture threof

Publications (1)

Publication Number Publication Date
JPS61292328A true JPS61292328A (en) 1986-12-23

Family

ID=14642936

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11464386A Pending JPS61292328A (en) 1986-05-21 1986-05-21 Manufacture of semiconductor sealing structure

Country Status (1)

Country Link
JP (1) JPS61292328A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6060779A (en) * 1997-04-30 2000-05-09 Shinko Electric Industries, Co., Ltd. Resin sealed ceramic package and semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4837411U (en) * 1971-09-07 1973-05-08
JPS532078A (en) * 1976-06-28 1978-01-10 Citizen Watch Co Ltd Sealing structure for semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4837411U (en) * 1971-09-07 1973-05-08
JPS532078A (en) * 1976-06-28 1978-01-10 Citizen Watch Co Ltd Sealing structure for semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6060779A (en) * 1997-04-30 2000-05-09 Shinko Electric Industries, Co., Ltd. Resin sealed ceramic package and semiconductor device

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