JPH04302457A - Fabrication of hybrid ic board - Google Patents
Fabrication of hybrid ic boardInfo
- Publication number
- JPH04302457A JPH04302457A JP3091680A JP9168091A JPH04302457A JP H04302457 A JPH04302457 A JP H04302457A JP 3091680 A JP3091680 A JP 3091680A JP 9168091 A JP9168091 A JP 9168091A JP H04302457 A JPH04302457 A JP H04302457A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- circuit board
- dam
- dam layer
- adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000010410 layer Substances 0.000 claims abstract description 75
- 239000000463 material Substances 0.000 claims abstract description 42
- 229920005989 resin Polymers 0.000 claims abstract description 29
- 239000011347 resin Substances 0.000 claims abstract description 29
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 230000001681 protective effect Effects 0.000 claims abstract description 21
- 239000012790 adhesive layer Substances 0.000 claims abstract description 18
- 239000000853 adhesive Substances 0.000 claims abstract description 8
- 230000001070 adhesive effect Effects 0.000 claims abstract description 8
- 239000011253 protective coating Substances 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 5
- 239000003822 epoxy resin Substances 0.000 abstract description 22
- 229920000647 polyepoxide Polymers 0.000 abstract description 22
- 238000001723 curing Methods 0.000 abstract description 5
- 238000013007 heat curing Methods 0.000 abstract 2
- 239000011521 glass Substances 0.000 description 5
- 239000000470 constituent Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 239000012466 permeate Substances 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 235000019353 potassium silicate Nutrition 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000001029 thermal curing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、半導体チップを実装し
、このチップ及びこのチップに接続するボンディングワ
イヤを保護樹脂層で封止した混成集積回路基板の製造方
法の改良に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improved method for manufacturing a hybrid integrated circuit board in which a semiconductor chip is mounted and the chip and bonding wires connected to the chip are sealed with a protective resin layer.
【０００２】0002
【従来の技術】近年、回路パターンを有する回路基板本
体にＩＣやＬＳＩなどの半導体チップを実装した混成集
積回路基板が各種の分野に多用されている。2. Description of the Related Art In recent years, hybrid integrated circuit boards, in which semiconductor chips such as ICs and LSIs are mounted on a circuit board body having a circuit pattern, have been widely used in various fields.
【０００３】図３は、従来の混成集積回路基板の一例を
示す。図中の１は、回路基板本体である。この回路基板
本体１は、絶縁基材２上に回路パターン３を形成した構
造になっている。前記回路基板本体１上には、半導体チ
ップ４が接着剤層５を介して搭載されている。前記半導
体チップ４は、前記回路基板本体１の所望の回路パター
ンにボンディングワイヤ６を介してボンディングされて
いる。このボンディングワイヤ６は、前記回路基板本体
１の回路パターン３と前記チップ４上面の電極パッド（
図示せず）とを電気的に接続している。前記半導体チッ
プ４及びボンディングワイヤ６周辺の前記回路基板本体
１上には、厚み０．６ｍｍ程度の枠状のダム層７が形成
されている。前記ダム層７は、エポキシ系樹脂やシリコ
ーン系樹脂などの液状樹脂をディスペンサーなどの装置
を用いて描画しながら塗布した後硬化することにより形
成される。前記ダム層７で囲まれた前記回路基板本体１
上には、保護樹脂層８が前記半導体チップ４及びボンデ
ィングワイヤ６を封止するように設けられている。前記
保護樹脂層８は、エポキシ系樹脂などの液状樹脂を前記
ダム層７の枠内にコーティングすることにより形成され
る。FIG. 3 shows an example of a conventional hybrid integrated circuit board. 1 in the figure is the circuit board main body. This circuit board main body 1 has a structure in which a circuit pattern 3 is formed on an insulating base material 2. A semiconductor chip 4 is mounted on the circuit board body 1 with an adhesive layer 5 interposed therebetween. The semiconductor chip 4 is bonded to a desired circuit pattern of the circuit board body 1 via bonding wires 6. This bonding wire 6 connects the circuit pattern 3 of the circuit board body 1 and the electrode pad (
(not shown) are electrically connected. A frame-shaped dam layer 7 with a thickness of about 0.6 mm is formed on the circuit board body 1 around the semiconductor chip 4 and the bonding wires 6. The dam layer 7 is formed by applying a liquid resin such as an epoxy resin or a silicone resin in a drawing manner using a device such as a dispenser, and then curing the resin. The circuit board body 1 surrounded by the dam layer 7
A protective resin layer 8 is provided thereon to seal the semiconductor chip 4 and bonding wires 6. The protective resin layer 8 is formed by coating the frame of the dam layer 7 with a liquid resin such as an epoxy resin.
【０００４】0004
【発明が解決しようとする課題】しかしながら、従来の
混成集積回路基板によれば、ダム層７を形成する際に液
状樹脂が流動変形して回路基板本体１上に広がって低く
なったり、高さがバラついたりすることがある。このた
め、保護樹脂層８の厚さを十分に厚くできず、半導体チ
ップ４及びボンディングワイヤ６の封止が不完全になっ
て、信頼性を低下させるという問題があった。また、ダ
ム層７を均一な幅又は高さにする必要があるが、ダム層
７の材料である樹脂の粘度、形成条件等の管理が困難で
ある。[Problems to be Solved by the Invention] However, in the conventional hybrid integrated circuit board, when forming the dam layer 7, the liquid resin flows and deforms and spreads over the circuit board body 1, causing the height to be lowered or lowered. may vary. Therefore, there was a problem in that the protective resin layer 8 could not be made sufficiently thick, resulting in incomplete sealing of the semiconductor chip 4 and the bonding wires 6, resulting in lower reliability. Further, although it is necessary to make the dam layer 7 uniform in width or height, it is difficult to control the viscosity of the resin that is the material of the dam layer 7, the formation conditions, etc.
【０００５】本発明は上記事情に鑑みてなされたもので
、十分かつ一定の高さのダム層を有し、半導体チップ及
びワイヤを十分な厚さの保護樹脂層で良好に封止した高
信頼性の混成集積回路基板の製造方法を提供することを
目的とする。The present invention has been made in view of the above circumstances, and is a highly reliable product having a dam layer of a sufficient and constant height, and in which semiconductor chips and wires are well sealed with a protective resin layer of sufficient thickness. An object of the present invention is to provide a method for manufacturing a hybrid integrated circuit board.
【０００６】[0006]
【課題を解決するための手段】本発明は、絶縁基材上に
回路パターンを有すると共に該回路パターンの外部接続
領域を除く表面に保護被膜を有する回路基板本体と、前
記本体の所望の回路パターンにダイボンディングされた
半導体チップと、前記本体の回路パターンと前記チップ
上面の電極パッドとを接続するボンディングワイヤと、
前記チップ及びボンディングワイヤ周辺の前記保護被膜
に接着剤層を介して形成された枠状のダム層と、このダ
ム層で囲まれた前記本体上に前記チップ及びワイヤを封
止するように設けられた保護樹脂層とを具備した混成集
積回路基板の製造する方法において、前記ダム層は、ダ
ム層形成用枠材を前記チップ及びボンディングワイヤ周
辺の前記保護被膜上に前記保護樹脂層と同じ材料からな
る接着剤を介して形成した後、硬化により前記接着剤の
一部を構成する樹脂を前記ダム層形成用枠材中に浸透さ
せることにより形成することを特徴とする混成集積回路
基板の製造方法である。Means for Solving the Problems The present invention provides a circuit board main body having a circuit pattern on an insulating base material and a protective coating on the surface of the circuit pattern except for an external connection area, and a circuit board body having a circuit pattern on the main body. a semiconductor chip that is die-bonded to the semiconductor chip; a bonding wire that connects the circuit pattern of the main body and the electrode pad on the top surface of the chip;
A frame-shaped dam layer is formed on the protective coating around the chip and the bonding wire via an adhesive layer, and a frame-shaped dam layer is provided on the main body surrounded by the dam layer so as to seal the chip and the wire. In the method for manufacturing a hybrid integrated circuit board comprising a protective resin layer, the dam layer is made of the same material as the protective resin layer, and a frame material for forming the dam layer is placed on the protective coating around the chip and the bonding wire. A method for producing a hybrid integrated circuit board, comprising: forming the hybrid integrated circuit board using an adhesive, and then curing the resin constituting a part of the adhesive to infiltrate into the frame material for forming the dam layer. It is.
【０００７】本発明において、絶縁基材の材料としては
、例えばガラスエポキシ樹脂等が挙げられる。[0007] In the present invention, examples of the material for the insulating base material include glass epoxy resin.
【０００８】本発明において、ダム層の断面状態は粗れ
ている方が良い。これは、枠状のダム層材料を硬化する
際に接着剤層からその材料を毛細管現象により浸透させ
、硬化させるためである。粗れた断面状態を得るには、
ル−タ加工（削り出し）あるいは金型による打ち抜き等
が挙げられるが、後者の方が好ましい。前記ダム層の材
料としては、ガラスエポキシが好ましい。In the present invention, it is preferable that the dam layer has a rough cross-sectional condition. This is because when the frame-shaped dam layer material is cured, the material permeates through the adhesive layer by capillary action and is cured. To obtain a rough cross-sectional condition,
Examples include router machining (machining) and punching with a mold, but the latter is preferred. The material for the dam layer is preferably glass epoxy.
【０００９】[0009]
【作用】本発明においては、まず、ダム層形成用枠材を
ディスペンサーなどの装置を用いて前記チップ及びボン
ディングワイヤ周辺の前記保護被膜上にエポキシ系樹脂
からなる第２接着剤層を介して形成した後、前記ダム層
形成用枠材を硬化させる。この硬化により、硬化時の熱
により第２接着剤層の粘度が低下すると同時に、第２接
着剤層の構成材料であるエポキシ系樹脂材料が毛細管現
象により前記枠材に浸透し、内部にエポキシ系樹脂を含
浸した状態のダム層を形成される。[Operation] In the present invention, first, a frame material for forming a dam layer is formed on the protective coating around the chip and the bonding wire via a second adhesive layer made of epoxy resin using a device such as a dispenser. After that, the dam layer forming frame material is cured. Through this curing, the viscosity of the second adhesive layer decreases due to the heat during curing, and at the same time, the epoxy resin material that is the constituent material of the second adhesive layer penetrates into the frame material due to capillary action, and the epoxy resin material inside A dam layer impregnated with resin is formed.
【００１０】0010
【実施例】以下、本発明の一実施例について図１及び図
２を参照して説明する。図１は混成集積回路基板の断面
図、図２は図１の平面図である。Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is a sectional view of a hybrid integrated circuit board, and FIG. 2 is a plan view of FIG. 1.
【００１１】図中の１１は、回路基板本体である。この
回路基板本体１１は、ガラスエポキシ樹脂からなる絶縁
基材１２上に回路パターン１３を形成した構造になって
いる。前記回路基板本体１１上には、半導体チップ１４
が第１接着剤層１５を介して搭載されている。前記半導
体チップ１４は、前記回路基板本体１１の所望の回路パ
ターンにボンディングワイヤ１６を介してダイボンディ
ングされている。このボンディングワイヤ１６は、前記
回路基板本体１１の回路パターン１３と前記チップ１４
上面の電極パッド（図示せず）とを電気的に接続してい
る。前記半導体チップ１４及びボンディングワイヤ１６
周辺の前記回路基板本体１１上には、厚み０．６ｍｍで
内径１０ｍｍ，外径１２ ｍｍの正方形状のダム層１
７がエポキシ系樹脂からなる第２接着剤層１８を介して
形成されている。ここで、ダム層１７の断面状態は粗れ
ている状態の方が好ましく、その材料としてはガラスエ
ポキシ系樹脂を用いた。前記ダム層１７で囲まれた前記
回路基板本体１１上には、エポキシ系樹脂からなる保護
樹脂層１８が前記半導体チップ１４及びボンディングワ
イヤ１６を封止するように設けられている。11 in the figure is a circuit board body. This circuit board main body 11 has a structure in which a circuit pattern 13 is formed on an insulating base material 12 made of glass epoxy resin. A semiconductor chip 14 is mounted on the circuit board body 11.
is mounted via the first adhesive layer 15. The semiconductor chip 14 is die-bonded to a desired circuit pattern of the circuit board body 11 via bonding wires 16. This bonding wire 16 connects the circuit pattern 13 of the circuit board body 11 and the chip 14.
It is electrically connected to an electrode pad (not shown) on the upper surface. The semiconductor chip 14 and the bonding wire 16
A square dam layer 1 with a thickness of 0.6 mm, an inner diameter of 10 mm, and an outer diameter of 12 mm is placed on the circuit board main body 11 in the periphery.
7 is formed via a second adhesive layer 18 made of epoxy resin. Here, it is preferable that the cross-sectional state of the dam layer 17 is rough, and glass epoxy resin is used as the material thereof. A protective resin layer 18 made of epoxy resin is provided on the circuit board body 11 surrounded by the dam layer 17 so as to seal the semiconductor chip 14 and the bonding wires 16.
【００１２】上記構成の混成集積回路基板は、次のよう
にして製造する。まず、絶縁基材１２上に導電材料層（
図示せず）を形成した後、パタ−ニングして回路パタ−
ン１３を形成し、回路基板本体１１を形成した。つづい
て、この回路基板本体１１の所定の位置上に第１接着剤
層１５を介して半導体チップ１４を形成した。次に、前
記回路基板本体１１の回路パターン１３と前記半導体チ
ップ１４上面の電極パッド（図示せず）とを、ボンディ
ングワイヤ１６を介して電気的に接続した。次いで、前
記半導体チップ１４及びボンディングワイヤ１６周辺の
前記回路基板本体１１上に、エポキシ系樹脂からなる第
２接着剤層１８を液状のガラスエポキシ系樹脂をディス
ペンサーなどの装置を用いて描画しながら塗布し、厚み
０．６ｍｍ，内径１０ｍｍ，外径１２ｍｍの正方形状の
ダム層形成用枠材を形成した。The hybrid integrated circuit board having the above structure is manufactured as follows. First, a conductive material layer (
(not shown), and then patterned to create a circuit pattern.
Then, the circuit board body 11 was formed. Subsequently, a semiconductor chip 14 was formed on a predetermined position of this circuit board body 11 with a first adhesive layer 15 interposed therebetween. Next, the circuit pattern 13 of the circuit board body 11 and the electrode pads (not shown) on the upper surface of the semiconductor chip 14 were electrically connected via bonding wires 16. Next, a second adhesive layer 18 made of epoxy resin is applied onto the circuit board body 11 around the semiconductor chip 14 and the bonding wires 16 while drawing a liquid glass epoxy resin using a device such as a dispenser. Then, a square frame material for forming a dam layer was formed with a thickness of 0.6 mm, an inner diameter of 10 mm, and an outer diameter of 12 mm.
【００１３】次に、第２接着剤層１８上に、ダム層用枠
を搭載させ熱硬化を行なった。これにより、前記第２接
着剤層１８の粘度が低下するとと同時に、接着剤を構成
するエポキシ系樹脂が前記ダム層形成用枠材に浸透し、
前記ダム層形成用枠材が硬化してダム層１７が形成され
た。ダム層用枠の接着と同時に、枠材への浸透が成され
たダム層１７が形成された。つづいて、前記ダム層形成
用枠材内に保護樹脂層用のエポキシ樹脂を流し込み、前
記半導体チップ１４及びボンディングワイヤ１６を覆っ
た。次に、熱硬化を行い、半導体チップ１４及びボンデ
ィングワイヤ１６を封止する保護樹脂層１８を形成して
、混成集積回路基板を製造した。Next, a dam layer frame was mounted on the second adhesive layer 18 and thermally cured. As a result, the viscosity of the second adhesive layer 18 decreases, and at the same time, the epoxy resin constituting the adhesive permeates into the dam layer forming frame material.
The dam layer forming frame material was cured, and the dam layer 17 was formed. Simultaneously with adhesion of the frame for the dam layer, a dam layer 17 was formed in which the frame material was penetrated. Subsequently, an epoxy resin for a protective resin layer was poured into the frame material for forming the dam layer to cover the semiconductor chip 14 and the bonding wires 16. Next, thermal curing was performed to form a protective resin layer 18 for sealing the semiconductor chip 14 and bonding wires 16, thereby manufacturing a hybrid integrated circuit board.
【００１４】上記実施例に係る混成集積回路基板の製造
方法によれば、ダム層形成用枠材をディスペンサーなど
の装置を用いて前記チップ及びボンディングワイヤ周辺
の前記保護被膜上にエポキシ系樹脂からなる第２接着剤
層１８を介して形成した後、前記ダム層形成用枠材を硬
化させるため、硬化を行う際、硬化時の熱により接着剤
層１８の粘度が低下すると同時に、接着剤層１８の構成
材料であるエポキシ系樹脂材料が毛細管現象により前記
枠材に浸透し、内部にエポキシ系樹脂を含浸した状態の
ダム層１７を形成できる。つまり、上記ダム層形成用枠
材は絶縁器材と同じ材料であるガラスエポキシを用いて
作製した枠材であるため、従来のように液状樹脂に起因
する樹脂流動を伴うことなく、その高さ，幅を自在に調
整できる。また、上記ダム層形成用枠材には、上述した
ように熱硬化時に接着剤層１８の構成材料であるエポキ
シ系樹脂材料を含浸させることができるため、熱硬化に
より作製されたダム層１７にはエポキシ系樹脂材料が充
分含浸され、ダム層１７と保護樹脂層１８との密着性を
良好に保つことができる。According to the method for manufacturing a hybrid integrated circuit board according to the above embodiment, a frame material for forming a dam layer made of epoxy resin is applied onto the protective coating around the chip and the bonding wire using a device such as a dispenser. After forming the dam layer through the second adhesive layer 18, the frame material for forming the dam layer is cured. The epoxy resin material that is the constituent material permeates the frame material by capillary action, forming the dam layer 17 in which the epoxy resin is impregnated inside. In other words, since the frame material for forming the dam layer is a frame material made using glass epoxy, which is the same material as the insulating equipment, its height and height are The width can be adjusted freely. In addition, since the frame material for forming the dam layer can be impregnated with the epoxy resin material that is the constituent material of the adhesive layer 18 during thermosetting as described above, the dam layer 17 produced by thermosetting is sufficiently impregnated with the epoxy resin material, and good adhesion between the dam layer 17 and the protective resin layer 18 can be maintained.
【００１５】なお、上記実施例では、ダム層の形状が四
角形である場合について述べたが、これに限定されない
。[0015] In the above embodiment, the case where the dam layer has a rectangular shape has been described, but the shape is not limited to this.
【００１６】[0016]
【発明の効果】以上詳述した如く本発明によれば、十分
かつ一定の高さのダム層を有し、半導体チップ及びワイ
ヤを十分な厚さの保護樹脂層で良好に封止した高信頼性
の混成集積回路基板を提供できる。Effects of the Invention As detailed above, according to the present invention, a highly reliable product having a dam layer of a sufficient and constant height and sealing semiconductor chips and wires well with a protective resin layer of sufficient thickness. It is possible to provide a multifunctional hybrid integrated circuit board.
【図１】本発明の一実施例に係る混成集積回路基板の断
面図。FIG. 1 is a cross-sectional view of a hybrid integrated circuit board according to an embodiment of the present invention.
【図２】図１の保護樹脂層を除いた平面図。FIG. 2 is a plan view of FIG. 1 with the protective resin layer removed.
【図３】従来の混成集積回路基板の断面図。FIG. 3 is a cross-sectional view of a conventional hybrid integrated circuit board.
１１…回路基板本体、１２…絶縁基材、１３…回路パタ
−ン、１４…半導体チップ、１５，１８…接着剤層、１
６…ボンディングワイヤ、１７…ダム層、１８…保護樹
脂層。DESCRIPTION OF SYMBOLS 11... Circuit board main body, 12... Insulating base material, 13... Circuit pattern, 14... Semiconductor chip, 15, 18... Adhesive layer, 1
6... Bonding wire, 17... Dam layer, 18... Protective resin layer.
Claims (1)
共に該回路パターンの外部接続領域を除く表面に保護被
膜を有する回路基板本体と、前記本体の所望の回路パタ
ーンにダイボンディングされた半導体チップと、前記本
体の回路パターンと前記チップ上面の電極パッドとを接
続するボンディングワイヤと、前記チップ及びボンディ
ングワイヤ周辺の前記保護被膜に接着剤層を介して形成
された枠状のダム層と、このダム層で囲まれた前記本体
上に前記チップ及びワイヤを封止するように設けられた
保護樹脂層とを具備した混成集積回路基板を製造する方
法において、前記ダム層は、ダム層形成用枠材を前記チ
ップ及びボンディングワイヤ周辺に前記保護樹脂層と同
じ材料からなる接着剤を介して形成した後、硬化により
前記接着剤の一部を構成する樹脂を前記ダム層形成用枠
材中に浸透させることにより形成することをことを特徴
とする混成集積回路基板の製造方法。1. A circuit board body having a circuit pattern on an insulating base material and having a protective coating on the surface of the circuit pattern except for an external connection area, and a semiconductor chip die-bonded to a desired circuit pattern of the body. , a bonding wire connecting the circuit pattern of the main body and the electrode pad on the top surface of the chip, a frame-shaped dam layer formed on the protective coating around the chip and the bonding wire via an adhesive layer, and the dam. In the method for manufacturing a hybrid integrated circuit board, the dam layer includes a protective resin layer provided on the main body surrounded by a layer and a protective resin layer provided to seal the chip and wires, wherein the dam layer is a frame material for forming a dam layer. is formed around the chip and the bonding wire via an adhesive made of the same material as the protective resin layer, and then cured to infiltrate the resin constituting a part of the adhesive into the dam layer forming frame material. A method of manufacturing a hybrid integrated circuit board, comprising: forming a hybrid integrated circuit board by forming a hybrid integrated circuit board;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3091680A JP2902497B2 (en) | 1991-03-29 | 1991-03-29 | Manufacturing method of hybrid integrated circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3091680A JP2902497B2 (en) | 1991-03-29 | 1991-03-29 | Manufacturing method of hybrid integrated circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04302457A true JPH04302457A (en) | 1992-10-26 |
| JP2902497B2 JP2902497B2 (en) | 1999-06-07 |
Family
ID=14033208
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3091680A Expired - Lifetime JP2902497B2 (en) | 1991-03-29 | 1991-03-29 | Manufacturing method of hybrid integrated circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2902497B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5610737A (en) * | 1994-03-07 | 1997-03-11 | Kabushiki Kaisha Toshiba | Thin film transistor with source and drain regions having two semiconductor layers, one being fine crystalline silicon |
| NL1004651C2 (en) * | 1996-11-29 | 1998-06-03 | Nedcard | Method for encapsulating a chip on a support. |
| US6459144B1 (en) * | 2001-03-02 | 2002-10-01 | Siliconware Precision Industries Co., Ltd. | Flip chip semiconductor package |
| US6731001B2 (en) | 2000-08-10 | 2004-05-04 | Denso Corporation | Semiconductor device including bonded wire based to electronic part and method for manufacturing the same |
-
1991
- 1991-03-29 JP JP3091680A patent/JP2902497B2/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5610737A (en) * | 1994-03-07 | 1997-03-11 | Kabushiki Kaisha Toshiba | Thin film transistor with source and drain regions having two semiconductor layers, one being fine crystalline silicon |
| NL1004651C2 (en) * | 1996-11-29 | 1998-06-03 | Nedcard | Method for encapsulating a chip on a support. |
| WO1998023427A1 (en) * | 1996-11-29 | 1998-06-04 | Nedcard | Method for encapsulating a chip on a carrier |
| US6731001B2 (en) | 2000-08-10 | 2004-05-04 | Denso Corporation | Semiconductor device including bonded wire based to electronic part and method for manufacturing the same |
| US6459144B1 (en) * | 2001-03-02 | 2002-10-01 | Siliconware Precision Industries Co., Ltd. | Flip chip semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2902497B2 (en) | 1999-06-07 |
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