JPS6038845A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6038845A
JPS6038845A JP58147736A JP14773683A JPS6038845A JP S6038845 A JPS6038845 A JP S6038845A JP 58147736 A JP58147736 A JP 58147736A JP 14773683 A JP14773683 A JP 14773683A JP S6038845 A JPS6038845 A JP S6038845A
Authority
JP
Japan
Prior art keywords
semiconductor element
package
substrate
solder
electrical connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58147736A
Other languages
Japanese (ja)
Inventor
Eiji Ono
鋭二 大野
Tomio Ishida
石田　富雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58147736A priority Critical patent/JPS6038845A/en
Publication of JPS6038845A publication Critical patent/JPS6038845A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To execute an electrical connection with a substrate of a package for a semiconductor element and an internal sealing simultaneously by forming two projecting sections of an electrical connecting section and a connecting section for sealing on the same plane of the end surface of an opening in the package and loading the package onto the substrate with a conductor wire corresponding to the electrical connecting section. CONSTITUTION:Two projecting sections 10a, 10b are formed to the end surface of an opening functioning as a joining section with a substrate 14 of a package 10 for a semiconductor element. Conductor wires 11 connected to the semiconductor element 3 on the inside are formed to the external projecting section 10a, and solder 12 is padded onto the wires 11. Epoxy resin 13, a thermosetting temperature thereof is higher than the melting point of solder 12, as adhesives is attached to the internal projecting section 10b. When the package 10 is heated and pressed and loaded so as to cover the semiconductor element 15 fitted onto the alumina substrate 14 with conductor wires 16a at positions corresponding to solder 12, the package also functions as a ceramic cap.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体素子を使用する電子回路全般に用いるこ
とができる半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device that can be used in general electronic circuits using semiconductor elements.

従来例の構成とその問題点 近年、電子機器の小型化が進み、半導体素子の高密度実
装が計られており、その半導体素子の保護のために、し
ばしばチップキャリアタイプパ、。Conventional configurations and their problems In recent years, electronic devices have become smaller and semiconductor elements are being mounted in higher density.In order to protect the semiconductor elements, chip carrier types are often used.

ケージが用いられている。cage is used.

以下図面を参照しながら、従来のチップキャリアタイプ
パッケージについて説明する。第１図は従来のチップキ
ャリアタイプパッケージを示す。A conventional chip carrier type package will be described below with reference to the drawings. FIG. 1 shows a conventional chip carrier type package.

第１図において１はセラミックよりなるパリケージ、２
はパッケージ内部と外部を結ぶ導体線、３は半導体素子
、４は前記半導体素子３を保護する蓋である。従来のチ
ップキャリアタイプパッケージは、第２図に示すように
導体線２と基板γ上の導体線６をハンダ５により接続す
ることにより、基板上に搭載される。In Fig. 1, 1 is a pari cage made of ceramic;
3 is a conductor wire connecting the inside and outside of the package, 3 is a semiconductor element, and 4 is a lid that protects the semiconductor element 3. A conventional chip carrier type package is mounted on a substrate by connecting the conductor wire 2 and the conductor wire 6 on the substrate γ with solder 5, as shown in FIG.

しかしながら、このような構造では、蓋４を取り付ける
工程と基板にチップキャリアタイプのパッケージを取シ
付ける工程が必要で、作業能率が悪いという欠点を有し
ている。However, such a structure requires a process of attaching the lid 4 and a process of attaching a chip carrier type package to the substrate, which has the disadvantage of poor work efficiency.

発明の目的 本発明はこのような従来の欠点を除去するものであり、
作業能率の向上を実現することを目的とするものである
。OBJECTS OF THE INVENTION The present invention obviates these conventional drawbacks,
The purpose is to improve work efficiency.

発明の構成 この目的を達成するために本発明の半導体装置は、半導
体素子用パッケージの開口端面の同一平面上に電気的接
続部と封止用接続部の２つの凸部を設けるとともに内部
に半導体素子を設置し、かつその半導体素子用パッケー
ジを、前記電気的接続部に対応する導体線を有する基板
上に塔載し、前記電気的接続部と導体線を接続するとと
もに、封止用接続部を基板に密着させて半導体素子用パ
ッケージを封止したものである。Structure of the Invention In order to achieve this object, the semiconductor device of the present invention provides two convex portions, an electrical connection portion and a sealing connection portion, on the same plane of the open end surface of a semiconductor element package, and has a semiconductor device inside. The device is installed, and the package for the semiconductor device is mounted on a substrate having a conductor wire corresponding to the electrical connection portion, and the electrical connection portion and the conductor wire are connected, and a sealing connection portion is installed. A semiconductor element package is sealed by bringing the semiconductor element into close contact with a substrate.

実施例の説明 以下、本発明の実施例を図面を参照しながら説明する。Description of examples Embodiments of the present invention will be described below with reference to the drawings.

第３図に本発明の半導体装置において、半導体素子用パ
ッケージの内部に半導体素子を設置した様子を示してお
り、前記半導体素子用パックー７１０の基板との接合部
となる開１」端面に、２つの凸部１０　ａ　、　１０　
ｂを設ける。１１■記凸部１０　ａ　、　１０　ｂのう
ちの外側の凸部１０　ａには、内部の半導体素子３と接
続される導体線１１が形成され、その上にハンダ１２が
もられでいる。また、内側の凸部１ｏｂＫは、接着剤で
あるエポキシ樹脂１３が設けられている。前記エポキシ
樹脂１３は、熱硬化温度が前記ハンダ１２の融点よりも
高いものを用いる。前記半導体素子３を設置した半導体
素子用パッケージ１ｏは、加熱・加圧によりアルミナ基
板に接続する。接続部の前記二つの凸部１ｏａ、１ｏｂ
の間の溝は、接続時にハンダ１２とエポキシ樹脂１３が
接触しないだめのものである。FIG. 3 shows a state in which a semiconductor element is installed inside a semiconductor element package in the semiconductor device of the present invention. Two convex portions 10a, 10
b. A conductor wire 11 connected to the internal semiconductor element 3 is formed on the outer convex portion 10 a of the convex portions 10 a and 10 b described in 11.1, and a solder 12 is spread thereon. Further, the inner convex portion 1obK is provided with an epoxy resin 13 which is an adhesive. The epoxy resin 13 used has a thermosetting temperature higher than the melting point of the solder 12. The semiconductor element package 1o in which the semiconductor element 3 is installed is connected to an alumina substrate by heating and pressurizing. The two convex portions 1oa and 1ob of the connection portion
The groove between them prevents the solder 12 and the epoxy resin 13 from coming into contact with each other during connection.

第４図は第３図の半導体素子用パッケージ１０をアルミ
ナ基板１４上に設置した半導体素子１５を被うように設
置した例であり、セラミックキャップとしての働きも兼
ねている。第４図において、１６ａ、１６ｂは導体線、
１７は導体線１６ａ。FIG. 4 shows an example in which the semiconductor element package 10 of FIG. 3 is installed so as to cover the semiconductor element 15 placed on the alumina substrate 14, and also functions as a ceramic cap. In FIG. 4, 16a and 16b are conductor wires,
17 is a conductor wire 16a.

１６ｂを絶縁するだめの絶縁層である。This is an insulating layer for insulating the layer 16b.

なお、本実施例では接続部の二つの凸部１０ａ。In addition, in this embodiment, there are two protrusions 10a of the connection part.

１ｏｂのうぢ、外側の凸部１０　ａに２・ンダ１２を、
内側の凸部１０ｂにエポキシ樹脂１３を設置しだが、導
体線１１の配線を半導体素子用ノ＜ツケージ１ｏの内側
に施し、内側の凸部１０ｂにノ・ンダ１２を、外側の凸
部１０　ａにエポキシ樹脂１３を設置してもよいＯまだ
、半導体素子用ノ＜・ノケージ１０ど基板を接続するだ
めの加熱時におけるノ・ンダの酸化を防止するだめに、
非酸化性算量気中で接続してもよい０また、本実施例で
は、第３図の半導体素子用パッケージ１０をアルミナ基
板１４上に設置した半導体素子１５を被うように設置し
たが、半導体素子１５の代りに他の能動素子および受動
素子を設置してもよいし、アルミナ基板１４上に導体線
１６ａのみを設置し、半導体装置内部は半導体素子３の
みとしてもよい０ 発明の効果 以上のように本発明では、半導体素子用ノくツケージの
基板との電気的接続と内部封止が同時に行なえるため、
作業能率が向上し、まだ第４図に示したように、複数個
の半導体素子や他の能動素子・受動素子を簡単な構造に
より高密度に実装することができる。1ob, put 2nd 12 on the outer convex part 10a,
The epoxy resin 13 is installed on the inner protrusion 10b, and the wiring of the conductor wire 11 is applied to the inside of the semiconductor element cage 1o, and the solder 12 is placed on the inner protrusion 10b, and the outer protrusion 10a is coated with the epoxy resin 13. Epoxy resin 13 may be placed on the epoxy resin 13 to prevent oxidation of the cage 10 for semiconductor devices and other substrates during heating.
In addition, in this embodiment, the semiconductor element package 10 shown in FIG. 3 was placed so as to cover the semiconductor element 15 placed on the alumina substrate 14. Other active elements and passive elements may be installed in place of the semiconductor element 15, or only the conductor wire 16a may be installed on the alumina substrate 14, and only the semiconductor element 3 may be placed inside the semiconductor device. As shown in the figure, in the present invention, electrical connection with the substrate of the semiconductor chip cage and internal sealing can be performed at the same time.
Work efficiency is improved, and as shown in FIG. 4, a plurality of semiconductor elements and other active/passive elements can be mounted at high density with a simple structure.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のチップキャリアタイプパリケージに半導
体素子を設置した例を示す断面図、第２図は従来のチッ
プキャリアタイプパッケージを基板上に塔載した例を示
す断面図、第３図は本発明に使用する半導体素子用パッ
ケージの内部に半導体素子を設置した例を示す断面図、
第４図は本発明による半導体装置の一例を示す断面図で
ある。 ３．１５・・・・・・半導体素子、１０・・・・・・半
導体素子用パッケージ、Ｉ　Ｑ　ａ　、　１０　ｂ・・
・・・・凸部、１２・・・・・・ハンダ、１３・・・・
・・エポキシ樹脂、１４・・・・・・アルミナ基板、１
６ａ、１６ｂ・・・・・導体線。 代理人の氏名　弁理士　中　尾　敏　男　ほか１名第１
図 ４３ 第３図 第４図Fig. 1 is a sectional view showing an example of a conventional chip carrier type package in which a semiconductor element is installed, Fig. 2 is a sectional view showing an example of a conventional chip carrier type package mounted on a substrate, and Fig. 3 is a sectional view showing an example of a conventional chip carrier type package mounted on a substrate. A sectional view showing an example in which a semiconductor element is installed inside a semiconductor element package used in the present invention,
FIG. 4 is a sectional view showing an example of a semiconductor device according to the present invention. 3.15... Semiconductor element, 10... Package for semiconductor element, I Q a, 10 b...
...Protrusion, 12...Solder, 13...
...Epoxy resin, 14...Alumina substrate, 1
6a, 16b... Conductor wire. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 43 Figure 3 Figure 4

Claims (2)

【特許請求の範囲】[Claims] （１）半導体素子用パッケージの開口端面（７）同一平
面上に電気的接続部と封止用接続部の２つの凸部を設け
るとともに、内部に半導体素子を設置し、かつその半導
体素子用パッケージを前記電気的接続部に対応する導体
線を有する基板上に塔載し、前記電気的接続部と導体線
を接続するとともに、封止用接続部を基板に密着させて
半導体素子用パッケージを封止した半導体装置。(1) Opening end face of a semiconductor element package (7) Two convex parts, an electrical connection part and a sealing connection part, are provided on the same plane, a semiconductor element is installed inside, and the semiconductor element package is is mounted on a substrate having conductor wires corresponding to the electrical connection portions, the electrical connection portions and the conductor wires are connected, and the sealing connection portions are brought into close contact with the substrate to seal the semiconductor element package. A stopped semiconductor device. （２）電気的接続部と導体線との接続にハンダを用い、
封止用接続部と基板との接着に熱硬化型樹脂を用い、前
記ハンダの融点を前記熱硬化型樹脂の硬化温度よりも低
くした特許請求の範囲第１項に記載の半導体装置。(2) Using solder to connect the electrical connection part and the conductor wire,
2. The semiconductor device according to claim 1, wherein a thermosetting resin is used to bond the sealing connection portion and the substrate, and the melting point of the solder is lower than the curing temperature of the thermosetting resin.
JP58147736A 1983-08-11 1983-08-11 Semiconductor device Pending JPS6038845A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58147736A JPS6038845A (en) 1983-08-11 1983-08-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58147736A JPS6038845A (en) 1983-08-11 1983-08-11 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6038845A true JPS6038845A (en) 1985-02-28

Family

ID=15436977

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58147736A Pending JPS6038845A (en) 1983-08-11 1983-08-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6038845A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6388675U (en) * 1986-11-27 1988-06-09
US4816896A (en) * 1988-02-01 1989-03-28 Motorola Inc. Compliant standoff for semiconductor packages
US5065277A (en) * 1990-07-13 1991-11-12 Sun Microsystems, Inc. Three dimensional packaging arrangement for computer systems and the like

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6388675U (en) * 1986-11-27 1988-06-09
JPH0435343Y2 (en) * 1986-11-27 1992-08-21
US4816896A (en) * 1988-02-01 1989-03-28 Motorola Inc. Compliant standoff for semiconductor packages
US5065277A (en) * 1990-07-13 1991-11-12 Sun Microsystems, Inc. Three dimensional packaging arrangement for computer systems and the like

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