JPS6129155B2 - - Google Patents

Info

Publication number
JPS6129155B2
JPS6129155B2 JP56124870A JP12487081A JPS6129155B2 JP S6129155 B2 JPS6129155 B2 JP S6129155B2 JP 56124870 A JP56124870 A JP 56124870A JP 12487081 A JP12487081 A JP 12487081A JP S6129155 B2 JPS6129155 B2 JP S6129155B2
Authority
JP
Japan
Prior art keywords
metal layer
electrode
common electrode
input
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56124870A
Other languages
English (en)
Other versions
JPS5756953A (en
Inventor
Shinzo Anazawa
Seiichi Ueno
Isamu Nagameguri
Tadashi Nawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP56124870A priority Critical patent/JPS5756953A/ja
Publication of JPS5756953A publication Critical patent/JPS5756953A/ja
Publication of JPS6129155B2 publication Critical patent/JPS6129155B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6644—Packaging aspects of high-frequency amplifiers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

【発明の詳細な説明】 本発明は、トランジスタに関するもので、特に
超高周波帯において安定に動作する電界効果型ト
ランジスタの構成に適する様にしたものである。
超高周波帯の半導体装置の電気的特性及び信頼性
は半導体素子をマウントする容器の構造及び構成
部材の材質等により大きい影響をうける。特にカ
リウム砒素を基体とした電界効果型トランジスタ
に於いてはゲートとドレイン間の容量、ソースと
アース端子間のインダクタンスが重要な問題であ
るので半導体容器の構造、材質を充分吟味しなけ
ればならない。
従来の超高周波帯の電界効果型トランジスタは
第１図に示す如くセラミツク基板１の表裏にメタ
ライズにより導電体２，２′，２″，２を配し
て、ストリツプラインを構成し、導電体２′上に
半導体素子３をマウントし半導体３の各電極、即
ちゲート、ドレイン、ソース電極と導電体２，
２′，２″，２との間を夫々金属細線４，４′，
４″で電気的に接続し導電体２′よりソース電極
を、導電体２″より例えばゲート電極を、導電体
２より例えばドレイン電極を導出する如き構成
である。しかしこの構成によれば素子３のマウン
ト近辺の寄生リアクタンス成分の影響が大きく又
周波数が高くなるにつれて異常発振を起し易く
又、素子自体の発熱によつて電気的特性が加速的
に悪くなる等、満足すべき電界効果型トランジス
タは得られない。
本発明の目的はこれ等の該欠点を解決したトラ
ンジスタを提供する事にある。
本発明ではトランジスタを誘電体基板上に載置
し、このトランジスタの共通電極は誘電体基板に
設けられたスルーホールを介して、該基板の裏面
導体層と電気的に接続する様にしたものである。
以下本発明の一実施例を図面について詳細に説
明する。
第２図は本発明の基本的実施例を示し、この例
ではストリツプラインを構成するための絶縁基板
１として熱伝導度がよく、且つ低誘電率のベリリ
アセラミツク又はアルミナセラミツクを用い（こ
れの熱伝導度は鋼のそれと略々等しい）。またト
ランジスタとして電界効果トランジスタを用い
る。この絶縁基板１の裏面にはストリツプライン
を構成する共通導体２（この時接地用）を例えば
メタライズにより被着形成し、表面にはドレイン
とゲート電極の導出端子として用いられ、接地導
体２と対向してストリツプラインを構成する出力
用および入力用メタライズ層２″，２を形成す
ると共に共通導体としてソース電極用メタライズ
層２′を形成し、ソース電極用メタライズ層２′と
接地導体２との間をスルーホール５を通じて接続
し、ソース電極用メタライズ層２′をストリツプ
ラインの接地導体と同電位となし、この接地導体
と同電位となされたソース電極用メタライズ層
２′上に電界効果型トランジスタを構成する半導
体素子３をマウントし、半導体素子３のソース電
極を金属細線又は金属テープ４にてメタライズ層
２′に接続し、ゲート電極とドレイン電極も同様
に金属細線又は金属テープ４′及び４″にてメタラ
イズ層２″及び２に夫々接続する様になす。ス
ルーホール５は半導体素子３のソース電極と可及
的に近くなる様な位置に設置する。尚１０は外部
導出リード線である。
この様に構成する事によつて絶縁基板１が低誘
電率であるを以つてゲートソース間；ドレイン−
ソース間及びゲート−ドレイン間の静電容量を小
さくでき、然もソース電極はストリツプラインを
構成する接地導体２よりスルーホール５を通じて
導出する様にしたから接地までの距離を短かくで
きソースと接地間のリアクタンス成分を減少させ
る事ができる。従つて寄生リアクタンス成分の減
少と、熱放散の向上が期待でき超高周波域におけ
る動作を安定化する事ができる。
更に、接地インダクタンスを減少させるための
構造として、スルーホール５による結合を行なつ
ているので、誘電体基板１自体の表面及び裏面の
平担性は何等阻害されることはない。従つて、超
高周波用の微細なトランジスタチツプ２をマウン
トする際に平担な面にマウントでき、かつその後
のボンデイング接続時の圧力は基板表面に凹凸が
ないために均一な圧力となつて基板に伝達され、
局部的な圧力集中も生じない。この結果、耐機械
力についても優れた装置となる。又、その製造に
おいても基板成形時にスルーホールを形成出来、
その内部への金属導入も簡単なため、製造工程を
複雑化させることもない。
【図面の簡単な説明】
第１図は従来のストリツプライン型半導体容器
を示す斜視図、第２図は本発明の基本的実施例を
示す断面図である。 １：絶縁基板、２，２′，２″，２：ストリツ
プラインを構成するメタリツク層、３：半導体素
子、４：金属細線、６：ストリツプラインの接地
導体を構成する金属スタツド、７：補助スタツ
ド。

Claims (1)

    【特許請求の範囲】
  1. １ 表面に入力用金属層、出力用金属層及び第１
    の共通電極用金属層をそれぞれ分離して有する誘
    電体基板と、前記誘電体基板の裏面の全面に設け
    られた第２の共通電極用金属層と、前記第１と第
    ２の共通電極用金属層間の前記誘電体基板を貫通
    する複数の貫通孔と、該貫通孔に充填されて前記
    第１と第２の共通電極用金属層を電気的に接続す
    るスルーホール金属層と、前記第１の共通電極用
    金属層上に取り付けられた入力電極と出力電極と
    共通電極とを有するトランジスタ素子と、該トラ
    ンジスタ素子の前記入力電極を前記入力用金属層
    に、前記出力電極を前記出力用金属層に、前記共
    通電極を前記第１の共通電極用金属層にそれぞれ
    接続する手段とを有することを特徴とするトラン
    ジスタ。
JP56124870A 1981-08-10 1981-08-10 Transistor Granted JPS5756953A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56124870A JPS5756953A (en) 1981-08-10 1981-08-10 Transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56124870A JPS5756953A (en) 1981-08-10 1981-08-10 Transistor

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP48105715A Division JPS5910075B2 (ja) 1973-09-19 1973-09-19 電界効果型トランジスタ

Publications (2)

Publication Number Publication Date
JPS5756953A JPS5756953A (en) 1982-04-05
JPS6129155B2 true JPS6129155B2 (ja) 1986-07-04

Family

ID=14896131

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56124870A Granted JPS5756953A (en) 1981-08-10 1981-08-10 Transistor

Country Status (1)

Country Link
JP (1) JPS5756953A (ja)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0799753B2 (ja) * 1985-11-06 1995-10-25 日本電気株式会社 混成集積回路
DE3777856D1 (de) * 1986-02-24 1992-05-07 Hewlett Packard Co Hermetische, mikroelektronische hochfrequenzpackung fuer oberflaechenmontage.
US4839717A (en) * 1986-12-19 1989-06-13 Fairchild Semiconductor Corporation Ceramic package for high frequency semiconductor devices
FR2629271B1 (fr) * 1988-03-25 1991-03-29 Thomson Hybrides Microondes Dispositif d'interconnexion et de protection d'une pastille nue de composant hyperfrequence
CA2096008A1 (en) * 1990-11-19 1992-05-20 Joseph M. Ommen Microelectronics package

Also Published As

Publication number Publication date
JPS5756953A (en) 1982-04-05

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