JPS61288447A - Semiconductor element mounting substrate - Google Patents

Semiconductor element mounting substrate

Info

Publication number
JPS61288447A
JPS61288447A JP13127785A JP13127785A JPS61288447A JP S61288447 A JPS61288447 A JP S61288447A JP 13127785 A JP13127785 A JP 13127785A JP 13127785 A JP13127785 A JP 13127785A JP S61288447 A JPS61288447 A JP S61288447A
Authority
JP
Japan
Prior art keywords
substrate
coating layer
thick film
semiconductor element
glass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13127785A
Other languages
Japanese (ja)
Inventor
Akira Otsuka
昭 大塚
Masanori Tsujioka
正憲 辻岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP13127785A priority Critical patent/JPS61288447A/en
Publication of JPS61288447A publication Critical patent/JPS61288447A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481Insulating layers on insulating parts, with or without metallisation

Abstract

PURPOSE:To make it possible to apply thick film pastes and a glass film on the surface of an AlN substrate by a method wherein a coating layer consisting of a substance to be chosen from among an SiO2, an Al2O3, an MgO and a diamond is provided on the surface of the substrate. CONSTITUTION:A coating layer 2 consisting of some of an SiO2, an Al2O3, an MgO and a diamond or the mixture of these substances is formed on the surface of an AlN substrate 1. There is no limitation specially to the forming method for the coating layer 2, but such a method as a vapor-phase reaction method, a plasma CVD method and a PVD method is desirable in point of being able to form the coating layer with a favorable adhesion with the AlN substrate with good productivity efficiency. The circuits are formed on the substrate, whereon the coating layer is obtained in such a way, using thick film pastes 3 and a sealing glass film 6 is adhered on the sealing part. Lastly semiconductor elements 4 are connected to the prescribed positions on the circuits using element bonding materials 5. The covering layer 2 can be formed on the whole or part only of the surface of the substrate 1 according to need. The coating layer 2 has an electrical resistance, and moreover, has a good leakage property into the thick film pastes and the glass film. Accordingly the thick film pastes for circuit formation and the glass film for sealing can be applied on the coating layer 2 of the substrate by a screen printing and so forth.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体素子を塔載するための基板1特に放熱特
性が良好で且つ厚膜ペーストの塗布性及び低融点ガラス
等によるガラス封止性を改善した基板に関する。
Detailed Description of the Invention [Industrial Field of Application] The present invention provides a substrate 1 for mounting semiconductor elements, particularly a substrate 1 having good heat dissipation properties, coatability of thick film paste, and glass sealability with low melting point glass or the like. This invention relates to a board with improved characteristics.

〔従来の技術〕[Conventional technology]

一般に半導体素子搭載用基板は、必要に応じてその表面
に導体ペーストで回路を描き、所定位置に半導体素子を
ろう付けし又は接着用ペースト剤により接着し、最後に
樹脂、ガラス又はろう材で  ゛気密封止される。この
ため、基板に要求される特性は、半導体素子であるSl
と熱膨張係数が一致することが重要であったが、近年半
導1体素子の高密度化や高電力化が進むなかで、素子に
発生するジュール熱を有効に除去するための放熱特性も
又重要になっている。
Generally, a circuit board for mounting a semiconductor element is prepared by drawing a circuit on its surface with conductive paste as necessary, brazing the semiconductor element in a predetermined position or adhering it with an adhesive paste, and finally using resin, glass, or brazing material. Hermetically sealed. Therefore, the characteristics required for the substrate are as follows:
It was important that the coefficients of thermal expansion and the thermal expansion coefficients matched, but in recent years, as single-piece semiconductor devices have become denser and have higher power, the heat dissipation characteristics to effectively remove the Joule heat generated in the devices have also become important. It has become important again.

従来、基板材料にはAlOが多く用いられておす、半導
体素子が小型でA40  との熱膨張係数の差により生
じる応力が小さい場合には問題がなかった。しかし、半
導体素子が大型化すると、A10と81との熱膨張係数
に下記の表1に示す通り、2.7X10/l:の差があ
るため、この差により生じる応力が大きくなり、素子の
剥離や破壊が生じる。
Conventionally, AlO was often used as a substrate material, and there was no problem when the semiconductor element was small and the stress caused by the difference in thermal expansion coefficient with A40 was small. However, as semiconductor devices become larger, the thermal expansion coefficients of A10 and A81 differ by 2.7X10/l, as shown in Table 1 below, so the stress caused by this difference increases, causing the devices to peel off. or destruction will occur.

又、放熱特性の点からも、Aj0 は熱伝導度が表1に
示す通り極めて低いために基板材料として有効とは云え
ず、素子に発生するジュール熱が大きい場合には、Cu
やAjのヒートシンクを取付ける等の工夫が為されてい
る。
Also, from the point of view of heat dissipation characteristics, Aj0 has extremely low thermal conductivity as shown in Table 1, so it cannot be said to be effective as a substrate material, and if the Joule heat generated in the device is large, Cu
Efforts have been made, such as installing heat sinks such as and Aj.

表    1 そこで、熱膨張係数が81に近似し、且つ熱伝導度の良
い基板材料として表1に示すAINが提案され、一部で
利用されている。しかし、AINは厚膜ペーストやガラ
スとの濡れ性が悪く、その実用範囲が限定されていた。
Table 1 Therefore, AIN shown in Table 1 has been proposed as a substrate material with a thermal expansion coefficient close to 81 and good thermal conductivity, and has been used in some cases. However, AIN has poor wettability with thick film pastes and glass, and its practical range has been limited.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

本発明はSlと熱膨張係数が近似し且つ放熱特性の良い
klNを用いて、その表面への厚膜ペースト及びガラス
の塗布が可能な半導体素子塔載用基板を提供するもので
ある。
The present invention uses klN, which has a coefficient of thermal expansion similar to that of Sl and has good heat dissipation properties, to provide a substrate for mounting a semiconductor element on the surface of which a thick film paste and glass can be applied.

C問題点を解決するための手段〕 本発明の半導体素子搭載用基板は、A4N基体の表面の
少なくとも一部に、S10、AlO1Mgo及びダイヤ
モンドからなるグループから選ばれた少なくとも一つの
物質よりなる被覆層を有することを特徴とする。   
 ゛ 被覆層の厚さは0.1〜20μmが好ましい。この厚さ
が0.1μm未満では厚膜ペーストやガラスの塗布及び
付着が不充分であり、逆に20μmを超えると被覆層自
体が熱放散のバリヤとなってAINの優れた放熱特性が
発揮できず、被覆層とA4Nとの熱膨張係数の差によっ
て被覆層に剥離や破壊が発生しやすい。
Means for Solving Problem C] The substrate for mounting a semiconductor element of the present invention has a coating layer made of at least one substance selected from the group consisting of S10, AlO1Mgo, and diamond on at least a part of the surface of the A4N base. It is characterized by having the following.
``The thickness of the coating layer is preferably 0.1 to 20 μm. If this thickness is less than 0.1 μm, the coating and adhesion of the thick film paste or glass will be insufficient, and if it exceeds 20 μm, the coating layer itself will act as a barrier to heat dissipation, making it impossible for AIN to exhibit its excellent heat dissipation properties. First, the coating layer is likely to peel or break due to the difference in thermal expansion coefficient between the coating layer and A4N.

次に、図面に基ずいて本発明の半導体素子塔載用基板を
説明する。通常の方法で所定の形状に形成されたAlN
基体1の表面にS10、Al01Mg0及びダイヤモン
ドのいずれか又はこれらの混合物からなる被覆層2を形
成する。被覆層2の形成方法については特に制限はない
が、例えば気相反応法(avD法: OhemicaJ
 Vapor Deposition ) 、プラズマ
OVD法、PVD  (Phya土cal V’apo
r Deposit−1on)法dどが、AlN基体と
の密着性の良好な被覆層を生産性良く形成できる点で好
ましい。このようにして得られた本発明の基板上には、
厚膜ペースト3により回路を形成し、封止部に封止用ガ
ラス6を付着させる。最後に、回路上の所定位置に素子
接合材料5を用いて半導体素子4を接続する。なお、被
覆層2は必要に応じて基体1の表面の全部に又は表面の
一部のみに形成しても良い。
Next, the semiconductor element mounting substrate of the present invention will be explained based on the drawings. AlN formed into a predetermined shape by a normal method
A coating layer 2 made of any one of S10, Al01Mg0, and diamond or a mixture thereof is formed on the surface of the substrate 1. There are no particular restrictions on the method of forming the coating layer 2, but for example, a vapor phase reaction method (avD method: OhmicaJ
Vapor Deposition), plasma OVD method, PVD (Phya soil cal V'apo
The Deposit-1on) method is preferred in that it can form a coating layer with good adhesion to the AlN substrate with high productivity. On the substrate of the present invention obtained in this way,
A circuit is formed using the thick film paste 3, and a sealing glass 6 is attached to the sealing portion. Finally, the semiconductor element 4 is connected to a predetermined position on the circuit using the element bonding material 5. Note that the coating layer 2 may be formed on the entire surface of the substrate 1 or only on a part of the surface, if necessary.

〔作用〕[Effect]

本発明において被覆層を構成するSio 、At o 
、Mg0又はダイヤモンドは電気絶縁性を有し、しかも
厚膜ペースト及びガラスとの濡れ性が良い。
In the present invention, Sio and Ato constituting the coating layer
, Mg0 or diamond have electrical insulation properties and also have good wettability with thick film pastes and glass.

従って、基板の被覆層上にはスクリーン印刷等により回
路形成用の厚膜ペーストや封止用のガラスを塗布するこ
とが可能である。しかも、この被覆層は厚さが20μm
以下であれば、半導体素子に発生するジュール熱のAl
N基体からの放散を妨害しない。
Therefore, it is possible to apply a thick film paste for circuit formation or glass for sealing onto the coating layer of the substrate by screen printing or the like. Moreover, this coating layer has a thickness of 20 μm.
If it is below, the Joule heat generated in the semiconductor element is
Does not interfere with dissipation from the N substrate.

〔実施例〕〔Example〕

次に、実施例によって本発明を更に詳しく説明する。 Next, the present invention will be explained in more detail with reference to Examples.

実施例I AlN基体上にイオンブレーティング法によってAIO
の被覆層を形成して、ハイブリッドエC用基板を製造し
た。
Example I AIO was deposited on an AlN substrate by ion blating method.
A covering layer was formed to produce a Hybrid E-C substrate.

まず40鴎角、厚さQ、5mmのAlN基体を準備し−
これを予め2001:’に加熱し、真空容器中にセット
した。被覆層原料としてAlo 焼結体を用い1酸素工
・力5 X 10−’torrのもとて電子ビーム加熱
によりAA Oを蒸発させ、高周波コイルに13.56
 MHzの高周波を100Wにて印加して蒸発kl O
の一部をイオン化し、A4N基体表面に厚さ2.0μm
の密着性の良いAt O被N層を形成した。
First, prepare an AlN substrate with a diameter of 40 mm, a thickness of Q, and 5 mm.
This was preheated to 2001:' and set in a vacuum container. Using an Alo sintered body as the raw material for the coating layer, AAO was evaporated by electron beam heating under 1 oxygen pressure and a force of 5 x 10-'torr, and a high-frequency coil was heated at 13.56 mm.
Evaporate klO by applying MHz high frequency at 100W.
2.0 μm thick on the surface of the A4N substrate.
A N-coated layer with good adhesion was formed.

得られたハイブリッドTC用基板上に、スクリーン印刷
法でAgペーストを厚さ12μmに塗布し、560Cで
10分間大気中で焼成したところ、Agペーストとkl
 O被覆層との密着性の良好なバイブリツドエC用基板
が得られた。
On the obtained hybrid TC substrate, Ag paste was applied to a thickness of 12 μm by screen printing method and baked at 560C for 10 minutes in the air.
A substrate for hybrid E-C with good adhesion to the O coating layer was obtained.

実施例2 AlN基体上にプラズマOVD法によってAl Oの被
覆層を形成して、ガラス封止型パッケージ用基板を製造
した。
Example 2 A glass-sealed package substrate was manufactured by forming an Al 2 O coating layer on an AlN substrate by plasma OVD.

20關角、厚さQ、Qmmで中央に6間角、深さ0.3
簡の四部をもつAIN基体を反応室にセットし、A、/
C+7 、 co  及びHの混合ガスを用い全ガス圧
1.5torrで基体上にA40  を気相成長させた
。この時、反応室をsoo t:”に加熱し、13.5
6 MHzの高周波を300Wにて印加した。得られた
Al2O3被覆層は厚さ3.0μmであり、A/N基体
への密着性も良好であった。
20 angles, thickness Q, Qmm, 6 angles in the center, depth 0.3
Set the AIN substrate with four parts in the reaction chamber, A, /
A40 was vapor-phase grown on the substrate using a mixed gas of C+7, co and H at a total gas pressure of 1.5 torr. At this time, the reaction chamber was heated to 13.5
A high frequency of 6 MHz was applied at 300W. The resulting Al2O3 coating layer had a thickness of 3.0 μm and had good adhesion to the A/N substrate.

得られたガラス封止型パッケージ基板の凹部にドツティ
ング法によりAuペーストを滴下し、850Cで10分
間大気中で焼成した。次に、四部の外周にスクリーン印
刷法によって低融点ガラスを塗′ 布し、450Cで1
0分間大気中で焼成した。その後、リード先端部にAl
を蒸着した42%Ni −Feリードフレームを上記ガ
ラス部に4800で接着した。
Au paste was dropped into the concave portions of the obtained glass-sealed package substrate by a dotting method, and fired at 850C for 10 minutes in the air. Next, apply low melting point glass to the outer periphery of the four parts by screen printing method, and heat at 450C for 1 hour.
It was baked in the air for 0 minutes. After that, Al was applied to the lead tip.
A 42% Ni-Fe lead frame on which was vapor-deposited was bonded to the glass part with 4800.

この様にして得られたガラス封止型パッケージのAu部
に半導体素子をAu−3i共晶法で接着し、リードと半
導体素子の電極とをAtワイヤーボンディングした。最
後に、ガラスを塗布したA40  板とこのパッケージ
とを5000で気密封止した。気密封止後、所定のヒー
トサイクルのプレッシャークツカーテストを実施して、
ガラスとAl2O3被覆層1AIO被覆層とA4N基体
の間のり−り量を測定した結果、リークは全く無く充分
な気密封止が得られたことが判った。
A semiconductor element was bonded to the Au portion of the glass-sealed package obtained in this manner by the Au-3i eutectic method, and the leads and electrodes of the semiconductor element were bonded with At wire. Finally, the A40 plate coated with glass and this package were hermetically sealed with 5000mm. After hermetically sealing, a predetermined heat cycle pressure test is carried out.
As a result of measuring the amount of adhesion between the glass, the Al2O3 coating layer 1AIO coating layer, and the A4N substrate, it was found that there was no leakage at all and a sufficient hermetic seal was obtained.

実施例3 AIN基体上に高周波スパッタリング法によって、Aj
!O,MgO及びSiOの混合物を被覆して、半導′休
素子搭載用基板を製造した。
Example 3 Aj
! A substrate for mounting a semiconductor element was manufactured by coating with a mixture of O, MgO and SiO.

まず予めターゲットとして、MgO及びSiO□を埋め
込んだAt Oターゲットをセットしたスパッタリング
容器内に2インチ角、厚さ1 amのAIN基体を試料
ホルダーに固定した。次に、スパッタリング容器内をI
 X 1O−6torrに引くと共に、AjN基体を2
000に加熱し、Arガスをガス圧5X10torrま
で導入し、ターゲットに13.56MHzの高周波を1
 xw 印加して、ターゲットをスパッタリングし1A
/N基体表面に厚さ3.0μmの密着性の良いAl01
Mg0及びSiOの混合被覆層を形成した。
First, an AIN substrate of 2 inches square and 1 am thick was fixed to a sample holder in a sputtering container in which an At 2 O target embedded with MgO and SiO□ was set as a target in advance. Next, the inside of the sputtering container was
At the same time as pulling the
000, introduce Ar gas to a gas pressure of 5 x 10 torr, and apply a high frequency of 13.56 MHz to the target.
Apply xw to sputter the target at 1A
/N Al01 with a thickness of 3.0 μm and good adhesion to the substrate surface
A mixed coating layer of Mg0 and SiO was formed.

得られた半導体素子塔載用基板上にスクリーン印刷法で
、Auペーストを厚さ15μmに塗布し、900 Cで
10分間大気中で焼成し、Au上に外部リードを半田付
けし、引張試験を行なったところ、引張強度4.5臀物
という高い数値が得られ、密着性が良好な半導体素子搭
載用基板が得られた。
Au paste was applied to a thickness of 15 μm by screen printing on the obtained substrate for mounting a semiconductor device, baked at 900 C for 10 minutes in the air, external leads were soldered onto the Au, and a tensile test was conducted. As a result, a tensile strength as high as 4.5 was obtained, and a semiconductor element mounting substrate with good adhesion was obtained.

〔発明の効果〕〔Effect of the invention〕

本発明の半導体素子搭載用基板は、 (イ)基体として半導体素子材料のSiと熱膨張係数の
近似しているA4Nを用いるので、基板と素子との熱膨
張係数の差による応力が小さく、素子の剥離や破壊が生
じない。又、A4Nは熱伝導度が太きいので基板全体と
しての放熱特性も良好である。
The substrate for mounting a semiconductor element of the present invention has the following features: (a) Since A4N, which has a thermal expansion coefficient similar to that of Si, which is the semiconductor element material, is used as the base, stress due to the difference in thermal expansion coefficient between the substrate and the element is small, and the element No peeling or destruction occurs. Furthermore, since A4N has high thermal conductivity, the heat dissipation characteristics of the entire board are also good.

(ロ)iN基体の表面の少なくとも一部に、Si0  
(b) At least a part of the surface of the iN substrate has Si0
.

AIO、MgO及びダイヤモンドからなるグループから
選ばれた少なくとも1種の物質よりなる被覆層を有し、
これらの被覆層物質は電気絶縁性であると共に厚膜ペー
スト及びガラスとの濡れ性が良好であるため、AIN基
体の電気絶縁性を維持しつつ基板に厚膜ペーストの塗布
及びガラスでの封止が可能である。
having a coating layer made of at least one substance selected from the group consisting of AIO, MgO and diamond,
These coating layer materials are electrically insulating and have good wettability with the thick film paste and glass, so it is possible to apply the thick film paste to the substrate and seal it with glass while maintaining the electrical insulation of the AIN substrate. is possible.

従って、本発明は、半導体素子の大型化、高密度化及び
高消費電力化に充分対応できる半導体素子搭載用基板を
提供するものであり、その技術的、経済的な効果は大き
い。
Therefore, the present invention provides a substrate for mounting a semiconductor element that can fully cope with the increase in size, density, and power consumption of semiconductor elements, and has great technical and economical effects.

【図面の簡単な説明】[Brief explanation of drawings]

図面は半導体素子を塔載した本発明の基板の一具体例を
示す断面図である。 1・・AjN基体、2・・被覆層、3・・厚膜ペースト
、4・・半導体素子、5・・半導体素子接合材料、6・
・封止層ガラス。
The drawing is a sectional view showing a specific example of the substrate of the present invention on which a semiconductor element is mounted. 1. AjN substrate, 2. Covering layer, 3. Thick film paste, 4. Semiconductor element, 5. Semiconductor element bonding material, 6.
- Sealing layer glass.

Claims (2)

【特許請求の範囲】[Claims] (1)AlN基体の表面の少なくとも一部に、SiO_
2、Al_2O_3、MgO及びダイヤモンドからなる
グループから選ばれた少なくとも一つの物質よりなる被
覆層を有することを特徴とする半導体素子塔載用基板。
(1) SiO_
2. A substrate for mounting a semiconductor device, characterized by having a coating layer made of at least one substance selected from the group consisting of Al_2O_3, MgO, and diamond.
(2)上記被覆層の厚さが0.1〜20μmである特許
請求の範囲(1)項記載の半導体素子塔載用基板。
(2) The substrate for mounting a semiconductor element according to claim (1), wherein the thickness of the coating layer is 0.1 to 20 μm.
JP13127785A 1985-06-17 1985-06-17 Semiconductor element mounting substrate Pending JPS61288447A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13127785A JPS61288447A (en) 1985-06-17 1985-06-17 Semiconductor element mounting substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13127785A JPS61288447A (en) 1985-06-17 1985-06-17 Semiconductor element mounting substrate

Publications (1)

Publication Number Publication Date
JPS61288447A true JPS61288447A (en) 1986-12-18

Family

ID=15054173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13127785A Pending JPS61288447A (en) 1985-06-17 1985-06-17 Semiconductor element mounting substrate

Country Status (1)

Country Link
JP (1) JPS61288447A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6490586A (en) * 1987-10-01 1989-04-07 Ngk Insulators Ltd Aluminum nitride component and manufacture thereof
EP0688047A1 (en) * 1994-06-13 1995-12-20 Mitsubishi Materials Corporation Aluminium nitride substrate and method of producing the same
JP2002076192A (en) * 2000-08-30 2002-03-15 Toshiba Electronic Engineering Corp Aluminum nitride board and semiconductor package using it

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6490586A (en) * 1987-10-01 1989-04-07 Ngk Insulators Ltd Aluminum nitride component and manufacture thereof
EP0688047A1 (en) * 1994-06-13 1995-12-20 Mitsubishi Materials Corporation Aluminium nitride substrate and method of producing the same
JP2002076192A (en) * 2000-08-30 2002-03-15 Toshiba Electronic Engineering Corp Aluminum nitride board and semiconductor package using it

Similar Documents

Publication Publication Date Title
US4875284A (en) Process for producing a package for packing semiconductor devices
US5056702A (en) Method of manufacturing a semiconductor device
JPS5815241A (en) Substrate for semiconductor device
US4554573A (en) Glass-sealed ceramic package type semiconductor device
US3747173A (en) Method of sealing ceramic to nonmetalic using indium alloy seal
JPS6022347A (en) Substrate for semiconductor element mounting
JPS61288447A (en) Semiconductor element mounting substrate
JPH0870036A (en) Electrostatic chuck
JPS63124555A (en) Substrate for semiconductor device
JPS58103156A (en) Substrate for semiconductor device
JPS60181269A (en) Target for sputtering
JPH03196664A (en) Package for semiconductor device
JPS59115544A (en) Semiconductor element mounting substrate
JPH0362497A (en) Thin film electroluminescent element
JP2600336B2 (en) Method of manufacturing base material for high thermal conductive IC
JP2512898B2 (en) Insulating substrate and manufacturing method thereof
JP2859993B2 (en) Manufacturing method of electrostatic chuck
JPH05160284A (en) Semiconductor device containing package
JP2001118960A (en) Carbon-based metal composite material board with electric insulating film
JPH08316298A (en) Electrostatic chuck
JP2908932B2 (en) Electronic component storage package
JPS6130042A (en) Semiconductor element loading substrate
JPH02224264A (en) Manufacture of semiconductor element mounting substrate
JPS62122152A (en) Manufacture of substrate for semiconductor device
JPS61108151A (en) Substrate for semiconductor device