JPS63124555A - Substrate for semiconductor device - Google Patents
Substrate for semiconductor deviceInfo
- Publication number
- JPS63124555A JPS63124555A JP27102786A JP27102786A JPS63124555A JP S63124555 A JPS63124555 A JP S63124555A JP 27102786 A JP27102786 A JP 27102786A JP 27102786 A JP27102786 A JP 27102786A JP S63124555 A JPS63124555 A JP S63124555A
- Authority
- JP
- Japan
- Prior art keywords
- copper
- substrate
- thin film
- base material
- ceramic thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims description 26
- 239000010409 thin film Substances 0.000 claims abstract description 30
- 239000000919 ceramic Substances 0.000 claims abstract description 27
- 239000000463 material Substances 0.000 claims abstract description 24
- 229910000881 Cu alloy Inorganic materials 0.000 claims abstract description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 20
- 239000010949 copper Substances 0.000 claims abstract description 20
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract description 19
- 239000011733 molybdenum Substances 0.000 claims abstract description 19
- 229910052802 copper Inorganic materials 0.000 claims abstract description 17
- 238000000576 coating method Methods 0.000 claims description 12
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 abstract description 15
- 239000010408 film Substances 0.000 abstract description 5
- 150000004767 nitrides Chemical class 0.000 abstract description 5
- 239000002131 composite material Substances 0.000 abstract description 4
- 238000003466 welding Methods 0.000 abstract description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 abstract description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052799 carbon Inorganic materials 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 2
- 238000005253 cladding Methods 0.000 abstract description 2
- 238000004880 explosion Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 abstract 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 abstract 2
- 229910052593 corundum Inorganic materials 0.000 abstract 1
- 238000010030 laminating Methods 0.000 abstract 1
- 238000000465 moulding Methods 0.000 abstract 1
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 1
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 abstract 1
- 230000017525 heat dissipation Effects 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910000851 Alloy steel Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005422 blasting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- WUUZKBJEUBFVMV-UHFFFAOYSA-N copper molybdenum Chemical compound [Cu].[Mo] WUUZKBJEUBFVMV-UHFFFAOYSA-N 0.000 description 1
- SBYXRAKIOMOBFF-UHFFFAOYSA-N copper tungsten Chemical compound [Cu].[W] SBYXRAKIOMOBFF-UHFFFAOYSA-N 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 229910001651 emery Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005098 hot rolling Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000005382 thermal cycling Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ハイブリッドエC用基板、工Cモジュール用
基板等の半導体素子や電子電気部品な塔載するための電
気絶縁性の基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electrically insulating substrate for mounting semiconductor elements and electronic/electrical components, such as a substrate for a hybrid electronic device, a substrate for an industrial computer module, and the like.
従来、このような電気絶縁性基板としてはアルミナ基板
が広く用いられてきた。Conventionally, alumina substrates have been widely used as such electrically insulating substrates.
しかし、最近の半導体素子の大型化や高集積化に伴ない
半導体素子の発熱量が増大する一方、パッケージは薄型
化の傾向にあるため、半導体素子の発生する熱の放散性
がアルミナ基板よりも優れた電気絶縁性基板の開発が要
望されている。However, as semiconductor devices have become larger and more highly integrated in recent years, the amount of heat generated by semiconductor devices has increased, while packages have also tended to become thinner. There is a demand for the development of excellent electrically insulating substrates.
か\る要望に沿って数種の基板が提案されているが、ま
だ十分な熱放散性を具えた信頼性の高い電気絶縁性基板
を得るに至っていない。Several types of substrates have been proposed in response to these demands, but a highly reliable electrically insulating substrate with sufficient heat dissipation properties has not yet been obtained.
例えば、熱膨張係数が半導体素子に近いFe −42%
N1合金やフバールの板の一表面をアルミナ等の電気絶
縁性セラミック薄膜で被覆した基板があるが、熱伝導度
が小さい欠点があった。そこで、熱伝導度の大きい鋼又
は銅合金の板の一表面ごセラミック薄膜で被覆して熱放
散性を改善した基板が提案されたが、セラミックと銅又
は銅合金の熱膨張係数の差が大きいために、セラミック
薄膜の被覆工程や半導体素子塔載工程での熱サイクルに
よりセラミック薄膜に亀裂や破損が発生し易い欠点があ
った。For example, Fe -42% whose thermal expansion coefficient is close to that of semiconductor elements
There are substrates in which one surface of an N1 alloy or Fvar plate is coated with an electrically insulating ceramic thin film such as alumina, but these have the disadvantage of low thermal conductivity. Therefore, a substrate was proposed in which one surface of a steel or copper alloy plate with high thermal conductivity was coated with a ceramic thin film to improve heat dissipation, but the difference in thermal expansion coefficient between the ceramic and copper or copper alloy was large. Therefore, there is a drawback that the ceramic thin film is easily cracked or damaged due to thermal cycles during the coating process of the ceramic thin film or the process of mounting the semiconductor element on the tower.
更に、熱放散性が高くセラミックと熱膨張係数ご近似さ
せた銅−タングステン又は銅−モリブデン焼結合金を用
い、その−表面をセラミック薄膜で被覆した基板がある
が、塑性加工が困難であるうえ、パッケージの薄型化に
不可欠な厚さ0.51)!1以下の薄型基板は非常に高
価なも°のになる欠点があった。Furthermore, there are substrates that use copper-tungsten or copper-molybdenum sintered alloys, which have high heat dissipation properties and have a coefficient of thermal expansion similar to that of ceramics, and whose surfaces are coated with a ceramic thin film, but they are difficult to process plastically, and , thickness 0.51), which is essential for thinning packages! Thin substrates with a thickness of 1 or less have the disadvantage of being extremely expensive.
本発明は、上記した従来の事情に鑑み、高い熱放散性を
有すると共に、安価で薄型化が可能であって、優れた電
気絶縁性を具える等信頼性の高い半導体装置用基板を提
供することを目的としている。In view of the above-mentioned conventional circumstances, the present invention provides a highly reliable semiconductor device substrate that has high heat dissipation properties, can be made thin at low cost, and has excellent electrical insulation properties. The purpose is to
本発明の半導体装置用基板は、モリブデン板と該モリブ
デン板の上下両面に設けた銅又は銅合金の被覆からなる
基材と、該基材の一表面上に形成した電気絶縁性のセラ
ミック薄膜とからなる。The substrate for a semiconductor device of the present invention comprises a base material consisting of a molybdenum plate, a copper or copper alloy coating provided on both upper and lower surfaces of the molybdenum plate, and an electrically insulating ceramic thin film formed on one surface of the base material. Consisting of
本発明の半導体装置用基板を図面により詳しく説明する
。この基板の基材は熱膨張係数の小さいモリブデン板1
の上下両面に熱伝導率の高い銅又は銅合金の被覆2.3
を積層したものである。銅又は銅合金波N2.3Bモリ
ブデン板1の上下両面に形成する方法は、冷間圧接、熱
間圧接、爆発成形等のクラッド法が適しているが、他の
方法により形成しても良い。The semiconductor device substrate of the present invention will be explained in detail with reference to the drawings. The base material of this board is a molybdenum plate 1 with a small coefficient of thermal expansion.
Coated with copper or copper alloy with high thermal conductivity on both upper and lower surfaces 2.3
It is a layered structure. A suitable method for forming copper or copper alloy waves on both the upper and lower surfaces of the N2.3B molybdenum plate 1 is cladding methods such as cold pressure welding, hot pressure welding, and explosion forming, but other methods may be used.
この基材の一表面上、例えば銅又は鋼合金被覆2の表面
上には電気絶縁性のセラミック薄膜4?形成して基板を
構成する。電気絶縁性のセラミック薄膜4としては、例
えばAt O、Y O、Zr0 。On one surface of this substrate, for example on the surface of the copper or steel alloy coating 2, is an electrically insulating ceramic thin film 4? to form a substrate. Examples of the electrically insulating ceramic thin film 4 include At 2 O, Y 2 O, and Zr0.
TiO□等の酸化物やこれらを主成分とする複合酸化物
、Si3N4. AIN等の窒化物やこれらを主成分と
する複合窒化物、ダイヤモンドや疑似ダイヤモンド状炭
素又はこれらの混合物等がある。これらのセラミック薄
膜4はイオンブレーティング法、スパッタリング法等の
物理的又は化学的気相析出法により形成する。Oxides such as TiO□, composite oxides containing these as main components, Si3N4. Examples include nitrides such as AIN, composite nitrides containing these as main components, diamond, pseudo-diamond-like carbon, and mixtures thereof. These ceramic thin films 4 are formed by a physical or chemical vapor deposition method such as an ion blasting method or a sputtering method.
このように構成した本発明の電気絶縁性基板のセラミッ
ク薄膜4の表面には、従来と同様に金属配線5を蒸着等
により所定のパターンに形成シ、金属配線5上の所定位
置には半導体素子63チツプボンデイングし、この半導
体素子6と金属配線5の所定個所をボンディングワイヤ
7でワイヤボンディングして半導体装置を構成する。On the surface of the ceramic thin film 4 of the electrically insulating substrate of the present invention constructed as described above, metal wiring 5 is formed in a predetermined pattern by vapor deposition or the like as in the conventional method, and a semiconductor element is placed at a predetermined position on the metal wiring 5. 63 chip bonding is performed, and predetermined locations of this semiconductor element 6 and metal wiring 5 are wire-bonded using bonding wires 7 to construct a semiconductor device.
本発明の基板においては、熱膨張係数の小さいモリブデ
ン板1の上下両面に熱伝導率の高い銅又は銅合金の被覆
2.3を積層した基材を用いるので、半導体素子6で発
生する熱は基板表層の銅又は銅合金被覆2.3を伝わっ
て効率良く放散される。又、銅または銅合金はモリブデ
ンの両面に被覆されているので、電気絶縁性セラミック
薄膜を両面に被覆し、金属配線ご施し両面に半導体素子
を塔載できるのみならず両面とも高い熱放散性を得るこ
とができる。同時にまた、モリブデン板1が基材全体と
しての熱膨張係数を低減させると共に、高融点であるの
で実装プロセス等で軟化が生じに<<、剛性の高い基板
となり基板の薄型化を達成できる。In the substrate of the present invention, a base material in which coatings 2.3 of copper or copper alloy with high thermal conductivity are laminated on both upper and lower surfaces of a molybdenum plate 1 with a small coefficient of thermal expansion is used, so that the heat generated in the semiconductor element 6 is It is efficiently dissipated through the copper or copper alloy coating 2.3 on the surface of the substrate. In addition, since copper or copper alloy is coated on both sides of molybdenum, it is possible not only to coat both sides with electrically insulating ceramic thin films and mount semiconductor elements on both sides of metal wiring, but also to provide high heat dissipation properties on both sides. Obtainable. At the same time, the molybdenum plate 1 reduces the coefficient of thermal expansion of the base material as a whole, and has a high melting point, so it does not soften during the mounting process, etc., and becomes a highly rigid board, allowing the board to be made thinner.
基材におけるモリブデン板1の体積率は40%以上90
%以下が好ましく、90%を超えると銅又は鋼合金被覆
2.3が少なくなり基板表層に沿った有効な熱放散性が
得られず、40%未満では基材の熱膨張係数が半導体素
子であるGaAsの1.5倍デ超え基板として不適当で
ある他、熱サイクルでセラミック薄膜4に亀裂や剥離が
生じて絶縁耐圧が低下する等信頼性に劣る結果となるか
らである。The volume fraction of the molybdenum plate 1 in the base material is 40% or more 90
% or less is preferable; if it exceeds 90%, the copper or steel alloy coating 2.3 will decrease and effective heat dissipation along the substrate surface layer will not be obtained, and if it is less than 40%, the thermal expansion coefficient of the base material will be lower than that of the semiconductor element. This is because, in addition to being unsuitable as a substrate with a temperature exceeding 1.5 times that of GaAs, the ceramic thin film 4 cracks and peels due to thermal cycling, resulting in poor reliability such as a decrease in dielectric strength voltage.
又、モリブデン板1の上下両面に銅又は銅合金の被覆2
.3を形成しであるので、バイメタル効果の発生を防ぐ
ことができ、セラミック薄膜4の成膜プロセスや半導体
素子の実装プロセス等で受ける熱サイクルによっても基
材が変形せず、セラミック薄膜4の亀裂や剥離の発生を
有効に防止できる等、信頼性の高い基板が得られる。こ
の効果を最も有効に発揮させるためには、モリブデン板
1の上下両面に設けた銅又は銅合金の被覆2及び3の厚
さが同じであることが好ましい。Further, a coating 2 of copper or copper alloy is applied to both the upper and lower surfaces of the molybdenum plate 1.
.. 3, it is possible to prevent the occurrence of bimetallic effects, and the base material will not be deformed even by thermal cycles received during the film formation process of the ceramic thin film 4 or the mounting process of semiconductor elements, etc., and cracks in the ceramic thin film 4 can be prevented. A highly reliable substrate can be obtained, such as by effectively preventing the occurrence of delamination and peeling. In order to exhibit this effect most effectively, it is preferable that the copper or copper alloy coatings 2 and 3 provided on both the upper and lower surfaces of the molybdenum plate 1 have the same thickness.
尚、セラミック薄膜4の厚さは基板の用途により異なる
が、一般的には1μm〜20μmの範囲が好ましい。厚
さが1μm未満では十分な絶縁耐圧が得られず、20μ
mを超えると成膜時のストレスによってセラミック薄膜
4に亀裂や剥離が発生しや丁いからである。The thickness of the ceramic thin film 4 varies depending on the use of the substrate, but is generally preferably in the range of 1 μm to 20 μm. If the thickness is less than 1 μm, sufficient dielectric strength cannot be obtained;
This is because if it exceeds m, cracks or peeling may occur in the ceramic thin film 4 due to stress during film formation.
実施例I
MO体積率が34〜79%になるように、Mo板の上下
両面にOu被被覆熱間圧延法により形成して、厚さ0.
25鴎のOu/Mo/(!u溝構造クラツド材を作成し
、夫々10X301tllに切断した後、エメリーペー
パーで表面研磨して基材とした。Example I The upper and lower surfaces of a Mo plate are coated with O by a hot rolling method so that the MO volume fraction is 34 to 79%, and the thickness is 0.
25 Ou/Mo/(!U groove structure clad materials were prepared and cut into 10×301 tll pieces, respectively, and the surfaces were polished with emery paper to prepare base materials.
各基材の一表面上に高周波イオンブレーティング法によ
りAIO薄膜を厚さ0.5〜25μmに形成して基材と
した。尚、イオンブレーティング法は原料にAlO焼結
体を用いて電子ビームで溶融窯発させながら、酸素圧2
X 10−’torr、基材温度300C1)3,5
6MHzの高周波の電力100Wで行なった。An AIO thin film was formed on one surface of each base material to a thickness of 0.5 to 25 μm by high frequency ion blating method to obtain a base material. In addition, the ion blasting method uses an AlO sintered body as a raw material, and while igniting it in a melting furnace with an electron beam, the oxygen pressure is increased to 2.
X 10-'torr, base material temperature 300C1) 3,5
The test was performed using a high frequency power of 100 W at 6 MHz.
各基板の特性として、まず走査型電子顕微鏡でAIO薄
膜の亀裂の有無ご調べ、その後各基板に真空蒸着により
厚さ2μmで2X21B1)角のAIN極310個形成
し、電極と基材との間に直流SOVを印加して電気抵抗
を測定した。As for the characteristics of each substrate, we first examined the existence of cracks in the AIO thin film using a scanning electron microscope, and then formed 310 AIN poles with a thickness of 2 μm and a 2×21B1) angle on each substrate by vacuum evaporation, and formed the gap between the electrode and the substrate. The electrical resistance was measured by applying DC SOV to the sample.
得られた結果を下表に示す。尚、比較の為に、厚さ0.
25fiのCu板にAl2O3薄膜ご形成した基板(M
o体積率0%)についても同様に特性を調べ下表に示し
た。The results obtained are shown in the table below. For comparison, the thickness is 0.
A substrate (M
The characteristics of the sample (volume ratio: 0%) were similarly investigated and shown in the table below.
MO体積率が0%及び34%の煮1及び2は基材全体の
熱膨張係数が大きく、ht o 薄膜が1μmでも一
部に亀裂の発生があった。又、AlO薄膜が25μmと
厚い黒9でも一部に亀裂が発生した。In samples 1 and 2 with MO volume fractions of 0% and 34%, the coefficient of thermal expansion of the entire base material was large, and cracks occurred in some parts even when the hto thin film was 1 μm thick. In addition, cracks occurred in some parts even in Black 9, where the AlO thin film was as thick as 25 μm.
実施例2
実施例1の黒5の基材を用いて、その−表面上に各々膜
厚が10μmのYO薄膜及びYO1%含有ZrO薄膜を
実施例1と同様の方法で形成した。Example 2 Using the black 5 base material of Example 1, a YO thin film and a 1% YO-containing ZrO thin film each having a thickness of 10 μm were formed on the surface thereof in the same manner as in Example 1.
2゜
得られた各基板の特性を実施例1と同様にして調べたと
ころ、いずれもセラミック薄膜に亀裂の発生はなく、基
板の電気抵抗も1010Ω以上の良好な絶縁特性を示し
た。2. The characteristics of each of the obtained substrates were examined in the same manner as in Example 1, and it was found that no cracks occurred in the ceramic thin films in any of them, and the substrates exhibited good insulation properties with an electrical resistance of 1010 Ω or more.
尚、以上の説明においては半導体素子以外板としての具
体例を説明したが、本発明は半導体素子以外の例えば電
気機器や機械器具の部品や構成要素間に塔載し又は電気
的に遮断するために挿入する基板等にも適用可能である
。In the above explanation, specific examples have been explained as plates other than semiconductor elements, but the present invention is also applicable to boards other than semiconductor elements, such as for mounting between parts or components of electrical equipment or mechanical equipment, or for electrically interrupting them. It can also be applied to substrates inserted into
本発明によれば、基板表面に熱伝導率の高い銅又は銅合
金の被覆を積層しているので、・基°板表面に沿った熱
放散性は実質的に銅又は銅合金からなる基板に近い優れ
た特性を示す。又、熱伝導率の高い銅又は銅合金の間に
熱膨張係数の小さいモリブデン板を挿入しているので、
セラミック薄膜が比較的厚くても亀裂等の発生がなく、
安価で薄型化が可能であって信頼性の高い半導体装置用
基板な提供Tることができる。According to the present invention, since a copper or copper alloy coating with high thermal conductivity is laminated on the substrate surface, heat dissipation along the substrate surface is substantially reduced to that of the substrate made of copper or copper alloy. Showing excellent properties close to. In addition, molybdenum plates with a low coefficient of thermal expansion are inserted between copper or copper alloys with high thermal conductivity, so
Even if the ceramic thin film is relatively thick, it does not cause cracks, etc.
It is possible to provide a substrate for a semiconductor device that is inexpensive, can be made thinner, and has high reliability.
図面は本発明の半導体装置用基板を用いた半導体装置の
一具体例の断面図である。
1・・モリブデン板 2.3・・銅又は鋼合金被覆4・
・セラミック薄膜 5・・金属配線6・・半導体素子
7・・ボンデイングワイヤ1属配線
セラミック薄M興
1同又は多同合1)及覆The drawing is a sectional view of a specific example of a semiconductor device using the substrate for a semiconductor device of the present invention. 1. Molybdenum plate 2.3. Copper or steel alloy coating 4.
・Ceramic thin film 5・・Metal wiring 6・・Semiconductor element
7. Bonding wire 1 group wiring ceramic thin M-type 1 same or multiple 1) overturning
Claims (4)
た銅又は銅合金の被覆からなる基材と、該基材の一表面
上に形成した電気絶縁性のセラミック薄膜とからなる半
導体装置用基板。(1) A semiconductor device substrate consisting of a molybdenum plate, a copper or copper alloy coating provided on both upper and lower surfaces of the molybdenum plate, and an electrically insulating ceramic thin film formed on one surface of the base material. .
以上90%以下であることを特徴とする、特許請求の範
囲(1)項記載の半導体装置用基板。(2) The volume percentage of molybdenum plate in the above base material is 40%
The substrate for a semiconductor device according to claim (1), characterized in that the ratio is 90% or less.
金の被覆が同じ厚さであることを特徴とする、特許請求
の範囲(1)項又は(2)項記載の半導体装置用基板。(3) The substrate for a semiconductor device according to claim (1) or (2), wherein the copper or copper alloy coatings provided on both upper and lower surfaces of the molybdenum plate have the same thickness.
0μmであることを特徴とする、特許請求の範囲(1)
項ないし(3)項のいずれかに記載の半導体装置用基板
。(4) The thickness of the electrically insulating ceramic thin film is 1 to 2
Claim (1) characterized in that the diameter is 0 μm.
A substrate for a semiconductor device according to any one of items 1 to 3.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27102786A JPS63124555A (en) | 1986-11-14 | 1986-11-14 | Substrate for semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27102786A JPS63124555A (en) | 1986-11-14 | 1986-11-14 | Substrate for semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63124555A true JPS63124555A (en) | 1988-05-28 |
Family
ID=17494386
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27102786A Pending JPS63124555A (en) | 1986-11-14 | 1986-11-14 | Substrate for semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63124555A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5077595A (en) * | 1990-01-25 | 1991-12-31 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
JPH04287952A (en) * | 1991-02-18 | 1992-10-13 | Mitsubishi Electric Corp | Composite insulating board and semiconductor device using same |
US5296735A (en) * | 1991-01-21 | 1994-03-22 | Mitsubishi Denki Kabushiki Kaisha | Power semiconductor module with multiple shielding layers |
WO2004053984A1 (en) * | 2002-12-09 | 2004-06-24 | Kabushiki Kaisha Toyota Chuo Kenkyusho | Semiconductor element heat dissipating member, semiconductor device using same, and method for manufacturing same |
JP2006179791A (en) * | 2004-12-24 | 2006-07-06 | Toshiba Corp | Semiconductor device |
JP2008028295A (en) * | 2006-07-25 | 2008-02-07 | Toyota Central Res & Dev Lab Inc | Power semiconductor module and production method therefor |
JP2008140877A (en) * | 2006-11-30 | 2008-06-19 | Tecnisco Ltd | Composite material heatsink and its manufacturing method |
JP2008210847A (en) * | 2007-02-23 | 2008-09-11 | Jtekt Corp | Circuit structure |
-
1986
- 1986-11-14 JP JP27102786A patent/JPS63124555A/en active Pending
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5077595A (en) * | 1990-01-25 | 1991-12-31 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
US5296735A (en) * | 1991-01-21 | 1994-03-22 | Mitsubishi Denki Kabushiki Kaisha | Power semiconductor module with multiple shielding layers |
JPH04287952A (en) * | 1991-02-18 | 1992-10-13 | Mitsubishi Electric Corp | Composite insulating board and semiconductor device using same |
WO2004053984A1 (en) * | 2002-12-09 | 2004-06-24 | Kabushiki Kaisha Toyota Chuo Kenkyusho | Semiconductor element heat dissipating member, semiconductor device using same, and method for manufacturing same |
DE10393851B4 (en) * | 2002-12-09 | 2007-11-29 | Kabushiki Kaisha Toyota Chuo Kenkyusho | Semiconductor element heat dissipation element and semiconductor device in which this is used and method for its preparation |
US7396735B2 (en) | 2002-12-09 | 2008-07-08 | Kabushiki Kaisha Toyota Chuo Kenkyusyo | Semiconductor element heat dissipating member, semiconductor device using same, and method for manufacturing same |
JP2006179791A (en) * | 2004-12-24 | 2006-07-06 | Toshiba Corp | Semiconductor device |
JP4664670B2 (en) * | 2004-12-24 | 2011-04-06 | 株式会社東芝 | Semiconductor device |
JP2008028295A (en) * | 2006-07-25 | 2008-02-07 | Toyota Central Res & Dev Lab Inc | Power semiconductor module and production method therefor |
JP2008140877A (en) * | 2006-11-30 | 2008-06-19 | Tecnisco Ltd | Composite material heatsink and its manufacturing method |
JP2008210847A (en) * | 2007-02-23 | 2008-09-11 | Jtekt Corp | Circuit structure |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Levinson | Electronic ceramics: properties: devices, and applications | |
US5654586A (en) | Power semiconductor component having a buffer layer | |
EP0009978B1 (en) | Hybrid type integrated circuit device | |
US8304054B2 (en) | Printed circuit board made from a composite material | |
JPS5815241A (en) | Substrate for semiconductor device | |
US11021406B2 (en) | Copper-ceramic composite | |
JPH02263445A (en) | Aluminum nitride substrate and semiconductor using same | |
JPS63124555A (en) | Substrate for semiconductor device | |
JPH03211860A (en) | Semiconductor package | |
US20190055166A1 (en) | Copper-ceramic composite | |
EP0113088B1 (en) | Substrate for mounting semiconductor element | |
JPS58212940A (en) | Substrate for microwave circuit and its manufacture | |
US5250327A (en) | Composite substrate and process for producing the same | |
JPS62216979A (en) | Aluminum nitride sintered body with glass layer and manufacture | |
JPH07283499A (en) | Compound board for electronic parts | |
JPS58103156A (en) | Substrate for semiconductor device | |
JPH01165147A (en) | Ceramic substrate | |
JPS6246986A (en) | Aluminum nitride substrate and manufacture | |
JPS59184586A (en) | Circuit board for placing semiconductor element | |
JP2001118960A (en) | Carbon-based metal composite material board with electric insulating film | |
JPS62182182A (en) | Aluminum nitride sintered body with metallized surface | |
JPH0752761B2 (en) | Integrated circuit package | |
JPS63318146A (en) | Ceramic package and manufacture thereof | |
Patterson et al. | Evaluation of direct bond aluminum substrates for power electronic applications in extreme environments | |
JPS59115544A (en) | Semiconductor element mounting substrate |