JPS61287314A - Scrambler/descrambler circuit - Google Patents

Abstract

PURPOSE:To simplify the circuit by resetting a counter circuit into the initial state while an exclusive OR between an input to a shift register and an output of the 8th stage as a reset pulse synchronous with a clock of 1-bit width so as to eliminate the need for a one-shot pulse generating circuit required for a conventional circuit. CONSTITUTION:An exclusive OR between the input to the shift register 2 and the output of the 8th stage are used to reset a synchronous counter circuit 5 synchronously with a clock signal S1. If disadvantage exists in an input data S6, the counter circuit 5 detecting the disadvantage counts the clock signal S1 by 32 bits and when the disadvantage is not eliminated during the period, a carry output S5 is outputted to invert an output of the exclusive NOR. When the disadvantage is lost, a reset pulse S4 being an output of the exclusive OR circuit 4 ORing exclusively the output of a selection circuit 1 and the output of the 8th stage of the shift register 2 loads all '0' to Q1-Q5 of the counter circuit 5 synchronously with the clock signal S1 to set the counter circuit 5 to the initial state. Thus, the conventional one-shot pulse generating circuit is omitted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a scrambler/descrambler circuit compliant with CCITT Recommendation V, 35, and more particularly to a detection circuit for an adverse condition in which a specific repeating pattern exists.

〔overview〕

The scrambler/descrambler circuit of the present invention resets the counting circuit to its initial state by using the exclusive OR of the input of the shift register and the output of the 8th stage as a reset pulse synchronized with a 1-bit width clock, thereby solving the problems that were previously required. This eliminates the need for a single pulse generation circuit.

[Conventional technology]

Conventionally, this type of scrambler/descrambler circuit is
As shown in FIGS. 3 and 4, when operating as a scrambler, the A side is selected by the scrambler/descrambler switching signal S7 inputted from the input terminal 13 in the selection circuit l, and the scrambler is inputted from the input terminal 11. The input data S6 is subjected to an exclusive OR with the output of the exclusive NOR circuit 6 and is shifted by the clock signal S1 input from the input terminal 12 as the output of the selection circuit 1. 20-stage shift register 2
becomes the input. The third stage output of this shift register 2 and 2
The output of the 0th stage is subjected to an exclusive OR in an exclusive OR circuit 3, and further, in an exclusive NOR circuit 6, the output of the exclusive OR circuit 3 and a carry of the counting circuit 5a for detecting an unfavorable state are obtained. After the output S5 is subjected to an exclusive NOR, the output of the exclusive NOR circuit 6 is subjected to an exclusive OR with the input data S6, and is output to the output terminal 14. At the same time, the signal is input again to the selection circuit 1. By repeating the above steps, the manual data S6 is scrambled.

At this time, in order to detect an unfavorable state in which a specific repeating pattern exists, the counting circuit 5a counts the clock signal S1 by 32 bits, and if the unfavorable state continues during that time, the counting circuit 5a outputs a carry output S5. This occurs and the output of the exclusive NOR circuit 6 is inverted to prevent the disadvantageous state. If there is no disadvantageous state, the exclusive OR circuit 4 that takes the exclusive OR of the outputs of the first stage and the ninth stage of the shift register 2 generates a trigger pulse S2, and the AND circuit 8 generates a trigger pulse S2 using the clock signal S1. The single pulse generation circuit 9 is operated with the removed pulse s3. The single pulse generating circuit 9 generates a reset pulse S4a within a half period of one clock, and resets the counting circuit 5a to the initial state asynchronously to the clock signal S1.

In addition, when operating as a descrambler, the selection circuit 1
The B side is selected by the switching signal S7 and input to the shift register 2 at the next stage. Thereafter, it performs the same operation as the scrambler described above and is outputted to the output terminal 14 as descrambled data.

[Problem that the invention seeks to solve]

The conventional scrambler/descrambler circuit described above is
Single pulse generation circuit 9 to detect and prevent adverse conditions
The disadvantage is that the circuit is complicated.

An object of the present invention is to provide a scrambler/descrambler circuit with a simple circuit configuration that does not require a single pulse generation circuit by eliminating the above-mentioned drawbacks.

[Means for solving problems]

The scrambler/descrambler circuit of the present invention includes a shift register (2) that receives scrambled data and descrambled data as serial inputs, a shift register (2) that receives the output of this selection circuit as serial inputs, and A first exclusive OR circuit (3) that takes the exclusive OR of the output of the third stage and the output of the 20th stage of the shift register, a counting circuit (5) that counts the clock signal, and the output of the selection circuit. a second exclusive OR circuit (4) that performs an exclusive OR of the outputs of the eighth stage of the shift register and outputs a reset pulse for the counting circuit in synchronization with the clock signal;
An exclusive NOR circuit (6) which takes the exclusive NOR of the output of the exclusive OR circuit and the output of the counting circuit, and an exclusive NOR circuit (6) which takes the exclusive NOR of the output of the exclusive NOR circuit (6) and the output of the input data signal. The present invention is characterized by comprising a third exclusive OR circuit (7) which calculates an exclusive OR and outputs the result to the selection circuit and the output terminal.

[For production]

The present invention resets the counting circuit to its initial state by using the exclusive OR of the input of the shift register and the output of the 8th stage as a reset pulse synchronized with a 1-pin width clock. A single pulse generation circuit is not required.

〔Example〕

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In this embodiment, the switching signal S input from the input terminal 13 is
7, a shift register 1 receives scrambled data and descrambled data manually as input in series, and a 20-stage shift register 2 receives the output of this selection circuit 1 as input,
A first exclusive OR circuit 3 that takes the exclusive OR of the output of the third stage and the output of the 20th stage of the shift register 2, and a synchronous counting circuit that performs counting using the clock signal SL input to the input terminal 12. 5, the exclusive OR of the output of the selection circuit 1 and the output of the 8th stage of the shift register 2, and generates the clock signal S.
A second exclusive OR circuit 4 outputs a reset pulse S2 of the counting circuit 5 in synchronization with 1, and an exclusive NOR of the output of the exclusive OR circuit 3 and the carry output S5 of the counting circuit 5 is performed. an exclusive NOR circuit 6; and a third exclusive OR circuit 7 which performs the exclusive OR of the output of the exclusive NOR circuit 6 and the input data signal S6 and outputs the exclusive OR to the selection circuit 1 and the output terminal 14. It is equipped with

That is, the feature of the present invention is that the counting circuit 5 is reset in synchronization with the clock signal S1 using the exclusive AND of the input of the shift register and the output of the eighth stage. Therefore, as the counting circuit 5, a synchronous type circuit is used.

Next, the operation of this embodiment will be explained with reference to the operation timing chart shown in FIG. When operating as a scrambler, the A side is selected by the scrambler/descrambler switching signal S7 input from the input terminal 13 in the selection circuit l, and the output of the exclusive NOR circuit 6 is selected in the exclusive OR circuit 7. Input data input from the input terminal 11 that is subjected to the exclusive OR is outputted from the selection circuit 1 and inputted to the 20-stage shift register 2 which is shifted by the clock signal S1 input from the input terminal 12. The exclusive OR of the third stage output and the 20th stage output of the shift register 2 is taken by the exclusive OR circuit 3, and the output is a carry output S of the counting circuit 5 that detects a disadvantageous state.
5 and an exclusive NOR circuit 6 performs exclusive NOR. The output of the exclusive NOR circuit 6 is the input data S
6 and the exclusive OR circuit 7 and output as scrambled data to the output terminal 14, the data is input again to the selection circuit 1 and the same operation is repeated.

Furthermore, if the input data S6 has a disadvantageous state, the counting circuit 5 for detecting the disadvantageous state counts the clock signal S1 in 32 bits, and if the disadvantageous state is not canceled during that time, a carry output S5 is output and exclusive negation is performed. Inverts the OR output. As a result, the input data is inverted and the disadvantageous state disappears. If the disadvantageous state disappears while the counting circuit 5 is counting 32 bits, the output of the exclusive OR circuit 4 which is the exclusive OR of the output of the selection circuit 1 and the output of the 8th stage of the shift register 2 is used. With a certain reset pulse S4, the counting circuit 5 is loaded with the Q1 to Q5 heel O in synchronization with the clock signal Sl and set to the initial state.

When operating as a descrambler, the B side is selected by the scrambler/descrambler switching signal S7 inputted from the input terminal 13 in the selection circuit 1, and inputted to the next stage shift register 2. Thereafter, it performs the same operation as the scrambler described above and is outputted to the output terminal 14 as descrambled data.

〔Effect of the invention〕

As explained above, the present invention conventionally takes the exclusive OR of the output of the first stage and the output of the ninth stage of a 20-stage shift register to detect a disadvantageous state. By using the exclusive OR of the input of the shift register and the output of the eighth stage as a pulse synchronized with a 1-bit width clock and resetting the counting circuit to the initial state, there is an effect that the conventional single pulse generation circuit can be omitted.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is an operation timing diagram of FIG. 1. FIG. 3 is a block diagram of an example of a conventional scrambler/descrambler circuit. FIG. 4 is an operation timing diagram of FIG. 3. 1... Selection circuit, 2... Shift register, 3.4.
7... Exclusive OR circuit, 5.5a... Counting circuit,
6... Exclusive NOR circuit, 11.12.13...
・Input terminal, 14... Output terminal, Sl... Clock signal, S2... Trigger pulse, S3... Pulse, S
4, S4a...Reset pulse, S5...Carry output, S6...Input data, S7...Switching signal.

Claims (1)

[Claims] (1) A selection circuit (1) that switches input between scrambled data and descrambled data, and a shift register (1) that uses the output of this selection circuit as a serial input.
2), a first exclusive OR circuit (3) that takes the exclusive OR of the third stage output and the 20th stage output of this shift register, a counting circuit (5) that counts clock signals, and the above-mentioned A second exclusive OR circuit (4
), and an exclusive NOR circuit (6) which takes the exclusive NOR of the output of the first exclusive OR circuit and the output of the counting circuit
), and a third exclusive OR circuit (7) that performs the exclusive OR of the output of the exclusive NOR circuit (6) and the input data signal and outputs the result to the selection circuit and the output terminal. A scrambler/descrambler circuit characterized by: