JPS61287138A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61287138A JPS61287138A JP60128729A JP12872985A JPS61287138A JP S61287138 A JPS61287138 A JP S61287138A JP 60128729 A JP60128729 A JP 60128729A JP 12872985 A JP12872985 A JP 12872985A JP S61287138 A JPS61287138 A JP S61287138A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- inner lead
- semiconductor element
- expanded
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
この発明はインナーリードの端部がバンプを介して、半
導体素子の電極に接合されている半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device in which an end of an inner lead is bonded to an electrode of a semiconductor element via a bump.
従来の技術
従来のこの種の半導体装置は、例えば第５図及び第６図
のようになっていた。2. Description of the Related Art Conventional semiconductor devices of this type have been constructed as shown in FIGS. 5 and 6, for example.
すなわち、ポリイミドのような絶縁フィルム１に接着さ
れたストレートのインナーリード２の端部には、熱圧着
で金製のバンプ３が取付けられている。そしてこのバン
プ３を介して半導体素子４の電極６に前記インナーリー
ド２の端部が接合される。前記インナーリード２の横軸
は、！６図に示すように、前記バンプ３の横幅の半分以
下であることが一般である。又インナーリード２の端は
、第６図に示すように、前記電極６を横切って、パフシ
ベーシ冒ン１１！ｅ上に達シてイル。That is, gold bumps 3 are attached to the ends of straight inner leads 2 bonded to an insulating film 1 such as polyimide by thermocompression bonding. The ends of the inner leads 2 are bonded to the electrodes 6 of the semiconductor element 4 via the bumps 3. The horizontal axis of the inner lead 2 is ! As shown in FIG. 6, it is generally less than half the width of the bump 3. Further, the ends of the inner leads 2 cross the electrodes 6 to form a puffy base 11!, as shown in FIG. e reached the top.
発明が解決しようとする問題点
しかし、このような構造のものでは、バンプ３をインナ
ーリード２に取付けるときに位置ずれが生じた場合、接
合時にインナーリード２を介してバンプ３に作用する押
圧力が均等でなくなる結果、バンプ３と前記電極６との
接合強度が不十分になるという問題がある。Problems to be Solved by the Invention However, with such a structure, if a positional shift occurs when attaching the bump 3 to the inner lead 2, the pressing force acting on the bump 3 via the inner lead 2 during bonding As a result, there is a problem that the bonding strength between the bump 3 and the electrode 6 becomes insufficient.
またインナーリード２の先端が、半導体素子４のパッジ
ページロン膜６の上方にまで達しているので、接合時に
インナーリード２の先端部でパッジページロン膜６を破
壊するという問題があった本発明は、上記の問題点に鑑
み、接合強度が高く、接合時に半導体素子に損傷を与え
ない半導体装置を提供するものである。Furthermore, since the tips of the inner leads 2 reach above the pad Pageron film 6 of the semiconductor element 4, the present invention has a problem in that the tips of the inner leads 2 break the Pad Pageron film 6 during bonding. In view of the above problems, the present invention provides a semiconductor device that has high bonding strength and does not damage semiconductor elements during bonding.
問題点を解決するための手段
そして、上記問題点を解決する本発明の技術的な手段は
、半導体素子の電極と、端部において横幅が拡張される
と共にその拡張部が前記電極よりも大きくならない範囲
で形成されたインナーリードとが、前記インナーリード
の端部に取付けたバンプを介して接合されていることを
特徴とするものである。Means for Solving the Problems The technical means of the present invention for solving the above-mentioned problems is to provide an electrode of a semiconductor element whose width is expanded at the end, and the expanded portion does not become larger than the electrode. The inner lead formed in the area is connected to the inner lead via a bump attached to the end of the inner lead.
作 用 この技術的手段による作用は次のようになる。For production The effect of this technical means is as follows.
すなわち、インナーリードの端部が広くなっているので
、バンプとの間に多少の位置ずれがあってもこの広い部
分で吸収できる結果、接合時にインナーリードを介して
バンプに作用する押圧力を均等にでき、バンプと電極と
の接合強度を増大させることかできる。さらに、インナ
ーリードの端る
部が半導体素子の電極よりも小さくなってぃゞので、接
合時にパッジベージシン膜に接触して、これに損傷を与
えることを防止することができる。In other words, since the end of the inner lead is wide, even if there is some misalignment between the inner lead and the bump, this wide part can absorb it, and as a result, the pressing force applied to the bump via the inner lead during bonding is evenly distributed. This makes it possible to increase the bonding strength between the bump and the electrode. Furthermore, since the end portions of the inner leads are smaller than the electrodes of the semiconductor element, it is possible to prevent them from coming into contact with the padding thin film and damaging it during bonding.
実施例
以下、本発明の一実施例を第１図乃至第３図にもとづい
て説明する。ポリイミドのような絶縁フィルム１１に接
着されたインナーリード１２は鋼本体の外周に錫メッキ
が施されてなり、その端部１７は矩形状に拡張形成され
ている。この拡張部１７ａの横幅は、インナーリード１
２の他の部分の横幅の３〜６倍程度に定められている。EXAMPLE Hereinafter, an example of the present invention will be explained based on FIGS. 1 to 3. The inner lead 12 is bonded to an insulating film 11 such as polyimide, and the outer periphery of the steel body is plated with tin, and its end portion 17 is expanded into a rectangular shape. The width of this extended portion 17a is the width of the inner lead 1.
It is set to be about 3 to 6 times the width of the other part of 2.
又前記拡張部１７ａは半導体素子１４の電極１５よ！ｌ
１着干小さな形状に形成されている。Also, the extended portion 17a is the electrode 15 of the semiconductor element 14! l
It is formed into a small shape.
前記拡張部１７ａの下面には、金製のバンプ１３が熱圧
着等によって取付けられている。半導体素子１４の上面
適所には、アルミニウムからなる電極１６が形成されて
いると共に、この電極１６の周囲はパッジベージコン膜
１６で被覆されている。A gold bump 13 is attached to the lower surface of the extended portion 17a by thermocompression bonding or the like. An electrode 16 made of aluminum is formed at a suitable location on the upper surface of the semiconductor element 14, and the periphery of this electrode 16 is covered with a padding film 16.
前記インナーリード１２の端部１７を前記電極１６に接
合するに際しては、加圧ツールを用い、前記バンプ１３
に押圧力と熱を与えることによって、バンプ１３を前記
電極１６に溶融一体化させる。この結果、第３図に示す
半導体装置が得られる。When joining the end portion 17 of the inner lead 12 to the electrode 16, a pressure tool is used to bond the bump 13.
By applying pressing force and heat to the bump 13, the bump 13 is melted and integrated with the electrode 16. As a result, the semiconductor device shown in FIG. 3 is obtained.
次に、この一実施例の構成における作用を説明する。Next, the operation of the configuration of this embodiment will be explained.
上記のような構造になっているため、接合時にインナー
リード１２の端部１７を介してバンプ１３に作用する押
圧力はバンプ１３の全体に均等に及び、バンプ１３は前
記電極１６に確実強固に接合される。また、インナーリ
ード１２の端部１７がパッジベージラン膜１６に接触す
ることがない。Due to the above structure, the pressing force applied to the bump 13 through the end 17 of the inner lead 12 during bonding is evenly applied to the entire bump 13, and the bump 13 is firmly attached to the electrode 16. Joined. Further, the end portion 17 of the inner lead 12 does not come into contact with the pad page run film 16.
、以上のように本実施例によれば、バンプ１３と電極１
５との接合強度が高くなるとともに、位置ずれが多少発
生しても接合強度に影響しない。また、パッシベーショ
ン膜１６への影響もない。さらにインナーリード１２は
基部において細くなっているため、接合時の放熱が少な
く熱効率よく前記接合が可能になる。As described above, according to this embodiment, the bump 13 and the electrode 1
The bonding strength with 5 is increased, and even if some misalignment occurs, the bonding strength is not affected. Further, there is no influence on the passivation film 16. Furthermore, since the inner lead 12 is thinner at the base, heat radiation during bonding is reduced and the bonding can be performed with high thermal efficiency.
次に本発明の他の実施例について説明する。Next, other embodiments of the present invention will be described.
第４図は他の実施例を示しており、同図において、１１
は絶縁フィルム、１２はインナーリード、１４は半導体
素子、１６は電極、１６はパッシベーション膜、１７は
矩形に広がった端部で、以上は第１図乃至第３図に示す
実施例におけるものと同様なものである。前記実施例と
構成が異なるのは下面に小さな突起２８をもつ、裾広が
９になった金製のバンプ１３で接合されている点である
。FIG. 4 shows another embodiment, in which 11
12 is an insulating film, 12 is an inner lead, 14 is a semiconductor element, 16 is an electrode, 16 is a passivation film, and 17 is a rectangular end portion, which is the same as in the embodiment shown in FIGS. 1 to 3. It is something. The structure differs from the previous embodiment in that it is joined by a gold bump 13 with a wide bottom 9 and a small protrusion 28 on the lower surface.
上記のように構成された半導体装置について、以下その
作用を説明する。前記バンプ１３の下面の小さな突起２
８が前記電極１５に接合するとき、押圧力を受けて押し
広げられ、電極１５の表面酸化膜を破シやすくしている
ので、電極１５の真生面とバンプ１３との金属接合面が
増大する。また小さな突起２８を設けているのは応力集
中を起こさせてバンプ１３をつぶれやすくするためであ
る。The operation of the semiconductor device configured as described above will be explained below. A small protrusion 2 on the lower surface of the bump 13
When 8 is bonded to the electrode 15, it is pushed apart by the pressing force, making it easier to break the surface oxide film of the electrode 15, so that the metal bonding surface between the true surface of the electrode 15 and the bump 13 increases. . Further, the reason why the small protrusions 28 are provided is to cause stress concentration and make the bumps 13 more likely to collapse.
更に、裾広がりにバンプ１３が形成されているのは、高
価な金の使用量を少なくするため°である。Furthermore, the reason why the bumps 13 are formed at the wider hem is to reduce the amount of expensive gold used.
なお、上記実施例において、インナーリード１２の先端
部分１７を矩形としたが、先端部分１７は円形、楕円形
など他の形状に形成してもよい。In the above embodiment, the tip portion 17 of the inner lead 12 is rectangular, but the tip portion 17 may be formed in other shapes such as a circle or an ellipse.
発明の効果
以上のように本発明は、バンプと電極との接合強度を増
大させることができ、インナーリードを半導体素子の電
極に確実強固に接合できるという効果がある。また本発
明はインナーリードの端部が接合時に半導体素子のパフ
シペーシ替ン膜に接触することを回避でき、パフシベー
シッンが接合時に損傷されるのを防止できるという効果
があムEffects of the Invention As described above, the present invention has the advantage of being able to increase the bonding strength between bumps and electrodes, and allowing inner leads to be reliably and firmly bonded to electrodes of semiconductor elements. Furthermore, the present invention has the advantage that the ends of the inner leads can be prevented from coming into contact with the puff membrane replacement film of the semiconductor element during bonding, and the puff membrane can be prevented from being damaged during bonding.
第１図は本発明の一実施例において、接合前の状態を示
す主要部の縦断正面図、第２図はその干す主要部の縦断
正面図、第６図は従来の半導体装置の接合前の状態を示
す縦断正面図、第６図はその平面図である。
１２・・・・・・インナーリード、１３・・・・・・バ
ンプ、１４・・・・・・半導体素子、１５・・・・・・
電極、１７・・・・・・端部、１７ａ・・・・・・拡張
部。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名１２
−一一インデーリーｙ
ｆ５−ハ１ン７ａ
１７−塙邦
１フルー＝ｒＡ陸飾
１′１１Fig. 1 is a longitudinal sectional front view of the main part of an embodiment of the present invention showing the state before bonding, Fig. 2 is a longitudinal sectional front view of the main part to be dried, and Fig. 6 is a conventional semiconductor device before bonding. A longitudinal sectional front view showing the state, and FIG. 6 is a plan view thereof. 12...Inner lead, 13...Bump, 14...Semiconductor element, 15...
Electrode, 17... End portion, 17a... Extension portion. Name of agent: Patent attorney Toshio Nakao and 1 other person12
-11 Indy y f5-Ha1n7a 17-Hanakuni 1Flu = rA land decoration 1'11
Claims (1)
れると共にその拡張部が前記電極よりも大きくならない
範囲で形成されたインナーリードとが、前記インナーリ
ードの端部に取付けたバンプを介して接合されているこ
とを特徴とする半導体装置。(1) An electrode of a semiconductor element and an inner lead whose width is expanded at the end and whose expanded portion is not larger than the electrode are connected to each other via a bump attached to the end of the inner lead. A semiconductor device characterized in that the semiconductor device is bonded with
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60128729A JPS61287138A (en) | 1985-06-13 | 1985-06-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60128729A JPS61287138A (en) | 1985-06-13 | 1985-06-13 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61287138A true JPS61287138A (en) | 1986-12-17 |
| JPH0426546B2 JPH0426546B2 (en) | 1992-05-07 |
Family
ID=14992003
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60128729A Granted JPS61287138A (en) | 1985-06-13 | 1985-06-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61287138A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5027995A (en) * | 1988-08-31 | 1991-07-02 | Siemens Aktiengesellschaft | Process for bonding semiconductor chips to substrates |
| US5504375A (en) * | 1992-03-02 | 1996-04-02 | International Business Machines Corporation | Asymmetric studs and connecting lines to minimize stress |
-
1985
- 1985-06-13 JP JP60128729A patent/JPS61287138A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5027995A (en) * | 1988-08-31 | 1991-07-02 | Siemens Aktiengesellschaft | Process for bonding semiconductor chips to substrates |
| US5504375A (en) * | 1992-03-02 | 1996-04-02 | International Business Machines Corporation | Asymmetric studs and connecting lines to minimize stress |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0426546B2 (en) | 1992-05-07 |
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