JPS61283097A - Non-volatile memory device - Google Patents

Abstract

PURPOSE:To eliminate writing which exceeds the number of times of limitation by providing a counter to count the number of times of rewriting and a memory on the same chip of a memory device and issuing an alarm when the number of times of rewriting approaches the limitation. CONSTITUTION:On a non-volatile reading exclusive-use memory (EROM) 2 and the same semiconductor chip 1, a rewriting number times counter 7, the EROM 2 and the same number times rewritable memory 8 are provided. When a writing button is operated, the contents of the memory 8 are presetted to the counter 7. Next, the change of the output of electric power source 5 due to the action of rewriting is counted 7, and after the rewriting is completed, the output of the counter 7 is written to the memory 8. When the number of times of the rewriting approaches the use limit, an alarm generating circuit 9 is operated. For such a reason, the wasteful writing, which exceeds the number of times of the limitation, can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a rewritable read-only nonvolatile memory device that is effective for use in memory devices that are frequently rewritten, such as desktop electronic memo pads.

(Prior Art) Conventional non-volatile read-only memory device (hereinafter simply FR)
OM) tends to limit the number of rewrites, and the number of rewrites is determined based on whether or not it causes errors in the read output.
Generally speaking, for safety reasons, the number of times it could be rewritten was slightly less than the actual number of times it could be rewritten.

(Problems to be Solved by the Invention) Therefore, as described above, the conventional FROM is uneconomical in that it is judged that its life has come to an end and is discarded even though there is still no room for use.

In view of such uneconomical problems, the present invention provides a FROM that can be used up to the limit of the number of rewrites.

(Means for solving the problem) An electrically rewritable non-volatile memory (hereinafter referred to as EEROM) and a circuit for controlling write and read addresses for this memory are provided on the same semiconductor chip.
Form a counter that counts the number of rewrites and an EROM that stores the number of rewrites, and display the number of rewrites or the remaining number of possible rewrites on an input device, etc. that is prepared in addition to being used in combination with the counter. The above-mentioned problems can be solved by a warning method such as issuing a warning at the same time, or by a configuration that can notify of approaching the write limit.

(Function) If the EFROM of the present invention is used in an electronic device that is repeatedly rewritten, such as an electronic memo pad, when the number of rewrites approaches the actual usage limit, a warning such as an alarm or a number display will be automatically issued. Therefore, the user can not only use the device with peace of mind, but also eliminate economical costs and eliminate malfunctions during use, greatly improving the reliability of the device.

(Example) Hereinafter, the present invention will be explained in detail based on an example using drawings.

FIG. 1 is a block diagram showing the internal structure of an EFROM according to an embodiment of the present invention.

1 is a semiconductor chip (package), 2 is an electrically rewritable large-capacity EEROM with a memory capacity of, for example, 2 bytes, 3 is an 11-bit address generation circuit (binary counter) that determines the address, and 4 is an This is a write/erase control circuit that controls writing and erasing. Also, 5
has an oscillator as a power supply and generates a write voltage vw and an erase voltage V□ other than VB from the input voltage VB (for example, +5V) from the terminal T4. Reference numeral 6 denotes a counter control circuit which controls the rewrite count counter 7, writes the output of the rewrite count memory 8 to the rewrite count counter 7 each time writing is started, and writes the output of the rewrite count memory 8 to the rewrite count counter 7 each time writing is completed. It performs the operation of writing the output into the rewrite count memory 8.

The rewrite count counter 7 is a counter whose count value increases by one bit each time the output of the power supply 5 changes from the write voltage vw to the read voltage. Number of times memory is rewritten to 8
is preset with the output of

This rewrite count memory 8 is a non-volatile memory, and the EERO
It is composed of M and can be rewritten the same number of times as the large-capacity EEROM 2. For example, set the number of rewrites to 21.
If the number of rewrites is 6 (=65536) times, the number of rewrites memory 8 consisting of an IJROM will run out at 16 bits.

Further, 9 is a warning generation circuit, for example, a rewriting number counter 7.
When all of the upper 8 bits of the 16 output bits become "1", a warning voltage, for example "H" level, is output from the terminal T7. At this time, the lower 8 bits, that is, the remaining 25
If rewriting is performed only 6 times, the number becomes 2, so the user operates the device while taking into account the possible number of rewrites of this remaining disk, which is 256 times.

FIG. 2 is a diagram showing an example of an embodiment of the present invention, and shows a programmable ROM (PROM) writer 1 input to the present invention.
0 (however, the key gate is not shown) and the connector portion of the semiconductor chip 1 shown in FIG. Second
In the figure, terminals P1 to P8 are connected to terminals T1 to T8 of semiconductor chip 1 with their subscripts matching.

When data to be written to the semiconductor chip 1 is input and stored into the PROM writer 10 using a known input method using a key date (not shown) and the write button 14 is pressed, a high voltage, for example 12V, is generated at the terminal Ps. A control signal is sent to the counter control circuit 6 from an oscillator (not shown) built in the power supply 5 via the terminal T5 of the semiconductor chip 1. This counter control circuit 6 is connected to the rewrite number memory 8 to 1.
The 6-bit data (number of rewrites) is read and the rewrite number counter 7 is preset. Next, write from power supply 5'
A control signal is sent to the erase control circuit 4, which changes the address generation circuit 3 from rOJ to "211" and erases the EFROM 2.
clear the data. If this erase operation is not necessary, the next write operation may be performed directly.

When erasing is completed, the write data is output from the PROM writer 10 to the 8-bit terminal P8. The time required for erasing may be managed by providing a timer in the PROM writer 10, or may be returned to the PROM writer 10 by providing a new terminal (not shown) from the semiconductor chip 1. In any case, after writing becomes possible, the write clock is output to the terminal P3 of the PROM writer 10, and the address (11 bits) is output from the terminal P6, and transmitted to the semiconductor thiazo 1, and the data at that time is transferred to the PROM. Terminal P1 of writer 10 (8-bit,
The data and address timings are matched, and bytes are written to the large-capacity 11 JROM 2 in the second column. Note that the black and white lines are for timing adjustment, so they can be omitted if the address and data are synchronized.

When the writing is completed, an end mark is displayed on the data display section 11 of the PROM writer 10. Note that during writing, it goes without saying that the write data and address are displayed on the data display section 11 and the address display section 12, respectively. When this writing is completed, terminal P5 becomes 5V or QV.
Therefore, the write/erase control circuit 4 is driven from the power source 5 to send out a 1-bit clock signal corresponding to the number of write times, incrementing the counter count by one, and the state is written into the rewrite number memory 8. This writing (or rewriting) is also the same as writing (or rewriting) in EEROM 2, so its explanation will be omitted.

The normal write operation has been explained above. Next, the display of the remaining number of rewrites according to the present invention will be described.

Now, assume that the upper 8 bits of the write count memory 8 of the EEROM 2 on the semiconductor chip 1 are all "1", and connect the semiconductor chip 1 to the PROM writer 1°.
When the WRITE button 14 is pressed, the contents of the memory 8 are preset in the rewrite counter 7 as described above. The output of the rewriting number counter 7 is sent to the warning generation circuit 9 as a numerical value rlllfllllo0.
Compared to 000000 J, the upper 8 bits are "1", so a warning voltage of, for example, 5V is generated at terminal T7. At this time, the terminal P7 of the PROM writer 1° becomes 5V, and this is detected and a message indicating that the remaining number of rewrites is small is displayed on the address display section 12, and at the same time, an LED (light emitting diode) is displayed on the alarm section (ARARM) 13. A light-emitting display or a warning sound is generated. At this time, the terminal P2 of the PROM writer 10 becomes "H" level, and the bidirectional selector 15 is switched to the warning generation circuit 9 or
The lower 8 bits of the rewrite count counter 7 are output to the terminal TI. When the terminal T2 is "Ov", the 8-bit data from the terminal T1 is in the write state.
In the read state, the selector 15 is controlled by the output of the power supply 5 so that the 8-bit output data of the EEROM 2 is output to the terminal TI.

Therefore, the data of the lower 8 bits of the warning generation circuit 9 is transmitted to the terminal P1 of the PROM writer 10 via the terminal Tl, and the value obtained by subtracting the binary number indicated by the data from that 28 is displayed on the data display section 11. Displayed in hexadecimal. if,
If the lower 8 bits are all "O", "FF" is displayed. It is shown that it is possible to rewrite the remaining 256 times.

If the write button 14 is pressed again in this state, the terminal P
2 is "Ov", therefore the terminal T2 also becomes rOVJ, and the above write operation is performed. If the lower 8 bits of the warning generation circuit 9 are all "1", the data display section 11 will display "00" and no matter how many times you press the write button 14, the terminal P2 will remain at "5v" and the EEROM No writing is performed to 2.

According to the present invention described in detail above, writing exceeding the limit number of times is clearly prevented.

Although the explanation is based on an example using the FROM writer 1o, terminals T7 and T2 are connected internally, and a warning voltage is output from the warning generation circuit 9 only when a predetermined number of rewrites has been reached. It goes without saying that the same effect can be obtained even if the internal configuration of FIG. 1 is changed to prohibit the following.

(Effects of the Invention) As is clear from the above explanation, the FROM device of the present invention has the following features:
Since the limit number of rewrites is easily indicated or warned to the user, there is no need to rewrite data more than the limit and lose the data that has been written to no avail.
Since it only requires adding some peripheral circuits to the same step as the step that constitutes M, it can be implemented economically and easily, and therefore it can be implemented in the configuration of an electronic circuit, such as an electronic mechacho. There is much to be gained from it.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a circuit device according to an embodiment of the present invention, and FIG. 2 is a schematic diagram illustrating the state of use of the present invention. 1...Semiconductor chip, 2...Large capacity EEROM, 3
... Address generation circuit, 4... Write/erase control circuit, 5... Power supply, 6... Counter control circuit, 7...
Rewriting number counter, 8... Rewriting number memory, 9.
...Warning generation circuit, 10...PROM writer, 11.
...Data display section, 12...Address display section, 13.
...Alarm section, 14...Writing? Tan. one

Claims (1)

[Claims] electrically rewritable nonvolatile read-only memory and writing to this memory on the same semiconductor chip;
It consists of a circuit that controls the read address, a counter that counts the number of rewrites, and a nonvolatile memory that stores the number of rewrites. 1. A nonvolatile memory device characterized in that a warning can be issued using at least one of displaying that the number of rewrites of a memory device approaches a limit or issuing an alarm at that time.