KR200142436Y1 - Fiscal eprom driving apparatus - Google Patents

Abstract

The present invention relates to a physical EPROM driving device, which receives data DATA, an address signal ADDRESS and a control signal CONTROL from a CPU, temporarily stores them, and latches signals according to the stored signals. A latch for outputting a signal and a driving signal supplied from the power supply and a latch signal LATCH outputted from the latch for receiving a latch, and storing and outputting data generated from a CPU. Sales generated from the CPU by receiving a physical EPROM driving circuit that outputs a read signal and a read / read signal outputted from the physical EPROM driving circuit. It consists of a physical EPROM that stores and outputs data according to the data, so that a driving circuit for driving a large-capacity EPROM can be easily configured, and the circuit configuration is simple for easy operation and control. It is effective in reducing the manufacturing cost.

Description

Fiscal EPROM driving apparatus

The present invention relates to a Fiscal EPROM drive device, and more particularly, to a Fiscal EPROM drive device for efficiently driving a Fiscal EPROM for storing sales data in the cash register.

Cash registers are often used to calculate sales at stores that trade goods or to make simple tax calculations. Such a cash register is installed in a public place and a narrow store where cash is handled, and various functions are provided for amount calculation or sales management.

In addition, a commonly used cash register will use a Fiscal EPROM to permanently store data on sales. Physical EPROMs generally do not use RAM that can be read, written, or deleted, but can be read and written and erased with an electrical signal. Use a missing EPROM.

Nowadays, due to the development of semiconductor integrated circuit technology, a large-capacity EPROM that uses more data is marketed, and a problem that a more efficient physical EPROM driving circuit is required when using this large-capacity EPROM occurs.

Therefore, in order to solve this problem, the present invention effectively writes / leads data stored in a physical EPROM when using a physical EPROM using a large EPROM of 1 mega bit or more. An object of the present invention is to provide a physical EPROM driving device for reading.

The present invention having this purpose, the latch (Latch) for receiving the data (DATA), the address signal (ADDRESS) and the control signal (CONTROL) output from the CPU to temporarily store and output the latch signal (LATCH) in accordance with the stored signal And a write / read signal for storing and outputting data generated from a CPU by receiving a driving voltage supplied from the power supply and receiving a latch signal LATCH output from the latch. A physical EPROM driving circuit for outputting and a write / read signal outputted from the physical EPROM driving circuit are applied to store and output data according to sales contents generated from a CPU. It is characterized by consisting of a physical (Fiscal) EPROM.

1 is a block diagram showing the configuration of a physical EPROM drive device according to the present invention,

FIG. 2 is a detailed circuit diagram of a Fiscal EPROM driving device shown in FIG. 1;

3 is a waveform diagram of a write control signal of a physical EPROM according to the present invention;

4 is a waveform diagram of a read control signal of a physical EPROM according to the present invention.

When the present invention having such a feature is described with reference to the accompanying drawings.

1 is a block diagram illustrating a configuration of a physical EPROM driving apparatus according to the present invention. As shown, a control signal for processing the sales content, generating data DATA according to the processed result, and controlling the generated data, and an address signal for writing or reading the data. The CPU 11 outputs ADDRESS, the data DATA, the address signal ADDRESS and the control signal CONTROL outputted from the CPU 11 are temporarily stored, and the latch signal LATCH according to the stored signal. Latch (12) for outputting, a power supply 13 for generating and outputting a driving voltage during a circuit operation, and a drive voltage supplied with the driving voltage supplied from the power supply (13) A physical EPROM driving circuit 14 that receives a latch signal LATCH outputted from 12 and outputs a write / read signal for storing and outputting data generated by the CPU 11. ) And the physical EPROM drive circuit 14 Receiving the light emitter is (Write) / read (Read) signal output the stored data in accordance with the selling information generated in the CPU (11) and consists of a local fish (Fiscal) EPROM (15) for outputting.

Referring to the operation according to the configuration as follows.

When the sales contents are input, the CPU 11 generates data according to the simple tax according to the input sales contents. The generated data is applied by the latch 12. The latch 12 receiving the data applies the data to the physical EPROM 15 according to a control signal CONTROL applied from the CPU 11. The latch signal LATCH according to the write control signal CONTROL output from the CPU 11 is output to store data applied by the CPU 11.

The physical EPROM driving circuit 14 receiving the latch signal LATCH output from the latch 12 receives the physical EPROM according to the applied write latch signal LATCH. 15) Data DATA is stored. At this time, the data DATA generated by the CPU 11 to store the data DATA in the physical EPROM 15 is 1 mega bits of physical data through the latch 12. (Fiscal) The data bus is used to store data in the EPROM 15. The data bus signal DATA BUS applied through the data bus is stored according to the address bus signal ADDRESS BUS applied to the physical EPROM 15 via the address bus.

In addition, the CPU 11 outputs a control signal CONTROL according to read in order to read data stored in the physical EPROM 15. The latch 12 receiving the output control signal CONTROL outputs the latch according to the read control signal applied. The output latch signal LATCH is applied by the Fiscal EPROM driving circuit 14.

The physical EPROM driving circuit 14 receiving the latch signal LATCH according to the read signal reads data stored in the physical EPROM 15 according to the applied latch signal LATCH. It is read and applied to the latch 12 again through the data bus. The data bus signal DATA BUS applied through the data bus is applied to the latch 12 and applied to the CPU 11.

In this case, a constant potential level is applied by the power supply 13 to store or output the data bus signal DATA BUS to the physical EPROM 15.

The physical EPROM driving circuit 14 for driving the physical EPROM 15 will now be described in detail with reference to the accompanying drawings.

FIG. 2 is a detailed circuit diagram of the Fiscal EPROM driving device shown in FIG. 1. As shown, a first switching transistor Q1 for switching upon receiving a first latch signal LATCH 1 output from a latch 12 (shown in FIG. 1) and the first switching transistor Q1. And a second switching transistor Q2 for switching and outputting a switching signal according to the switching operation of the first and second switching transistors Q2 and the switching signal output from the second switching transistor Q2. A first reference voltage generator 14a outputting V _CC ) and a switching signal output from the second switching transistor Q2 are applied to maintain a constant level of potential to output a second potential level V _PP . A second reference voltage generator 14c for receiving a voltage generator 14b, a switching signal output from the second switching transistor Q2, and maintaining a potential level at a predetermined level; and the second reference voltage generator 14c. Output from A third switching transistor (Q3) and a second potential level outputted from the first potential level (V _CC) and the potentiometer (14b) output from the first reference voltage group (14a) for switching in accordance with the positive level signal (V _PP ) and the switching operation of the third switching transistor (Q3) and the second latch signal (Latch 2) output from the latch (Latch) 12 is received and output or store data in response to the applied signal Is composed of a physical EPROM 15.

In such a configuration, the first reference voltage generator 14a includes a diode D1 for filtering a switching signal output from the second switching transistor Q2 and a resistor for inducing a switching signal applied through the diode D1. (R4), a diode (D2) that receives and filters a DC voltage (5V), a switching signal induced through the resistor (R4), and a DC voltage (5V) applied through the diode (D2). The Zener diode ZD1 maintains a first potential level V _CC at a constant level.

The voltage generator 14b that receives the switching signal output from the second switching transistor Q2 and outputs the second potential level V _PP receives and filters the switching signal output from the second switching transistor Q2. And a diode D4 to filter by receiving a direct current voltage 5V.

The second reference voltage transformer 14c, which receives the switching signal output from the second switching transistor Q2 and outputs a signal of a predetermined level, has a resistor R5 for receiving and inducing a switching signal, and the resistor R5. Zener diode ZD2 maintains a constant level of potential according to a switching signal induced and applied to the resistor, and resistors R6 and R7 divide the potential of a predetermined level held by the zener diode ZD2. .

Then, the resistor R3 for receiving and inducing the first latch Latch 1 output from the latch 12, the collector resistor R2 of the first switching transistor Q1, and the second switching transistor It consists of a self bias resistor R1 of (Q2).

Referring to the operation according to the configuration as follows.

First, when data according to the sales contents is generated from the CPU 11 (shown in FIG. 1), the generated data is applied to the latch 12. FIG. The latch 12 receiving the data outputs a latch signal LATCH to process the applied data. At this time, if the data is to be stored, the latch signal LATCH outputs the first latch signal LATCH 1 according to data storage. The potential level of the first latch signal LATCH 1 output through the latch 12 is + 5V.

The first latch signal LATCH 1 having a potential level of +5 V is applied to the base terminal of the first switching transistor Q1 through the resistor R3. The first switching transistor Q1 receiving the first latch signal LATCH 1 switches. The second switching transistor Q2 connected to the collector terminal of the first switching transistor Q1 through the resistor R2 is turned on according to the switching operation of the first switch transistor Q1.

When the second switching transistor Q2 is turned on, a DC voltage (+ 12V) applied to the emitter stage is output to the collector stage. At this time, the resistor R1 is used for the self bias. The switching signal according to the DC voltage (+ 12V) output from the collector terminal of the second switching transistor Q2 is filtered out to remove the subcomponents through the diode D1 of the first reference voltage transformer 14a. The switching signal filtered through the diode D1 induces a resistor R4, and the DC voltage (+ 5V) is filtered through the diode D2 and applied.

The switching signal according to the DC voltage (+ 5V) applied through the diode D2 and the DC voltage (+ 12V) applied through the resistor R4 is applied to the Zener diode ZD1 at a predetermined level of the first potential level (V _CC). ) To be applied to the input pin 32 of the physical EPROM 15. In one example, the first potential level V _CC of a predetermined level in the zener diode ZD1 is maintained at + 6.1V and applied to the input pin 32 of the physical EPROM 15.

In addition, the switching signal output from the collector terminal of the second switching transistor Q2 is filtered through the diode D3 in the voltage generator 14b and the direct current voltage through the diode D4 to which the direct current voltage (+5 V) is applied. (+ 12V) is applied to input pin 1 of the physical EPROM 15.

The switching signal output from the collector terminal of the second switching transistor Q2 is induced through the resistor R5 in the second reference voltage generator 14c and the direct current voltage (+ 5.1V) through the zener diode ZD2. Will be maintained. The DC voltage (+ 5.1V) held through the zener diode ZD2 is divided by the resistors R6 and R7 and applied to the base terminal of the third switching transistor Q3. The third switching transistor Q3 that receives the divided voltage through the resistors R6 and R7 receives the DC voltage (+ 5V) through the resistor R8 and turns it on.

When the third switching transistor Q3 is turned on, the program signal applied to the input pin 31 of the physical EPROM 15 ( 0V, which is a low potential level, is input. In addition, the second latch signal Latch 2 output from the latch 12 is clock-enabled to the input pin 22 of the physical EPROM 15. 0, which is a level of low potential, is In addition, a DC voltage (+5.1 V) applied through the resistor R5 is applied to the input pin 24 of the physical EPROM 15. At this time, the DC voltage (+ 5.1V) is the EPROM data output enable signal ( )

As described above, when the condition for storing the data output from the latch 12 to the physical EPROM 15 is satisfied, the data is stored by one byte according to the address bus signal ADDRESS BUS. ) To the EPROM 15. This operation is successively stored in a physical EPROM 15 having a storage capacity of 1 Mega bit.

On the contrary, if a read signal for outputting data from the CPU 11 is output, the latch 12 outputs the first latch signal Latch 1 according to the read signal. At this time, the output first latch signal Latch 1 becomes a low level potential of 0V. The output first latch signal Latch 1 is applied to the base terminal of the first switching transistor Q1 through the resistor R3 to turn off the second switching transistor Q2. When the second switching transistor Q2 is turned off, the first reference voltage generator 14a transfers the DC voltage (+ 5V) applied through the diode D2 to the input pin 32 of the physical EPROM 15. + 5V) is applied.

In addition, the input pin 1 of the Fiscal EPROM 15 through the voltage transformer 14b.

DC voltage (+ 5V) is applied by diode D4. In addition, since the second switching transistor Q2 is turned off, the third switching transistor Q3 is turned off, and the program signal applied to the input pin 31 of the physical EPROM 15 ( ) Is input to + 5V.

In addition, the output enable signal applied through the resistor R5 ( ) Is a low level 0V is input to the input pin 24 of the physical EPROM (15). Finally, the second latch signal LATCH 2 applied from the latch 12 is clock-enabled to the input pin 22 of the physical EPROM 15. DC voltage (+ 5V) is applied.

When this condition is satisfied, data in the physical EPROM 15 is applied to the latch 12 along the data bus and read by the CPU 11.

Referring to the control waveform according to the operation using the accompanying drawings as follows.

3 is a waveform diagram of a write control signal of a physical EPROM according to the present invention. As shown, the waveform (a) shows the address (ADDRESS) signal period. The waveform (b) shows the valid data area DATA IN STABLE and the invalid data area DATA OUT VALID according to the address ADDRESS signal period.

In addition, drive voltages for storing data in the physical EPROM 15 (shown in FIG. 1) are shown in waveforms (c) and (d). As shown, the first potential level V _CC and the second potential level V _PP are 12V and 6V, respectively, in order to store data generated by the CPU 11.

The waveform (e) is a clock enable signal (Input) that is input to the input pin 22 of the physical EPROM (15) The data storage condition shows the low level, and the waveform (bar) shows the program signal () input to the input pin 31 of the physical EPROM 15. ) Indicates the condition of the low potential level.

In addition, an output enable signal (a storage condition) ) Is applied to the high potential level + 5V to the input pin 24 of the Physical EPROM 15.

Accordingly, by satisfying such a condition, the CPU 11 stores the generated data in the physical EPROM 15.

As described above, a control waveform according to a condition for reading data stored in the physical EPROM 15 will be described with reference to the accompanying drawings.

4 is a waveform diagram of a read control signal of a physical EPROM 15 according to the present invention. As shown, waveform (A) shows the effective address area (ADDRESS VALID) of the address signal (ADDRESS) generated when reading data, waveform (B) is a clock enable signal (Clock Enable) signal ( ) Shows low level 0V. In addition, the waveform (C) is an output enable signal ( ) Shows low level 0V, and the waveform (D) is a valid area (VALID OUTPUT) of read data that reads data stored in the physical EPROM 15 according to these conditions. Indicates.

Through this condition, the CPU 11 reads data stored in the physical EPROM 15.

Therefore, the present invention can simply configure a driving circuit for driving a large-capacity EPROM, the circuit configuration is simple, easy to operate and control, and there is an effect of reducing the manufacturing cost during circuit manufacturing.

Claims (6)

A latch for temporarily storing the data DATA, the address signal ADDRESS and the control signal CONTROL output from the CPU, and outputting the latch signal LATCH according to the stored signal, and is supplied from the power supply. A physical EPROM that outputs a write / read signal that receives a driving voltage and receives a latch signal LATCH output from the latch to store and output data generated from a CPU. A physical EPROM that receives a write / read signal outputted from the physical EPROM driving circuit and stores and outputs data according to sales contents generated from a CPU. Fiscal EPROM drive device comprising. The method of claim 1, A physical EPROM driving device further comprising a power supply for supplying power according to a control signal to the physical EPROM driving circuit and the physical EPROM. A first switching transistor Q1 for receiving and switching the first latch signal LATCH 1 output from the latch, and a switch for switching and outputting a switching signal according to a switching operation of the first switching transistor Q1. A first reference voltage source configured to receive a second switching transistor Q2 and a switching signal output from the second switching transistor Q2, and to maintain a potential at a predetermined level to output a first potential level V _CC ; A voltage receiving the switching signal output from the second switching transistor Q2 and maintaining a potential at a predetermined level to output the second potential level V _PP , and a switching signal output from the second switching transistor Q2. A second reference voltage receiving the voltage and maintaining a potential level at a predetermined level, and a third switching transistor configured to switch according to a predetermined level signal output from the second reference voltage generator Requester (Q3), and a switching operation of the first reference voltage group first potential level outputted from the (V _CC) a second potential level (V _PP) output from the said voltage group and the third switching transistor (Q3) And a physical EPROM receiving a second latch signal (Latch 2) output from a latch and outputting or storing data in response to the applied signal. The method of claim 3, wherein The first reference voltage regulator includes a diode D1 for filtering a switching signal output from the second switching transistor Q2, a resistor R4 for inducing a switching signal applied through the diode D1, and a direct current voltage. Is applied to filter the diode (D2), the switching signal induced through the resistor (R4) and the DC voltage (5V) applied through the diode (D2) is applied to a predetermined level of the first potential level (V _CC) (Fiscal) EPROM drive device characterized in that consisting of a Zener diode (ZD1) holding. The method of claim 3, wherein The voltage generator includes a diode EP3 that receives and filters a switching signal output from the second switching transistor Q2 and a diode D4 that receives and filters a DC voltage. drive. The method of claim 3, wherein The second reference voltage generator includes a resistor R5 for receiving and switching a switching signal, a zener diode ZD2 for maintaining a predetermined level of potential according to a switching signal induced and applied to the resistor R5, and the zener diode. A physical EPROM driving device comprising a resistor (R6) and a resistor (R7) for dividing a potential of a predetermined level held by (ZD2).