JPH0675866A - Memory control circuit - Google Patents

Abstract

PURPOSE:To provide the memory control circuit for improving a service life of a memory by minimizing the number of times of rewriting of an EEPROM by making a gate for transferring SRAM data to the EEPROM active, only when a power source of an apparatus is cut off in the case the SRAM data is changed, at the time of changing the data of the memory in which the SRAM and the EEPROM are integrated in one chip. CONSTITUTION:The memory control circuit is constituted so that at the time of transferring data from an EEPROM to an SRAM, or from the SRAM to the EEPROM in a memory in which the SRAM and the EEPROM are integrated in one chip, data 1b of the EEPROM to the SRAM at the time when a power source is turned on, by monostable multivibrator circuits 6, 7 and a RAM data change deciding circuit 11 operated in accordance with an output of a voltage detecting circuit 8 for detecting turn-on and cut-off of a power source of an apparatus, and also, SRAM data 1a is transferred to the EEPROM only when the SRAM data 1a is changed and the power source is cut off, and a backup circuit 5 for secuting the power source by the time required for a transfer time is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an occasional write / read memory (hereinafter referred to as SRAM) which does not require a memory holding operation.
And an electrically rewritable non-volatile memory (hereinafter referred to as EE
(Hereinafter referred to as PROM) on one chip in a memory control circuit.

[0002]

2. Description of the Related Art In recent years, a memory control circuit in which an SRAM and an EEPROM are integrated in one chip has been used to change or store data such as equipment setting conditions and energization time.

A conventional memory control circuit will be described below. 3 and 4 are a block diagram and a timing chart of a conventional memory control circuit.

In FIG. 3, 1 is a memory in which SRAM and EEPROM are integrated in one chip, and 1a is an SRA in the memory.
M data section, 1b is an EEPROM data section in the memory,
1c is a gate for transferring the EEPROM data to the SRAM, 1d is a gate for transferring the SRAM data to the EEPROM, 2 is a signal indicating the address of the SRAM data, and 3 is an input / output of data to / from the SRAM from outside the memory. Control signal, 4 is a data input / output line, 5 is a backup circuit, 6 is a mono-multi circuit that activates the gate of 1c, 7 is a mono-multi circuit that activates the gate of 1d, and 8 is voltage detection of equipment. A circuit, 9 is a power switch of the device, and 10 is a power source of the device. FIG. 4 shows a timing chart of a to e shown in FIG.
a is the power supply voltage of the device, b is the output signal of the voltage detection circuit, and c
Is a backup power supply voltage of the circuit, and d and e are mono-multi output signals.

The operation of the memory control circuit configured as described above will be described below. When the power is turned on by the power switch 9 of the device (see the timing chart a), the voltage detection circuit 8 keeps 0 until the voltage of the device becomes normal.
After V (hereinafter referred to as L level) is output and the voltage becomes normal, the voltage rises to Vcc (hereinafter referred to as H level) (see timing chart b). When the output of b rises from the L level to the H level, the mono-multi circuit 6 operates as EEPR.
A control signal that activates the gate 1c for the time t1 required for transferring the OM data 1b to the SRAM 1a is output (see timing chart d). Since the SRAM data is the setting conditions of the device, the energization time, and the like, a signal 2 (generally an address bus) indicating the data address of the SRAM and a control signal 3 (generally the data input / output) from the outside of the memory are requested according to the request. The SRAM data 1a is read or changed by the data input / output line 4 (generally a data bus) by chip select and read / write signals. Then, when the power switch 9 of the device is cut off, an abnormality in the voltage of the device is detected, and when the voltage drops below a certain value, the output of the voltage detection circuit 8 falls from the H level to the L level (timing chart b). reference).
When the output of b falls from the H level to the L level,
The mono-multi circuit 7 outputs a control signal that activates the gate 1d for the time t2 required to transfer all the data to the EEPROM 1b in order to store the changed SRAM data 1a (see the timing chart e). Further, even if the power of the device is cut off, the backup circuit 5 operates so that the power supply voltage of the memory 1 and the mono-multi circuits 6, 7 is held until the data transfer is completed (see the timing chart c).

[0006]

However, in the above-mentioned conventional configuration, when the power of the device is turned on, the S
Regardless of whether the RAM data is changed or not, the SRAM data is always transferred to the EEPROM when the power is cut off.
The EEPROM cannot transfer data indefinitely, that is, cannot be rewritten, and the rewriting is limited.
It has a drawback of shortening the life of the M part, that is, the memory.

The present invention solves the above-mentioned conventional problems. SRAM data is EEPed each time the power source of the device is cut off.
An object of the present invention is to provide a memory control circuit that significantly improves the life of the EEPROM section, that is, the memory by transferring data to the EEPROM only when the power is shut off when the SRAM data is changed, instead of transferring it to the ROM. And

[0008]

In order to solve the above-mentioned problems, according to the present invention, a circuit having a memory in which an SRAM and an EEPROM are integrated in one chip and data of the EEPROM are transferred to the SRAM when the power of the device is turned on. A first circuit that generates a signal, a second circuit that generates a signal that transfers the data of the SRAM to the EEPROM when the power of the device is shut off, and the second circuit only when the data of the SRAM is changed. And a backup circuit that holds the power of the memory until the transfer is completed even if the power of the device is cut off.

[0009]

By the above means, when the power of the equipment is turned on, E
EPROM data to SRAM, S
Only when the RAM data is changed, the SRAM data is
By outputting the control signal transferred to the EPROM,
The life of the memory can be greatly improved.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

1 and 2 are a block diagram and a timing chart of an embodiment of a memory control circuit according to the present invention.

In FIG. 1, reference numeral 1 is an SRAM and an EEPROM.
A memory that integrates a single chip into the memory, 1a is SR in the memory
AM data part, 1b is an EEPROM data part in the memory, 1c is a gate for transferring the EEPROM data to the SRAM, 1d is a gate for transferring the SRAM data to the EEPROM, and 2 is a signal indicating the address of the SRAM data. Reference numeral 3 is a control signal for inputting / outputting data to / from the SRAM from outside the memory, 4 is a data input / output line, 5 is a backup circuit, 6 is a mono-multi circuit for activating the gate of 1c, and 7 is a gate of 1d. A mono-multi circuit to be activated, 8 is a device voltage detection circuit, 9 is a device power switch, 10 is a device power supply, and 11 is an SRAM data change determination circuit. 2 is shown in FIG.
7A to 7H are timing charts, in which a is the power supply voltage of the device, b is the output signal of the voltage detection circuit, c is the backup power supply voltage of the circuit, d, e, g are mono-multi output signals,
f and h are mono-multi control signals.

The operation of the memory control circuit configured as described above will be described below. When the power is turned on by the power switch 9 of the device (see the timing chart), the voltage detection circuit 8 keeps L until the voltage of the device becomes normal.
After the level is output and the voltage becomes normal, it rises to the H level (see timing chart b). When the output of b rises from L level to H level, the mono-multi circuit 6 outputs a control signal for activating the gate 1c for a time t1 required for transferring the data 1b of the EEPROM to the SRAM 1a (timing chart d reference).
Since the SRAM data is the setting conditions of the device, the energization time, etc., if there is a change in the data,
A signal 2 (generally an address bus) indicating a data address of the SRAM and a control signal 3 (generally a chip select and a read / write signal) for inputting / outputting the data, and an SRA by a data input / output line 4 (generally a data bus).
The M data 1a is changed. At this time, the SARAM data change determination circuit 11 outputs a control signal for activating the mono-multi circuit 7 (see timing chart f). Then, when the power switch 9 of the device is cut off, an abnormality in the voltage of the device is detected, and when the voltage drops below a certain value, the output of the voltage detection circuit 8 falls from the H level to the L level (timing chart b). reference). When the output of b falls from the H level to the L level, the mono-multi circuit 7 opens the gate 1d for the time t2 required to transfer all the data to the EEPROM 1b in order to store the changed SRAM data 1a. A control signal to activate is output (see timing chart e).

Even if the power supply to the equipment is cut off, the backup circuit 5 waits until the transfer of the data is completed.
The memory 1 and the mono-multi circuits 6, 7 and the SRAM data change determination circuit operate so as to hold the power supply voltage (see timing chart c).

On the other hand, if there is no change in the setting conditions of the device, the energization time, etc., the SRAM data is not changed. At this time, the SRAM data change determination circuit 11 outputs a control signal for deactivating the mono-multi circuit 7 (see timing chart h). Then, when the power switch 9 of the device is cut off, an abnormality in the voltage of the device is detected, and when the voltage drops below a certain value, the output of the voltage detection circuit 8 falls from the H level to the L level (timing chart b However, the mono-multi circuit 7 includes a gate 1d for transferring the SRAM data 1a to the EEPROM 1b.
Does not output a control signal for activating (see timing chart g).

As described above, according to this embodiment, the voltage detection circuit for detecting the power-on or the power-off of the device, and the mono-multi circuit for activating the gate for transferring the EEPROM data to the SRAM according to the output, Also, SR
Mono-multi circuit that activates the gate that transfers AM data to the EEPROM, and SRAM data change determination circuit that operates the mono-multi circuit that activates the gate that transfers SRAM data to the EEPROM only when there is a change in the SRAM data By providing the backup circuit, the SRAM data is not transferred to the EEPROM each time the power supply of the device is cut off, but the EEPROM is changed only when the power supply is cut off when the SRAM data is changed.
It goes without saying that the life of the EEPROM section, that is, the memory is significantly improved by transferring the data to M.
Further, the data can be surely saved even when the power of the device is cut off.

[0017]

As described above, according to the present invention, the SRAM
And a circuit having a memory in which the EEPROM is integrated in one chip, and a first circuit for generating a signal for transferring the data of the EEPROM to the SRAM when the power of the device is turned on.
When the power of the equipment is cut off, the SRAM data is EEPR
A second circuit for generating a signal to be transferred to the OM, and the SR
A third circuit that validates the signal of the second circuit only when the AM data is changed, and a backup that keeps the circuit power until the transfer is completed even if the power of the device is cut off. By providing the circuit, it is possible to realize an excellent memory control circuit which can significantly improve the life of the memory and can surely save the data even when the power of the device is cut off.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory control circuit according to an embodiment of the present invention.

[FIG. 2] Same timing chart

FIG. 3 is a block diagram of a conventional memory control circuit.

FIG. 4 is a timing chart of the same.

[Explanation of symbols]

 1 memory 1a SRAM data section in memory 1b EEPROM data section in memory 1c Gate for transferring EEPROM data to SRAM 1d Gate for transferring SRAM data to EEPROM 5 Backup circuit 6, 7 Mono-multi circuit 8 Power detection circuit 9 Equipment Power switch 10 Power supply for equipment 11 SRAM data change determination circuit

Claims (1)

[Claims] 1. A circuit having a memory in which a non-volatile memory that does not require a memory holding operation and a non-volatile memory that is electrically rewritable in one chip are integrated, and data of the non-volatile memory when a device is powered on. The first circuit that generates a signal for transferring to the memory for reading and writing memory that does not require the memory holding operation, and the data in the memory for writing and reading the memory that does not require the memory holding operation to the non-volatile memory when the power of the device is cut off. A second circuit for generating a signal to be transferred, and a third circuit for validating the signal of the second circuit only when the data of the occasional write / read memory which does not require the memory holding operation is changed. A memory control circuit having a backup circuit that holds the power supply of the circuit until the transfer is completed even when the power supply of the device is cut off.