JPS61279138A - Mounting structure of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the short circuit between an IC and the edge of a solder and to alleviate stress due to difference in thermal expansions between a substrate and the IC, by making a basis metal layer, which is included in a solder bump, thick, and reducing the volume of the solder in one bump. CONSTITUTION:An IC 3 with a solder bump is bonded to a resin circuit substrate 6 having a conducting pattern 7 with a face down attitude. At this time, the thickness of the core 1 of a basis metal such as copper, which is included in the solder bump 2, is made to be 20-35mum. Then, at the time of bonding, the solder layer of several tens of mum remains between the core 1 of the metal and the conducting pattern immediately beneath the bump. After the bonding, the solder is solidified. Then the short circuit between the IC 3 and the edge of the solder is prevented. The stress due to the difference in thermal expansions between the substrate 6 and the IC 3 is alleviated.

Description

[Detailed Description of the Invention] [Field of Application in Parallel Work] The present invention relates to a mounting structure of a face-down bonding type semiconductor device, and particularly to a mounting structure of a small semiconductor device mainly made of a resin substrate such as a circuit block for a wristwatch. Regarding the implementation structure.

[Conventional technology]

Conventionally, as shown in FIG.
A barrier metal such as the following is grown by a method such as vaporization, sputtering, or plating, and then a solder layer 12 of Pb:8% with a ratio of 95:5 or 426 is formed thereon by a method such as plating or distillation. Then, I formed solder bumps for face-down bonding, but #! - The dimensional specifications of the pants, that is, the thickness TI of the base metal core 11 and the height T of the solder bump as shown in FIG. The volume of the solder and solder are determined by taking into account compatibility with the ceramic substrate, since the face-down mounting structure that includes solder bumps has begun to be applied mainly to industrial hybrid integrated circuits using ceramic substrates. ,
The above specifications have also been used as a guideline when implementing face-down mounting using solder bumps on other boards.

That is, as shown in FIG. 4(C), a solder flow prevention guard 20 is provided in advance on the conductive pattern 14 on the ceramic substrate 17, and the solder bumps 18 are aligned face-down and then thermally bonded. The solder does not flow over the turns and the height of the bump after bonding can be maintained at about 11 to 100 microns. In addition, in order to secure as much effective solder volume as possible for the solder bump 18 itself, the base metal layer such as copper is made as thin as several micrometers. Bump specifications are determined based on the principle that stress is absorbed by the solder bump and the reliability of the joint is ensured.

[Problem that the invention seeks to solve]

However, when trying to apply the conventional face-down bonding method used on solder bumps to circuit mounting for wristwatches mainly using resin substrates, we decided to use dams to prevent solder flow due to the low cost required for watch substrates. It is difficult to provide a pattern (increase in process and cost), and it is difficult to provide a pattern suitable for the pattern on a resin substrate (good positioning accuracy, simple and cheap).
It turned out that there was no way to form a dam. For example, the method of printing the solder resist after turning is simple, but it costs a certain amount of money, and the printing position accuracy is around ±0.3 (taking into account resin sag). It is far from less than ±0°1.In any case, from the viewpoint of the manufacturing process of resin substrates such as glass epoxy and polyimide, the reality is that an inexpensive and accurate dam forming method has been found for a long time. Using solder bumps having the specifications shown in Fig. 1, face-down bonding (in this case, solder bumps) is performed on the pattern 14 without a solder flow prevention dam on the resin substrate 16 as shown in Fig. 4(b). When the solder flows along the pattern 14 and the tip penetrates thinly as if eating the gold on the pattern, the solder that flows out is collected at the edge 19 of exactly 20 chips, as shown in Figure 8. It was found that the S under the passivation film 4 (shown in Figure 1) contacts the chip body and causes electrical failure.The incidence rate is
11" shown in FIG. 8, 1 is 5 to 10μ, T,
It varies from 60 to 100μ, and when adjusting the solder volume, it is about 20 to 5 inches, and considering the dimensional tolerance of bumps, variations in the surface treatment state of the board pattern, etc., it is not a structure that can be used stably for mass production. do not have. Conventional as above.

The solder bump structure was mainly determined based on the relationship with ceramic substrates, and was used as is for substrates made of other materials, so when applied to inexpensive substrates that do not have solder flow prevention dams, solder flows along the pattern and stagnates. There was a drawback that an electrical short could occur between the solder and the IC end.

Therefore, in order to solve these conventional drawbacks, the present invention secures thermal stress consistency with the resin-based substrate and prevents edge shorting between the solder end and the solder even on a substrate that does not have a solder flow prevention dam. The purpose is to provide a mounting structure with zero layers of solder bumps.

[Means for solving problems]

In order to solve the above problems, the invention is to thicken the underlying metal layer in the solder bumps, and to reduce the solder volume in one bump so that edge shorts between the IC ends and the solder are less likely to occur. At the same time, the solder body PA was selected to be able to alleviate the stress caused by the difference in thermal expansion between the substrate and the IC, thereby ensuring reliability as a consumer semiconductor device.

[Effect]

When a solder bump configured as described above is heated from below the substrate or is face-down bonded by a flow bonding method, the solder in the solder first flows along the conductive pattern of the substrate, but the solder solder flows inside the solder bump. Since the upper surface of the base metal layer (core) such as copper is flat, a solder layer of several tens of microns remains between this metal core and the conductive pattern directly under the bump due to the optical surface tension of the solder, which causes the solder layer to remain directly in the process. Since no external force is applied, the solder O is in a state of floating on the melted solder bump), and solidifies upon completion of the bonding. The presence of the solder layer of several tens of micrometers relieves the stress after bonding between the workpiece and the resin substrate to a degree that cannot be said to be sufficient, and the resin substrate itself has thermal softening properties compared to ceramic. Furthermore, in ordinary circuit packaging for watches, sealing and reinforcing the IC with resin makes it possible to obtain bonding reliability against stress such as thermal stress. In addition, because the thickness of the base metal layer (core) has increased, the solder layer of 10 μm remains on the element, and the volume of solder has decreased, edge shorts between the C edge and the solder on the conductive pattern are prevented. It is possible to do so.

〔Example〕

Embodiments of the present invention will be described below based on all the drawings.
In FIG. 1, a solder bump on an IC chip 8 consists of a base metal core 1 such as copper and a solder layer 2, and is numeral 111 in the figure. l is 3
0μ, T8 is 85μ. Note that the size of the hole is 2rrrm 0 to 3 mm for analog wristwatches, so it can be said that the influence of thermal stress during bonding is relatively small.Next, Figure 2 shows the mounting structure of the present invention. For example,
Place the bonding wiring pattern 7 face-down on a solder bump attachment 08' on a printed wiring board 6 made of a resin base material such as heat-resistant glass epoxy or glass polyimide, and
When bonding is performed by heating the substrate from below or using a flow method, as explained in the section of the above-mentioned operation, a solder layer of about 20 μm remains between the base metal core 1 and the pattern 7 due to the surface tension of the solder. That is, t'=20μ, therefore t=approximately 50μ, ensuring a gap of 50μ between the IC chip and the wiring pattern 7 on the board, and the solder volume also being 40μ as described later. ~120xlO""'Order 3
(Conventional solder volume is 200 XIC"" tr
An' before and after] There is no need to worry about edge shorts between the IC end and the solder on pattern 7.

Work with solder bumps on boards without solder flow prevention dams
In bonding, thickening the underlying metal layer such as copper is an essential condition for preventing edge shorts, but the recommended range of thickness is from 20μ at the bottom to 20μ at the highest due to variations in the plating process and the actual effect of preventing edge shorts. It has been confirmed through tests etc. that it is 35μ. Base metal core volume at that time (■1)
The relationship between and the solder volume (V) is as shown in FIG.

Base metal core thickness: 20-35μ Solder bump height: 75-100μ Base metal core diameter: φ160μ When the plating is varied, the range in which edge shorting is good is shown in the shaded area in the figure. That is, the solder volume is 40 to 120xlO-813
It is also a necessary condition. V at that time:
The range of the ratio of V from 2.5:1 to 0°5:1 is a guideline for calculating other parameters (for example, bump diameter) when parameters such as the thickness of the base metal core and the solder volume are given. becomes.

Next, although not particularly shown, in face-down bonding, when reflow bonding is performed by heating the IC chip from the back side (upper collar in Figure 2) with a heater chip, a certain amount of pressure is applied to the bumps (50°C). ~150.97'
), but if you set the bonding temperature and solder volume appropriately so that the solder does not flow too much, you can ensure the thickness of the metal core and ensure the gap between the workpiece 0 and the board pattern. The occurrence of edge shorts can be suppressed by making the thickness at least 5 μm or more. It goes without saying that the above method using a heater chip can also be applied to face-down bonding to a flexible printed wiring board made of polyimide or the like.

〔Effect of the invention〕

By adopting the mounting structure as described above, the present invention has the advantage that even when face-down bonding using the solder bump method is applied to a substrate made of an inexpensive material such as °C that does not have a dam to prevent solder flow, IC edges and patterns can be easily bonded. This has a remarkable effect of improving quality by preventing edge shorts with solder that has flowed into the solder, and also ensures sufficient bonding reliability for consumer use such as wristwatches.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a solder bump according to the present invention. Fig. 2 is a mounting structure according to the present invention. Fig. 8 is a cross-sectional view of a conventional solder bump, Fig. 4 is a conventional mounting structure, and Fig. 5 is a diagram of the relationship between solder volume and base metal core volume according to the present invention. It is. 1, 11, Base metal core 2. +2. , solder layer 8
．． 13. , Engineering ○ Tetsu 7”6, 16., Board 7.14.,
Wiring pattern Applicant: Seiko Electronics Industry Co., Ltd. Figure 1 Figure 2/3 1 Figure 3 Figure 5

Claims (3)

[Claims] (1) In a semiconductor device formed by face-down bonding an IC with solder bumps to a resin circuit board having a conductive pattern, the thickness of the base metal core such as copper contained in the solder bumps must be 20 to 35 μm. A mounting structure for a semiconductor device characterized by: (2) The semiconductor device mounting structure according to claim 1, wherein the upper surface of the base metal core is flat. (3) The mounting structure for a semiconductor device according to claim 1, wherein the volume of solder constituting the solder bumps is 40 to 120 (×10^-^5 mm^3) per bump.