JPS58202540A - Method of bonding fine positioning by stand-off - Google Patents

Method of bonding fine positioning by stand-off

Info

Publication number
JPS58202540A
JPS58202540A JP8611182A JP8611182A JPS58202540A JP S58202540 A JPS58202540 A JP S58202540A JP 8611182 A JP8611182 A JP 8611182A JP 8611182 A JP8611182 A JP 8611182A JP S58202540 A JPS58202540 A JP S58202540A
Authority
JP
Japan
Prior art keywords
stand
bumps
fine positioning
substrate
positioning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8611182A
Other languages
Japanese (ja)
Inventor
Yoshiaki Takeuchi
Koichi Fujiwara
Shigeyuki Tsurumi
Isamu Odaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP8611182A priority Critical patent/JPS58202540A/en
Publication of JPS58202540A publication Critical patent/JPS58202540A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components

Abstract

PURPOSE:To improve the accuracy of positioning by a method weherin the positioning of connecting bumps is performed by utilizing the stand-off between an IC device and a wiring substrate. CONSTITUTION:When the IC device 1 and the wiring substrate 2 are connected by the bumps 5 of solder, etc. in a state of opposition, a plurality of recesses 7 are provided either on the device or on the substrate 2, and the stand-off 3 of a projection is provided at the position opposed to the recess 7 on the other. Then, since the projection 3 and the recess 7 are not fitted each other in the case of generation of slippage at the position of the bumps 5, difference generates to the gap between the device 1 and the substrate 2, and therefore the positional displacement can be judged by the measurement of this gap.
JP8611182A 1982-05-21 1982-05-21 Method of bonding fine positioning by stand-off Pending JPS58202540A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8611182A JPS58202540A (en) 1982-05-21 1982-05-21 Method of bonding fine positioning by stand-off

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8611182A JPS58202540A (en) 1982-05-21 1982-05-21 Method of bonding fine positioning by stand-off

Publications (1)

Publication Number Publication Date
JPS58202540A true JPS58202540A (en) 1983-11-25

Family

ID=13877585

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8611182A Pending JPS58202540A (en) 1982-05-21 1982-05-21 Method of bonding fine positioning by stand-off

Country Status (1)

Country Link
JP (1) JPS58202540A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6255996A (en) * 1985-09-05 1987-03-11 Nec Corp Wiring board
JPS6411025U (en) * 1987-07-10 1989-01-20
US4818728A (en) * 1986-12-03 1989-04-04 Sharp Kabushiki Kaisha Method of making a hybrid semiconductor device
JPH0191320U (en) * 1987-12-09 1989-06-15
US4874721A (en) * 1985-11-11 1989-10-17 Nec Corporation Method of manufacturing a multichip package with increased adhesive strength
JPH06295937A (en) * 1993-03-26 1994-10-21 Nec Corp Mounting method of photoelectric element

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6255996A (en) * 1985-09-05 1987-03-11 Nec Corp Wiring board
US4874721A (en) * 1985-11-11 1989-10-17 Nec Corporation Method of manufacturing a multichip package with increased adhesive strength
US4818728A (en) * 1986-12-03 1989-04-04 Sharp Kabushiki Kaisha Method of making a hybrid semiconductor device
JPS6411025U (en) * 1987-07-10 1989-01-20
JPH0191320U (en) * 1987-12-09 1989-06-15
JPH06295937A (en) * 1993-03-26 1994-10-21 Nec Corp Mounting method of photoelectric element

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